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WO2025084065A1 - Couche mince semi-conductrice à oxyde, transistor à couches minces et cible de pulvérisation - Google Patents

Couche mince semi-conductrice à oxyde, transistor à couches minces et cible de pulvérisation Download PDF

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WO2025084065A1
WO2025084065A1 PCT/JP2024/033410 JP2024033410W WO2025084065A1 WO 2025084065 A1 WO2025084065 A1 WO 2025084065A1 JP 2024033410 W JP2024033410 W JP 2024033410W WO 2025084065 A1 WO2025084065 A1 WO 2025084065A1
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thin film
oxide semiconductor
atm
atoms
film transistor
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元隆 越智
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Kobelco Research Institute Inc
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10P14/60—

Definitions

  • the present disclosure relates to oxide semiconductor thin films, thin film transistors, and sputtering targets.
  • Amorphous oxide semiconductors have higher carrier mobility when forming thin film transistors (TFTs) than amorphous silicon semiconductors, for example.
  • Amorphous oxide semiconductors also have a large optical band gap and are highly transparent to visible light.
  • thin films of amorphous oxide semiconductors can be formed at lower temperatures than amorphous silicon semiconductors. Taking advantage of these characteristics, amorphous oxide semiconductor thin films are expected to be applied to next-generation large displays that can be driven at high speeds with high resolution, and flexible displays that use resin substrates, which require film formation at low temperatures.
  • the present disclosure has been made based on the above-mentioned circumstances, and aims to provide an oxide semiconductor thin film that has high mobility and light stress resistance, as well as excellent S value and switching characteristics when a transistor is formed, a thin film transistor using this oxide semiconductor thin film, and a sputtering target for forming this oxide semiconductor thin film.
  • the inventors discovered that by controlling the number of atoms and the ratio of the number of atoms in a thin oxide semiconductor film containing In, Zn, and Fe within a predetermined range, it is possible to obtain an oxide semiconductor thin film for thin film transistors that has high carrier mobility and light stress resistance that were previously thought to be unfeasible according to the common sense of engineers in this field, and that has excellent S-values and switching characteristics, and thus completed the invention disclosed herein.
  • the oxide semiconductor thin film according to one embodiment of the present disclosure is an oxide semiconductor thin film containing metal elements, the metal elements being composed of In, Zn, Fe and unavoidable impurities, the number of In atoms being 50 atm% or more and 80 atm% or less, the number of Zn atoms being 20 atm% or more and 48 atm% or less, and the number of Fe atoms being 1.5 atm% or more and 2.5 atm% or less, relative to the total number of In, Zn and Fe atoms, and the ratio of the number of In atoms to Zn atoms, In/Zn, being 1.5 atm% or more and 2.5 or less.
  • the metal elements being composed of In, Zn, Fe and unavoidable impurities
  • the number of In atoms being 50 atm% or more and 80 atm% or less
  • the number of Zn atoms being 20 atm% or more and 48 atm% or less
  • the number of Fe atoms being 1.5 atm% or more and 2.5 atm%
  • a thin-film transistor according to another aspect of the present disclosure is a thin-film transistor having the oxide semiconductor thin film of the present disclosure, and is used in an organic EL display.
  • a sputtering target is used for forming an oxide semiconductor thin film and contains metal elements, the metal elements being composed of In, Zn, Fe and unavoidable impurities, the number of In atoms being 50 atm% or more and 80 atm% or less, the number of Zn atoms being 20 atm% or more and 48 atm% or less, and the number of Fe atoms being 1.5 atm% or more and 2.5 atm% or less, relative to the total number of In, Zn and Fe atoms, and the ratio of the number of In atoms to Zn atoms, In/Zn, being 1.5 atm% or more and 2.5 atm% or less.
  • the oxide semiconductor thin film of the present disclosure has high mobility and light stress resistance, as well as excellent S value and switching characteristics when a transistor is formed.
  • the thin film transistor of the present disclosure using this oxide semiconductor thin film has high mobility and light stress resistance, as well as excellent S value and switching characteristics.
  • the sputtering target of the present disclosure can form this oxide semiconductor thin film.
  • FIG. 1 is a schematic cross-sectional view showing a thin film transistor according to an embodiment of the present disclosure formed on a substrate surface.
  • An oxide semiconductor thin film according to an embodiment of the present disclosure is an oxide semiconductor thin film containing metal elements, the metal elements being composed of In, Zn, Fe, and unavoidable impurities, in which, relative to the total number of In, Zn, and Fe atoms, the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more and 2.5 atm% or less, and the ratio of the number of In atoms to the number of Zn atoms, In/Zn, is 1.5 to 2.5.
  • the oxide semiconductor thin film has high light stress resistance because the atomic numbers of In and Zn are within the above range and the atomic number of Fe is equal to or greater than the above lower limit.
  • the oxide semiconductor thin film has an atomic number of Fe equal to or less than the above upper limit, so that the carrier mobility can be increased when a thin film transistor is formed using the oxide semiconductor thin film.
  • the atomic number ratio of In/Zn is equal to or greater than the above lower limit, so that the S value can be increased, and because it is equal to or less than the above upper limit, so that the switching characteristics can be excellent.
  • a thin-film transistor according to another aspect of the present disclosure is a thin-film transistor having the oxide semiconductor thin film described in (1) above, and is used in an organic electroluminescence display.
  • the thin-film transistor has the oxide semiconductor thin film, and therefore has high mobility and light stress resistance, as well as excellent S value and switching characteristics. Therefore, the thin-film transistor is suitable for use in organic EL displays.
  • the S value is preferably 0.4 V/dec or more and 1.0 V/dec or less, and the threshold voltage is preferably 0.6 V or more.
  • the carrier mobility is preferably more than 25 cm 2 /Vs.
  • the thin film transistor can be suitably used in, for example, next-generation large-sized organic EL displays that require high speed.
  • a sputtering target according to another embodiment of the present disclosure is used for forming an oxide semiconductor thin film and contains metal elements, the metal elements being composed of In, Zn, Fe and unavoidable impurities, the number of In atoms being 50 atm% or more and 80 atm% or less, the number of Zn atoms being 20 atm% or more and 48 atm% or less, and the number of Fe atoms being 1.5 atm% or more and 2.5 atm% or less, relative to the total number of In, Zn and Fe atoms, and the ratio of the number of In atoms to Zn atoms, In/Zn, being 1.5 atm% or more and 2.5 atm% or less.
  • the metal elements being composed of In, Zn, Fe and unavoidable impurities, the number of In atoms being 50 atm% or more and 80 atm% or less, the number of Zn atoms being 20 atm% or more and 48 atm% or less, and the number of Fe atoms being 1.5 atm%
  • the sputtering target contains In, Zn, and Fe whose atomic numbers are within the above ranges, and the ratio of the atomic numbers of In/Zn is within the above range. Therefore, by forming an oxide semiconductor thin film using the sputtering target and then forming a thin film transistor on the oxide semiconductor thin film, it is possible to manufacture a thin film transistor that has excellent S value and switching characteristics in addition to high mobility and light stress resistance.
  • carrier mobility refers to the field effect mobility in the saturation region of a thin-film transistor
  • field effect mobility refers to a value calculated by ⁇ FE [m 2 /Vs] shown in the following formula (1) in the saturation region (Vg>Vd-Vth) of the current-voltage characteristics of a thin-film transistor, where Vg [V] is the gate voltage, Vth [V] is the threshold voltage, Id [A] is the drain current, L [m] is the channel length, W [m] is the channel width, and C ox [ F ] is the capacitance of the gate insulating film.
  • the "threshold voltage" of a thin film transistor refers to the gate voltage at which the drain current of the transistor becomes 10 -9 A.
  • the "S value" of a thin-film transistor refers to the minimum change in gate voltage required to increase the drain current by one order of magnitude.
  • the thin film transistor shown in Fig. 1 can be used in the manufacture of display devices such as next-generation large displays and flexible displays, etc.
  • the thin film transistor is preferably used in organic EL displays.
  • the thin-film transistor is a bottom-gate type transistor formed on the surface of the substrate X.
  • the thin-film transistor has a gate electrode 1, a gate insulating film 2, an oxide semiconductor thin film 3, an ESL (Etch Stop Layer) protective film 4, source and drain electrodes 5, a passivation insulating film 6, and a conductive film 7.
  • ESL Etch Stop Layer
  • the substrate X is not particularly limited, but may be, for example, a substrate used in a display device. Such substrate X may be a transparent substrate such as a glass substrate or a silicone resin substrate.
  • the glass used for the glass substrate is not particularly limited, but may be, for example, alkali-free glass, high strain point glass, soda lime glass, etc.
  • a metal substrate such as a stainless steel thin film or a resin substrate such as a polyethylene terephthalate (PET) film may also be used as the substrate X.
  • PET polyethylene terephthalate
  • the average thickness of the substrate X is preferably 0.3 mm or more and 1.0 mm or less from the viewpoint of processability. Furthermore, the size and shape of the substrate X are appropriately determined according to the size and shape of the display device or the like to be used.
  • the "average thickness” refers to the average value calculated by measuring the thickness at any 10 points.
  • the gate electrode 1 is formed on the surface of the substrate X and has electrical conductivity.
  • the thin film constituting the gate electrode 1 is not particularly limited, but may be an Al alloy or an Al alloy having a thin film or alloy film of Mo, Cu, Ti, or the like laminated on the surface of the Al alloy.
  • the shape of the gate electrode 1 is not particularly limited, but from the viewpoint of controllability of the channel length and channel width, a rectangular shape in plan view with the channel length and channel width directions of the thin film transistor are preferable.
  • the size of the gate electrode 1 may be any size that can ensure the channel length and channel width of the thin film transistor.
  • the channel length direction of the thin film transistor is the opposing direction of the source electrode 5a and drain electrode 5b of the thin film transistor.
  • the channel width direction of the thin film transistor is the direction perpendicular to the channel length direction of the thin film transistor and parallel to the surface of the substrate X.
  • the lower limit of the average thickness of the gate electrode 1 is preferably 50 nm, and more preferably 170 nm.
  • the upper limit of the average thickness of the gate electrode 1 is preferably 500 nm, and more preferably 400 nm. If the average thickness of the gate electrode 1 is less than the lower limit, the resistance of the gate electrode 1 is high, and therefore there is a risk that the power consumption of the gate electrode 1 will increase and that disconnection will be more likely to occur. Conversely, if the average thickness of the gate electrode 1 exceeds the upper limit, it becomes difficult to planarize the gate insulating film 2 and the like laminated on the surface side of the gate electrode 1, and there is a risk that the characteristics of the thin film transistor will deteriorate.
  • the gate insulating film 2 is laminated on the front surface side of the substrate X so as to cover the gate electrode 1.
  • the thin film constituting the gate insulating film 2 is not particularly limited, and examples thereof include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a metal oxide film such as Al 2 O 3 or Y 2 O 3.
  • the gate insulating film 2 may have a single layer structure of these thin films, or a multilayer structure in which two or more types of thin films are laminated.
  • the shape of the gate insulating film 2 is not limited as long as it covers the gate electrode 1.
  • the gate insulating film 2 may cover the entire surface of the substrate X.
  • the lower limit of the average thickness of the gate insulating film 2 is preferably 50 nm, more preferably 100 nm.
  • the upper limit of the average thickness of the gate insulating film 2 is preferably 300 nm, more preferably 250 nm. If the average thickness of the gate insulating film 2 is less than the lower limit, the withstand voltage of the gate insulating film 2 may be insufficient, and the gate insulating film 2 may break down due to application of a gate voltage. Conversely, if the average thickness of the gate insulating film 2 exceeds the upper limit, the capacitance of the capacitor formed between the gate electrode 1 and the oxide semiconductor thin film 3 may be insufficient, and the drain current may be insufficient. Note that when the gate insulating film 2 has a multi-layer structure, the "average thickness of the gate insulating film" refers to the average thickness of the total of the layers.
  • the oxide semiconductor thin film 3 itself is another embodiment of the present disclosure.
  • the oxide semiconductor thin film 3 is an oxide semiconductor thin film containing metal elements.
  • the metal elements are composed of In, Zn, Fe, and unavoidable impurities. That is, the oxide semiconductor thin film 3 does not substantially contain metal elements other than In, Zn, and Fe.
  • the lower limit of the number of In atoms relative to the total number of In, Zn, and Fe atoms is 50 atm%, more preferably 55 atm%, and even more preferably 60 atm%.
  • the upper limit of the number of In atoms is 80 atm%, more preferably 75 atm%, and even more preferably 70 atm%. If the number of In atoms is less than the lower limit, the carrier mobility of the thin film transistor may decrease. Conversely, if the number of In atoms exceeds the upper limit, the leakage current of the oxide semiconductor thin film 3 may increase or the threshold voltage may shift to the negative side, causing the oxide semiconductor thin film 3 to become conductive.
  • the lower limit of the number of Zn atoms relative to the total number of In, Zn, and Fe atoms is 20 atm%, more preferably 25 atm%, and even more preferably 30 atm%.
  • the upper limit of the number of Zn atoms is 48 atm%, more preferably 45 atm%, and even more preferably 40 atm%. If the number of Zn atoms is less than the lower limit, the number of other metal atoms will be relatively large, and there is a risk of the material becoming a conductor. Conversely, if the number of Zn atoms exceeds the upper limit, the carrier concentration will be suppressed, and there is a risk of the carrier mobility of the thin film transistor decreasing.
  • the lower limit of the number of Fe atoms relative to the total number of In, Zn, and Fe atoms is 1.5 atm%, more preferably 1.6 atm%, and even more preferably 1.7 atm%.
  • the upper limit of the number of Fe atoms is 2.5 atm%, more preferably 2.4 atm%, and even more preferably 2.3 atm%. If the number of Fe atoms is less than the lower limit, there is a risk of a large threshold voltage shift due to light irradiation. Conversely, if the number of Fe atoms exceeds the upper limit, there is a risk of the carrier concentration being suppressed, and the carrier mobility of the thin film transistor being reduced.
  • the lower limit of the ratio of the number of In atoms to Zn atoms, In/Zn is 1.5, more preferably 1.6, and even more preferably 1.7.
  • the upper limit of the In/Zn atomic ratio is 2.5, more preferably 2.4, and even more preferably 2.3. If the In/Zn atomic ratio is less than the lower limit, the S value and carrier mobility may decrease. Conversely, if the In/Zn atomic ratio exceeds the upper limit, good switching characteristics may not be obtained.
  • the planar shape of the oxide semiconductor thin film 3 is not particularly limited, but from the viewpoint of controllability of the channel length and channel width of the thin film transistor, a shape similar to that of the gate electrode 1 is preferable.
  • the size of the oxide semiconductor thin film 3 in a planar view may be any size that can ensure the channel length and channel width of the thin film transistor.
  • the size of the oxide semiconductor thin film 3 in a planar view is preferably smaller than the size of the gate electrode 1 in a planar view in order to reliably dispose the oxide semiconductor thin film 3 directly above the gate electrode 1.
  • the lower limit of the difference in the side lengths in the channel direction and the channel width direction between the oxide semiconductor thin film 3 and the gate electrode 1 is preferably 2 nm, more preferably 4 nm.
  • the upper limit of the difference in the side lengths is preferably 10 nm, more preferably 8 nm.
  • the difference in the side lengths is less than the lower limit, a part of the oxide semiconductor thin film 3 may deviate from directly above the gate electrode 1 due to a patterning shift or the like, which may result in a deterioration in the flatness of the oxide semiconductor thin film 3 and a deterioration in the characteristics of the thin film transistor. Conversely, if the difference in the side lengths exceeds the upper limit, the thin film transistor may become unnecessarily large.
  • the average thickness of the oxide semiconductor thin film 3 can be determined based on the conditions under which the drain current can be turned off when the oxide semiconductor thin film 3 is used as a switching element. Specifically, it is preferable that the inside of the oxide semiconductor thin film 3 is completely depleted by applying a gate voltage. For this purpose, it is preferable that the average thickness t ch [m] of the oxide semiconductor thin film 3 satisfies the relationship of the following formula (2) with respect to the carrier concentration N C [m ⁇ 3 ], where ⁇ OX is the dielectric constant of the insulating film, ⁇ AOS is the dielectric constant of the semiconductor, ⁇ f [eV] is the Fermi level of the semiconductor, and q [C] is the electronic charge. From the viewpoint of the relationship between the following formula (2) and the carrier concentration described later, and the control accuracy of the film thickness distribution when the oxide semiconductor thin film 3 is manufactured, the average thickness of the oxide semiconductor thin film 3 can be, for example, 20 nm to 60 nm.
  • the cross section of the oxide semiconductor thin film 3 in the thickness direction may be tapered toward the substrate X.
  • the taper angle is preferably 30° or more and 40° or less.
  • the lower limit of the carrier concentration of the oxide semiconductor thin film 3 is preferably 1 ⁇ 10 12 cm ⁇ 3 , more preferably 1 ⁇ 10 13 cm ⁇ 3 , and even more preferably 1 ⁇ 10 14 cm ⁇ 3 .
  • the upper limit of the carrier concentration of the oxide semiconductor thin film 3 is preferably 1 ⁇ 10 20 cm ⁇ 3 , more preferably 1 ⁇ 10 19 cm ⁇ 3 , and even more preferably 1 ⁇ 10 18 cm ⁇ 3 . If the carrier concentration of the oxide semiconductor thin film 3 is less than the lower limit, the drain current of the thin film transistor may be insufficient.
  • the carrier concentration of the oxide semiconductor thin film 3 exceeds the upper limit, it becomes difficult to completely deplete the inside of the oxide semiconductor thin film 3, so that the threshold voltage may shift to the negative side, and the thin film transistor may not function as a switching element.
  • the hole mobility of the oxide semiconductor thin film 3 is preferably more than 25 cm 2 /Vs, more preferably more than 27 cm 2 /Vs, and still more preferably more than 30 cm 2 /Vs. If the hole mobility of the oxide semiconductor thin film 3 is below the lower limit, the switching characteristics of the thin film transistor may be degraded.
  • the upper limit of the hole mobility of the oxide semiconductor thin film 3 is not particularly limited, but the hole mobility of the oxide semiconductor thin film 3 is usually 100 cm 2 /Vs or less. "Hall mobility” refers to carrier mobility obtained by Hall effect measurement.
  • the ESL protective film 4 is a protective film that prevents the oxide semiconductor thin film 3 from being damaged and the characteristics of the thin film transistor from being deteriorated when the source and drain electrodes 5 are formed by etching.
  • the thin film that constitutes the ESL protective film 4 is not particularly limited, but a silicon oxide film is preferably used.
  • the lower limit of the average thickness of the ESL protective film 4 is preferably 50 nm, and more preferably 80 nm.
  • the upper limit of the average thickness of the ESL protective film 4 is preferably 250 nm, and more preferably 200 nm. If the average thickness of the ESL protective film 4 is less than the above lower limit, the ESL protective film 4 may not be able to sufficiently protect the oxide semiconductor thin film 3. Conversely, if the average thickness of the ESL protective film 4 exceeds the above upper limit, it may be difficult to flatten the passivation insulating film 6, and the wiring from the source and drain electrodes 5 may be easily broken.
  • the source and drain electrodes 5 cover a portion of the gate insulating film 2 and the ESL protective film 4, and are electrically connected to the oxide semiconductor thin film 3 at both ends of the channel of the thin film transistor.
  • a drain current of the thin film transistor flows between the source electrode 5a and the drain electrode 5b in response to the voltage between the gate electrode 1 and the source electrode 5a and the voltage between the source electrode 5a and the drain electrode 5b.
  • the thin film that constitutes the source and drain electrodes 5 is not particularly limited as long as it is conductive, and for example, the same thin film as that of the gate electrode 1 can be used.
  • the lower limit of the average thickness of the source and drain electrodes 5 is preferably 100 nm, and more preferably 150 nm.
  • the upper limit of the average thickness of the source and drain electrodes 5 is preferably 400 nm, and more preferably 300 nm. If the average thickness of the source and drain electrodes 5 is less than the lower limit, the resistance of the source and drain electrodes 5 is high, which may increase power consumption in the source and drain electrodes 5 or make them more susceptible to breakage. Conversely, if the average thickness of the source and drain electrodes 5 exceeds the upper limit, it may become difficult to planarize the passivation insulating film 6, and wiring using the conductive film 7 may become difficult.
  • the distance between the source electrode 5a and the drain electrode 5b i.e., the lower limit of the channel length of the thin-film transistor, is preferably 5 ⁇ m, and more preferably 10 ⁇ m.
  • the upper limit of the channel length of the thin-film transistor is preferably 50 ⁇ m, and more preferably 30 ⁇ m. If the channel length of the thin-film transistor is less than the lower limit, high-precision processing will be required, and there is a risk of a decrease in manufacturing yield. Conversely, if the channel length of the thin-film transistor exceeds the upper limit, there is a risk of the switching time of the thin-film transistor becoming longer.
  • the length of the source electrode 5a and the drain electrode 5b in the channel width direction i.e., the lower limit of the channel width of the thin film transistor, is preferably 100 ⁇ m, and more preferably 150 ⁇ m.
  • the upper limit of the channel width of the thin film transistor is preferably 300 ⁇ m, and more preferably 250 ⁇ m. If the channel width of the thin film transistor is less than the above lower limit, there is a risk of insufficient drain current. Conversely, if the channel width of the thin film transistor exceeds the above upper limit, there is a risk of excessive drain current, which unnecessarily increases the power consumption of the thin film transistor.
  • the passivation insulating film 6 covers the gate electrode 1, the gate insulating film 2, the oxide semiconductor thin film 3, the ESL protective film 4, the source electrode 5a, and the drain electrode 5b, and prevents the characteristics of the thin film transistor from deteriorating.
  • the thin film constituting the passivation insulating film 6 is not particularly limited, but a silicon nitride film is preferably used, which has a relatively easy sheet resistance controllable by the hydrogen content.
  • the passivation insulating film 6 may have a two-layer structure of, for example, a silicon oxide film and a silicon nitride film.
  • the lower limit of the average thickness of the passivation insulating film 6 is preferably 100 nm, and more preferably 250 nm.
  • the upper limit of the average thickness of the passivation insulating film 6 is preferably 500 nm, and more preferably 300 nm. If the average thickness of the passivation insulating film 6 is less than the above lower limit, the effect of preventing deterioration of the characteristics of the thin-film transistor may be insufficient. Conversely, if the average thickness of the passivation insulating film 6 exceeds the above upper limit, the passivation insulating film 6 may become unnecessarily thick, which may increase the manufacturing cost of the thin-film transistor and reduce production efficiency. Note that if the passivation insulating film 6 has a multi-layer structure, the "average thickness of the passivation insulating film" refers to the average thickness of the total.
  • a contact hole 8 is opened in the passivation insulating film 6 to allow electrical connection with the drain electrode 5b.
  • the shape and size of the contact hole 8 in a plan view are not particularly limited as long as electrical connection with the drain electrode 5b is ensured, but it can be, for example, a square with one side measuring 10 ⁇ m to 30 ⁇ m in a plan view.
  • the conductive film 7 is connected to the drain electrode 5b via a contact hole 8 formed in the passivation insulating film 6.
  • the conductive film 7 constitutes a wiring for acquiring a drain current from the thin film transistor.
  • the conductive film 7 is not particularly limited, and the same thin film as the gate electrode 1 can be used. Among them, a transparent conductive film suitable for application to a display is preferable. Examples of such a transparent conductive film include an ITO film and a ZnO film.
  • the position where the conductive film 7 is connected to the drain electrode 5b is preferably a position where the drain electrode 5b contacts the gate insulating film 2, and not directly above the gate electrode 1.
  • the lower limit of the average wiring width of the conductive film 7 is preferably 5 ⁇ m, and more preferably 10 ⁇ m.
  • the upper limit of the average wiring width of the conductive film 7 is preferably 50 ⁇ m, and more preferably 30 ⁇ m. If the average wiring width of the conductive film 7 is less than the above lower limit, the wiring of the conductive film 7 may have high resistance, and the power consumption and voltage drop in the wiring of the conductive film 7 may increase. Conversely, if the average wiring width of the conductive film 7 exceeds the above upper limit, the integration degree of the thin film transistor may decrease.
  • the "average wiring width of the conductive film” refers to the average width of the wiring portion of the conductive film 7 that is disposed on the surface of the passivation insulating film 6 and acquires the drain current from the thin film transistor.
  • the lower limit of the average thickness of the conductive film 7 is preferably 50 nm, and more preferably 80 nm.
  • the upper limit of the average thickness of the conductive film 7 is preferably 200 nm, and more preferably 150 nm. If the average thickness of the conductive film 7 is less than the lower limit, the wiring made of the conductive film 7 will have high resistance, and the power consumption and voltage drop in the wiring made of the conductive film 7 may increase.
  • the average thickness of the conductive film 7 refers to the average thickness of the wiring portion of the conductive film 7 that is disposed on the surface of the passivation insulating film 6 and acquires drain current from the thin film transistor.
  • the carrier mobility (electron mobility) of the thin film transistor is preferably more than 25 cm 2 /Vs, more preferably more than 27 cm 2 /Vs, and more preferably more than 30 cm 2 /Vs. If the carrier mobility of the thin film transistor is less than the lower limit, the switching characteristics of the thin film transistor may be deteriorated. In addition, by setting the carrier mobility to be more than the lower limit, the thin film transistor can be suitably used in, for example, next-generation large organic EL displays that require high speed. On the other hand, the upper limit of the carrier mobility of the thin film transistor is not particularly limited, but the carrier mobility of the thin film transistor is usually 100 cm 2 /Vs or less.
  • the lower limit of the threshold voltage of the thin-film transistor is preferably 0.6 V, and more preferably 1.0 V.
  • the upper limit of the threshold voltage of the thin-film transistor is preferably 5 V, more preferably 3 V, and even more preferably 2 V. If the threshold voltage of the thin-film transistor is below the lower limit, the leakage current in the off state as a switching element with no voltage applied to the gate electrode 1 may become large, and the standby power of the thin-film transistor may become too large. Conversely, if the threshold voltage of the thin-film transistor exceeds the upper limit, the drain current in the on state as a switching element with a voltage applied to the gate electrode 1 may become insufficient.
  • the upper limit of the threshold voltage shift of the thin-film transistor due to light irradiation is preferably 2 V, more preferably 1.5 V, and even more preferably 1 V. If the threshold voltage shift exceeds the upper limit, when the thin-film transistor is used in a display device, the performance of the thin-film transistor may be unstable and the required switching characteristics may not be obtained.
  • the lower limit of the threshold voltage shift is preferably 0 V, that is, the threshold voltage shift does not occur.
  • threshold voltage shift due to light irradiation refers to the absolute value of the difference in threshold voltage before and after irradiation when the thin-film transistor is irradiated with a white LED for 2 hours under the following conditions: a substrate temperature of 60°C, a voltage of 10 V between the source and drain of the thin-film transistor, and -10 V between the gate and source.
  • the lower limit of the S value (Subthreshold Swing value) of the thin film transistor is preferably 0.4 V/dec, and more preferably 0.45 V/dec.
  • the upper limit of the S value is preferably 1.0 V/dec, more preferably 0.7 V, and even more preferably 0.5 V.
  • the S value when driving a current-driven display such as an organic EL display, if the S value is below the lower limit, a slight change in gate voltage may cause the current to change too much, making current control difficult. Conversely, if the S value exceeds the upper limit, it may take a long time to switch the thin film transistor.
  • the thin film transistor can be manufactured by a manufacturing method including, for example, a gate electrode forming step, a gate insulating film forming step, an oxide semiconductor thin film forming step, an ESL protective film forming step, a source and drain electrode forming step, a passivation insulating film forming step, a conductive film forming step, and a post-annealing treatment step.
  • the gate electrode 1 is deposited on the surface of the substrate X.
  • a conductive film is laminated to a desired thickness on the surface of the substrate X by a known method, for example, a sputtering method.
  • the conditions for laminating the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., a film formation power density of 3 W/cm 2 to 4 W/cm 2 , a pressure of 0.1 Pa to 0.4 Pa, and a carrier gas of Ar.
  • the conductive film is patterned to form the gate electrode 1.
  • the patterning method is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used. At this time, it is preferable to etch the cross section of the gate electrode 1 into a tapered shape that expands toward the substrate X in order to improve the coverage of the gate insulating film 2.
  • the gate insulating film 2 is formed on the front surface side of the substrate X so as to cover the gate electrode 1 .
  • an insulating film is laminated to a desired thickness on the front surface side of the substrate X by a known method, for example, various CVD methods.
  • a silicon oxide film is laminated by a plasma CVD method
  • the conditions are a substrate temperature of 300° C. to 400° C., a deposition power density of 0.7 W/cm 2 to 1.3 W/cm 2 , and a pressure of 100 Pa to 300 Pa, and a mixed gas of N 2 O and SiH 4 is used as a source gas.
  • the oxide semiconductor thin film 3 is formed on the surface of the gate insulating film 2 and directly above the gate electrode 1. Specifically, an oxide semiconductor layer is laminated on the surface of the substrate X, and then the oxide semiconductor layer is patterned to form the oxide semiconductor thin film 3.
  • a known sputtering device is used to deposit an oxide semiconductor layer on the surface of the substrate X by a sputtering method.
  • a sputtering method By using the sputtering method, it is possible to easily form an oxide semiconductor layer having excellent in-plane uniformity in its components and film thickness.
  • the sputtering target used in the sputtering method is itself another embodiment of the present disclosure. That is, the sputtering target is used to form the oxide semiconductor thin film 3 and is a sputtering target containing metal elements, the metal elements being composed of In, Zn, Fe, and unavoidable impurities.
  • a specific example of the sputtering target is an oxide target containing In, Zn, and Fe (IZFO target).
  • the lower limit of the number of In atoms relative to the total number of In, Zn, and Fe atoms in the sputtering target is 50 atm%, more preferably 55 atm%, and even more preferably 60 atm%.
  • the upper limit of the number of In atoms is 80 atm%, more preferably 75 atm%, and even more preferably 70 atm%.
  • the lower limit of the number of Zn atoms relative to the total number of In, Zn, and Fe atoms is 20 atm%, more preferably 25 atm%, and even more preferably 30 atm%.
  • the upper limit of the number of Zn atoms is 48 atm%, more preferably 45 atm%, and even more preferably 40 atm%.
  • the lower limit of the number of Fe atoms relative to the total number of In, Zn, and Fe atoms is 1.5 atm%, more preferably 1.6 atm%, and even more preferably 1.7 atm%.
  • the upper limit of the number of Fe atoms is 2.5 atm%, more preferably 2.4 atm%, and even more preferably 2.3 atm%.
  • the lower limit of the In/Zn atomic ratio is 1.5, more preferably 1.6, and even more preferably 1.7.
  • the upper limit of the In/Zn atomic ratio is 2.5, more preferably 2.4, and even more preferably 2.3.
  • the sputtering target is preferably made to have the same composition as the desired oxide semiconductor layer.
  • composition deviation of the oxide semiconductor layer to be formed can be suppressed, making it easier to obtain an oxide semiconductor layer having the desired composition.
  • the sputtering target can be manufactured, for example, by a powder sintering method.
  • the sputtering target for stacking the oxide semiconductor layer is not limited to the target containing In, Zn, and Fe described above, and multiple targets with different compositions may be used.
  • the multiple targets are configured to contain In, Zn, and Fe as a whole.
  • each target may contain multiple elements of In, Zn, and Fe.
  • the multiple targets may also be oxide targets containing one or multiple elements of In, Zn, and Fe.
  • the multiple targets can also be manufactured by, for example, a powder sintering method. When the multiple targets are used, the sputtering method can be a co-sputtering method in which the multiple targets are simultaneously discharged.
  • the conditions for stacking the oxide semiconductor layer by sputtering are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., a deposition power density of 2 W/cm 2 to 3 W/cm 2 , a pressure of 0.1 Pa to 0.3 Pa, and a carrier gas of Ar.
  • oxygen may be contained in the atmosphere as an oxygen source.
  • the oxygen content in the atmosphere may be 3 vol. % to 5 vol. %.
  • the method for stacking the oxide semiconductor layer is not limited to sputtering, and a chemical film formation method such as a coating method may also be used.
  • the oxide semiconductor layer is patterned to form the oxide semiconductor thin film 3.
  • the method for patterning the oxide semiconductor thin layer is not particularly limited, but for example, a method of performing photolithography and then wet etching can be used.
  • a pre-annealing process may be performed to reduce the density of trap levels in the oxide semiconductor thin film 3. This can reduce the threshold voltage shift of the manufactured thin film transistor due to light irradiation.
  • the lower limit of the pre-annealing temperature is preferably 300°C, more preferably 350°C.
  • the upper limit of the annealing temperature is preferably 450°C, more preferably 400°C. If the pre-annealing temperature is below the lower limit, the effect of improving the electrical characteristics of the thin film transistor may be insufficient. Conversely, if the pre-annealing temperature exceeds the upper limit, the oxide semiconductor thin film 3 may be damaged by heat.
  • the pressure and time conditions of the annealing treatment are not particularly limited, but for example, conditions of an N 2 atmosphere at atmospheric pressure (0.9 atm to 1.1 atm) and a time of 10 minutes to 60 minutes can be used.
  • the ESL protective film 4 is formed on the surface of the oxide semiconductor thin film 3 in a portion where the source and drain electrodes 5 are not formed.
  • an insulating film is laminated to a desired thickness on the front surface side of the substrate X by a known method, for example, various CVD methods.
  • a silicon oxide film is laminated by a plasma CVD method
  • the conditions are a substrate temperature of 100° C. to 300° C., a deposition power density of 0.2 W/cm 2 to 0.5 W/cm 2 , and a pressure of 100 Pa to 300 Pa, and a mixed gas of N 2 O and SiH 4 is used as a source gas.
  • a source electrode 5a and a drain electrode 5b are formed to be electrically connected to the oxide semiconductor thin film 3 on both ends of the channel of the thin film transistor.
  • a conductive film is laminated to a desired thickness on the surface of the substrate X by a known method, for example, a sputtering method.
  • the conditions for laminating the conductive film by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., a film formation power density of 3 W/cm 2 to 4 W/cm 2 , a pressure of 0.1 Pa to 0.4 Pa, and a carrier gas of Ar.
  • the conductive film is patterned to form the source electrode 5a and the drain electrode 5b.
  • the patterning method is not particularly limited, but for example, a method of performing photolithography followed by wet etching can be used.
  • ⁇ Passivation insulating film formation process> In the passivation insulating film forming step, a passivation insulating film 6 that covers the thin film transistor is formed.
  • an insulating film is laminated to a desired thickness on the front surface side of the substrate X by a known method, for example, various CVD methods.
  • conditions for laminating a silicon nitride film by plasma CVD are a substrate temperature of 100° C. to 200° C., a deposition power density of 0.2 W/cm 2 to 0.5 W/cm 2 , and a pressure of 100 Pa to 300 Pa, and a mixed gas of NH 3 and SiH 4 is used as a source gas.
  • the conductive film 7 that is electrically connected to the drain electrode 5b through the contact hole 8 is formed.
  • a contact hole 8 is formed by a known method, for example, photolithography to pattern a contact portion with the drain electrode 5b, followed by dry etching.
  • a conductive film 7 that is electrically connected to the drain electrode 5b through the contact hole 8 is formed by a known method, for example, sputtering.
  • the conditions for laminating the conductive film 7 by the sputtering method are not particularly limited, but may be, for example, a substrate temperature of 20° C. to 50° C., a film formation power density of 3 W/cm 2 to 4 W/cm 2 , a pressure of 0.1 Pa to 0.4 Pa, and a carrier gas of Ar.
  • the post-annealing process is a process of carrying out a final heat treatment.
  • This heat treatment can reduce the density of trap states formed at the interface between the oxide semiconductor thin film 3 and the gate insulating film 2 and at the interface between the oxide semiconductor thin film 3 and the ESL protective film 4. This can reduce the threshold voltage shift of the thin film transistor due to light irradiation.
  • the lower limit of the post-annealing temperature is preferably 200°C, and more preferably 250°C.
  • the upper limit of the post-annealing temperature is preferably 400°C, and more preferably 350°C. If the post-annealing temperature is below the lower limit, the effect of improving the electrical characteristics of the thin-film transistor may be insufficient. Conversely, if the post-annealing temperature exceeds the upper limit, the thin-film transistor may be damaged by heat.
  • the pressure and time conditions for the post-annealing process are not particularly limited, but for example, atmospheric pressure (0.9 atm or more and 1.1 atm or less) and a time of 10 minutes to 60 minutes can be used.
  • the post-annealing process may be performed in an atmospheric atmosphere, but is preferably performed in an atmosphere of an inert gas such as nitrogen. By performing the post-annealing process in an inert gas atmosphere, it is possible to suppress variations in the quality of the thin-film transistor caused by the binding of molecules, etc. contained in the atmosphere to the thin-film transistor during the post-annealing process.
  • the oxide semiconductor thin film 3 has a high light stress resistance because the number of In atoms is 50 atm% or more and 80 atm% or less, the number of Zn atoms is 20 atm% or more and 48 atm% or less, and the number of Fe atoms is 1.5 atm% or more, relative to the total number of In, Zn, and Fe atoms. Also, the oxide semiconductor thin film 3 has a number of Fe atoms of 2.5 atm% or less, so that the carrier mobility can be increased when a thin film transistor is formed using the oxide semiconductor thin film 3. Furthermore, the ratio In/Zn of the number of In atoms to Zn atoms is 1.5 or more, so that the S value can be increased, and the ratio In/Zn of 2.5 or less can be made excellent in switching characteristics.
  • the thin-film transistor since the thin-film transistor has the oxide semiconductor thin film 3, it has high mobility and light stress resistance, as well as excellent S value and switching characteristics. Therefore, the thin-film transistor is suitable for use in organic EL displays.
  • the sputtering target contains In, Zn, and Fe whose atomic numbers are within the above ranges, and the ratio of the atomic numbers of In/Zn is within the above range. Therefore, by forming an oxide semiconductor thin film 3 using the sputtering target, and then forming a thin film transistor on the oxide semiconductor thin film 3, it is possible to manufacture a thin film transistor that has excellent S value and switching characteristics in addition to high mobility and light stress resistance.
  • oxide semiconductor thin film, thin film transistor, and sputtering target of the present disclosure are not limited to the above-described embodiments.
  • a bottom-gate type thin-film transistor is described, but a top-gate type thin-film transistor may also be used.
  • the thin-film transistor has an ESL protective film, but the ESL protective film is not an essential component.
  • the oxide semiconductor thin film is less susceptible to damage, so the ESL protective film can be omitted.
  • the oxide semiconductor thin film does not substantially contain any metal elements other than In, Zn, and Fe, but it may unavoidably contain other metal elements.
  • a metal element may be Sn.
  • Example 1 A glass substrate (Corning "EagleXG", diameter 6 inches, thickness 0.7 mm) was prepared, and a Mo thin film was first formed on the surface of the glass substrate to an average thickness of 100 nm.
  • the film formation conditions were a substrate temperature of 25°C (room temperature), a film formation power density of 3.8 W/ cm2 , a pressure of 0.266 Pa, and a carrier gas of Ar. After the Mo thin film was formed, a gate electrode was formed by patterning.
  • a silicon oxide film having an average thickness of 250 nm was formed as a gate insulating film by CVD so as to cover the gate electrode.
  • a mixed gas of N2O and SiH4 was used as a source gas.
  • the film forming conditions were a substrate temperature of 320°C, a film forming power density of 0.96 W/ cm2 , and a pressure of 133 Pa.
  • an oxide semiconductor layer containing essentially only In, Zn, and Fe and having an average thickness of 40 nm was formed on the front side of the glass substrate by sputtering.
  • sputtering method For the sputtering method, a method that has been established as a method for investigating the optimal composition ratio was used. Specifically, three targets, In 2 O 3 , ZnO, and In 2 O 3 with Fe chips attached, were placed at different positions around the glass substrate, and sputtering was performed on the stationary glass substrate to form an oxide semiconductor layer. According to this method, three targets with different constituent elements are placed at different positions around the glass substrate, so the distance from each target varies depending on the position on the glass substrate.
  • Zn is more than In at a position close to the ZnO target and far from the In 2 O 3 target
  • In is more than Zn at a position close to the In 2 O 3 target and far from the ZnO target.
  • an oxide semiconductor layer with a different composition ratio depending on the position on the glass substrate can be obtained.
  • a sputtering device (“CS200" manufactured by ULVAC, Inc.) was used, and the deposition conditions were a substrate temperature of 25° C. (room temperature), deposition power density of 2.55 W/cm 2 , pressure of 0.133 Pa, and carrier gas of Ar.
  • the oxygen content of the atmosphere was 4% by volume.
  • the resulting oxide semiconductor layer was patterned using photolithography and wet etching to form an oxide semiconductor thin film with a different composition depending on the position on the glass substrate.
  • the wet etchant used was "ITO-07N” manufactured by Kanto Chemical Co., Ltd.
  • a pre-annealing process was carried out to improve the film quality of this oxide semiconductor thin film.
  • the pre-annealing process was carried out for 60 minutes in an air atmosphere (atmospheric pressure) at 300°C.
  • a silicon oxide film was formed on the front surface of the glass substrate by CVD to an average thickness of 100 nm.
  • a mixed gas of N2O and SiH4 was used as the source gas.
  • the film formation conditions were a substrate temperature of 230°C, a film formation power density of 0.32 W/ cm2 , and a pressure of 133 Pa.
  • an ESL protective film was formed by patterning.
  • a Mo thin film was formed on the front surface of the glass substrate to an average thickness of 200 nm under the following film forming conditions: substrate temperature 25° C. (room temperature), film forming power density 3.8 W/cm 2 , pressure 0.266 Pa, and carrier gas Ar. After forming the Mo thin film, a source electrode and a drain electrode were formed by patterning.
  • a passivation insulating film having a two-layer structure of a silicon oxide film (average thickness 100 nm) and a silicon nitride film (average thickness 150 nm) was formed on the front surface of the glass substrate by CVD.
  • a mixed gas of N2O and SiH4 was used to form the silicon oxide film
  • a mixed gas of NH3 and SiH4 was used to form the silicon nitride film.
  • the film formation conditions were a substrate temperature of 150°C, a film formation power density of 0.32 W/ cm2 , and a pressure of 133 Pa.
  • a contact hole was formed using photolithography and dry etching, and a pad was provided for electrical connection to the drain electrode. Electrical measurements of the thin-film transistor can be performed by applying a probe to this pad.
  • the thin film transistor of Example 1 was obtained.
  • the channel length of this thin film transistor was 20 ⁇ m, and the channel width was 200 ⁇ m.
  • the composition of the oxide semiconductor thin film in the thin film transistor of Example 1 was as shown in Table 1.
  • the In/Zn ratio is determined according to the composition of the oxide semiconductor thin film. This ratio is also shown in Table 1.
  • Examples 2 to 10 and Comparative Examples 1 to 7 The thin film transistors of Examples 2 to 10 and Comparative Examples 1 to 7 were obtained in the same manner as in Example 1, except that the number of In, Zn, and Fe atoms relative to the total number of In, Zn, and Fe atoms in the sputtering target used, i.e., the number of In, Zn, and Fe atoms relative to the total number of In, Zn, and Fe atoms in the oxide semiconductor thin film to be formed, and the pre-annealing and post-annealing temperatures were changed as shown in Table 1.
  • the carrier mobility was defined as the field effect mobility ⁇ FE [m 2 /Vs] in the saturation region of the static characteristics.
  • This field effect mobility ⁇ FE [m 2 /Vs] was calculated by ⁇ FE [m 2 /Vs] shown in the following formula (3) in the saturation region (Vg>Vd-Vth) of the static characteristics, where Vg [V], threshold voltage Vth [V], drain current Id [A], channel length L [m], channel width W [ m ], and capacitance C ox [F] of the gate insulating film.
  • Table 1 The results are shown in Table 1.
  • the threshold voltage was determined as the gate voltage at which the drain current of the transistor became 10 ⁇ 9 A, calculated from the static characteristics of the thin film transistor.
  • the S value was determined by calculating the amount of change in gate voltage required to increase the drain current by one digit from the static characteristics, and taking the minimum value as the S value. The results are shown in Table 1.
  • Carrier Mobility Basically, the higher the carrier mobility, the better. In terms of use in organic EL displays, the carrier mobility is preferably 25 m 2 /Vs or more. A: The carrier mobility is 25 m 2 /Vs or more. B: The carrier mobility is less than 25 m 2 /Vs.
  • the threshold voltage is preferably 0.6 V or more.
  • the preferred range is set to 0.4 V/dec or more and 1.0 V/dec or less.
  • mobility x threshold voltage Even if the mobility is large, if the threshold voltage is high, the carrier density is small, and the switching characteristics are degraded. Conversely, even if the threshold voltage is low, if the mobility is small, the switching characteristics are degraded. As an index for evaluating this relationship, the product of the mobility and the threshold voltage was defined. A case in which the mobility x threshold voltage was 30 cm 2 /s or more and 100 cm 2 /s or less was determined to be excellent in switching characteristics. A: Mobility x threshold voltage is 30 cm 2 /s or more and 100 cm 2 /s or less. B: The S value is less than 30 cm 2 /s or more than 100 cm 2 /s.
  • the thin film transistors of Examples 1 to 10 have high carrier mobility and excellent S value and switching characteristics.
  • the thin film transistors of Comparative Examples 1 to 5 are considered to have low carrier mobility, mainly because the In/Zn atomic ratio is less than 1.5.
  • Comparative Examples 1 and 2 are considered to have low S value, mainly because the number of Zn atoms is more than 49 atm %.
  • the thin film transistors of Comparative Examples 6 and 7 are considered to have poor switching characteristics, which are indexed by mobility x threshold voltage, mainly because the In/Zn atomic ratio is more than 2.5.
  • the oxide semiconductor thin film of the present disclosure has high mobility and light stress resistance, as well as excellent S value and switching characteristics when a transistor is formed.
  • the thin film transistor of the present disclosure using this oxide semiconductor thin film has high mobility and light stress resistance, as well as excellent S value and switching characteristics.
  • the sputtering target of the present disclosure can form this oxide semiconductor thin film.

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Abstract

Le but de la présente invention est de fournir une couche mince semi-conductrice à oxyde qui est excellente en termes de caractéristiques de commutation et de valeur S lorsqu'elle est formée dans un transistor, et qui présente une mobilité et une résistance à la contrainte de lumière élevées. Une couche mince semi-conductrice à oxyde selon la présente divulgation contient des éléments métalliques. Les éléments métalliques comprennent de l'In, du Zn, du Fe et des impuretés inévitables. Par rapport au nombre total d'atomes d'In, de Zn et de Fe, le nombre d'atomes d'In est de 50 à 80 % atm, le nombre d'atomes de Zn est de 20 à 48 % atm, le nombre d'atomes de Fe est de 1,5 à 2,5 % atm, et le rapport In/Zn du nombre d'atomes d'In par rapport à Zn est de 1,5 à 2,5.
PCT/JP2024/033410 2023-10-17 2024-09-19 Couche mince semi-conductrice à oxyde, transistor à couches minces et cible de pulvérisation Pending WO2025084065A1 (fr)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009081885A1 (fr) * 2007-12-25 2009-07-02 Idemitsu Kosan Co., Ltd. Transistor à effet de champ à oxyde semi-conducteur et son procédé de fabrication
WO2012029454A1 (fr) * 2010-08-31 2012-03-08 Jx日鉱日石金属株式会社 Oxyde fritté et pellicule mince semi-conductrice d'oxyde
WO2019107043A1 (fr) * 2017-11-29 2019-06-06 株式会社神戸製鋼所 Film mince semi-conducteur à oxyde, transistor à couches minces et cible de pulvérisation cathodique
JP2020194945A (ja) * 2019-05-30 2020-12-03 株式会社神戸製鋼所 ディスプレイ用酸化物半導体薄膜、ディスプレイ用薄膜トランジスタ及びスパッタリングターゲット
WO2020241227A1 (fr) * 2019-05-30 2020-12-03 株式会社コベルコ科研 Corps fritté à base d'oxyde et cible de pulvérisation
US20210135014A1 (en) * 2019-10-30 2021-05-06 Lg Display Co., Ltd. Thin film transistor, gate driver including the same, and display device including the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009081885A1 (fr) * 2007-12-25 2009-07-02 Idemitsu Kosan Co., Ltd. Transistor à effet de champ à oxyde semi-conducteur et son procédé de fabrication
WO2012029454A1 (fr) * 2010-08-31 2012-03-08 Jx日鉱日石金属株式会社 Oxyde fritté et pellicule mince semi-conductrice d'oxyde
WO2019107043A1 (fr) * 2017-11-29 2019-06-06 株式会社神戸製鋼所 Film mince semi-conducteur à oxyde, transistor à couches minces et cible de pulvérisation cathodique
JP2020194945A (ja) * 2019-05-30 2020-12-03 株式会社神戸製鋼所 ディスプレイ用酸化物半導体薄膜、ディスプレイ用薄膜トランジスタ及びスパッタリングターゲット
WO2020241227A1 (fr) * 2019-05-30 2020-12-03 株式会社コベルコ科研 Corps fritté à base d'oxyde et cible de pulvérisation
US20210135014A1 (en) * 2019-10-30 2021-05-06 Lg Display Co., Ltd. Thin film transistor, gate driver including the same, and display device including the same

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