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WO2018063310A1 - Transistors à effet tunnel comprenant des régions de source/drain utilisant différents matériaux semi-conducteurs - Google Patents

Transistors à effet tunnel comprenant des régions de source/drain utilisant différents matériaux semi-conducteurs Download PDF

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Publication number
WO2018063310A1
WO2018063310A1 PCT/US2016/054724 US2016054724W WO2018063310A1 WO 2018063310 A1 WO2018063310 A1 WO 2018063310A1 US 2016054724 W US2016054724 W US 2016054724W WO 2018063310 A1 WO2018063310 A1 WO 2018063310A1
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Prior art keywords
semiconductor material
layer
type
transistor
gate
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English (en)
Inventor
Glenn A. Glass
Anand S. Murthy
Ian A. Young
Uygar E. Avci
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Intel Corp
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Intel Corp
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Priority to PCT/US2016/054724 priority Critical patent/WO2018063310A1/fr
Priority to TW106127969A priority patent/TWI761363B/zh
Publication of WO2018063310A1 publication Critical patent/WO2018063310A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/021—Manufacture or treatment of gated diodes, e.g. field-controlled diodes [FCD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • a field-effect transistor is a semiconductor device that includes three terminals: a gate, a source, and a drain.
  • a FET uses an electric field applied by the gate to control the electrical conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain.
  • charge carriers e.g., electrons or holes
  • the FET is referred to as an n-channel device
  • the FET is referred to as a p-channel device.
  • MOSFETs metal -oxide-semiconductor FETs
  • MISFETs metal-insulator-semiconductor FETs
  • IGFETs insulated-gate FETs
  • CMOS Complementary MOS structures use a combination of p-channel MOSFET (p-MOS) and n-channel MOSFET (n-MOS) to implement logic gates and other digital circuits.
  • a FinFET is a MOSFET transistor built around a thin strip of semiconductor material (generally referred to as a fin).
  • the conductive channel of the FinFET device resides on the outer portions of the fin adjacent to the gate dielectric. Specifically, current runs along/within both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor.
  • a nanowire transistor (sometimes referred to as a gate-all-around (GAA) or nanoribbon transistor) is configured similarly to a fin-based transistor, but instead of a finned channel region where the gate is on three portions (and thus, there are three effective gates), one or more nanowires are used for the channel region and the gate material generally surrounds each nanowire.
  • GAA gate-all-around
  • Figure 1 illustrates a method of forming an integrated circuit (IC) including at least one tunneling transistor including source/drain (S/D) regions employing different material, in accordance with some embodiments of the present disclosure.
  • FIGS 2A-H illustrate example integrated circuit structures that are formed when carrying out method of Figure 1, in accordance with various embodiments.
  • Figure 2D' illustrates the example structure of Figure 2D, including vertical isolation structures, in accordance with an embodiment.
  • Figure 2Ff illustrates the example structure of Figure 2H, including the vertical isolation structures of Figure 2D', in accordance with an embodiment.
  • Figure 3 illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, specifically taken along the A-A plane, in accordance with some embodiments of the present disclosure.
  • Figure 3' illustrates the IC structure of Figure 3, including shading and patterning to assist with visualizing the material and doping scheme of the S/D regions, in accordance with some embodiments of the present disclosure.
  • FIGS 4 and 5 illustrate example p-type and n-type Fermi filter field-effect transistor (FFFET) energy band diagrams, respectively, for FFFET devices including S/D regions employing different semiconductor material, in accordance with some embodiments.
  • FFFET Fermi filter field-effect transistor
  • FIG. 6 illustrates a computing system implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • S/D source/drain
  • MOSFETs may employ source-channel-drain region doping schemes of p-n-p or n- p-n, where 'p' represents suitable p-type doping for a given semiconductor material and 'n' represents suitable n-type doping for a given semiconductor material.
  • MOSFETs employ similar-type doping in both of the S/D regions of one such device.
  • other transistor types employ doping schemes that include a source region with dissimilar-type doping relative to the drain region of that transistor.
  • tunnel field-effect-transistors generally include a similar structure as MOSFETs (as TFETs also include source, channel, and drain regions), except that TFETs may employ source-channel-drain doping schemes of p-i-n or n-i-p, where i represents intrinsic or nominally undoped semiconductor material (e.g., where nominally undoped includes impurity dopant concentrations of less than 1E16, 1E17, or 1E18 atoms per cubic cm).
  • TFETs employ dissimilar-type doping in the S/D regions of one such device.
  • FFFETs Fermi filter FETs
  • MOSFETs MOSFETs
  • FFFETs also include source, channel, and drain regions
  • FFFETs include a bilayer source region of opposite type doping, such that FFFETs may employ source-channel-drain doping schemes of np-i-p (or np-n-p) or pn-i-n (or pn-p-n).
  • TFETs, FFFETs, and other transistor types that include source and drain regions employing different dopant types (e.g., in contrast with S/D regions of MOSFETs that generally include only the same dopant types) and/or utilize tunneling mechanisms, it may be desired to alter the S/D material configuration from the conventional single semiconductor material designs to improve transistor performance.
  • TFETs and FFFETs are two types of tunneling transistor devices that have steeper current turn-on (e.g., versus gate voltage) than conventional p-n-p and n-p-n MOSFET devices, due to the fundamental switching mechanisms being relatively different.
  • MOSFET devices generally switch by modulating thermionic emission over a barrier, whereas TFET and FFFET devices switch by modulating quantum tunneling through a barrier.
  • the techniques described herein enhance the ability of such relatively steeper on-current devices (e.g., TFETs and FFFETs) to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate.
  • the material bandgap engineering may incorporate a material-based band offset component to control off-state leakage.
  • Such a band offset can expand upon the limited band offset achievable using conventional material configurations (e.g., single composition material configurations), because with such conventional material configurations, above a threshold doping concentration, there is no additional decrease in leakage current for a given source to drain voltage at fixed dimensions.
  • Si silicon germanium
  • Ge germanium
  • group IV semiconductor material includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as Si, Ge, SiGe, and so forth.
  • group IV element e.g., silicon, germanium, carbon, tin
  • group III-V semiconductor material includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP), and so forth.
  • group III element e.g., aluminum, gallium, indium
  • group V element e.g., nitrogen, phosphorus, arsenic, antimony
  • group III element e.g., aluminum, gallium, indium
  • group V element e.g., nitrogen, phosphorus, arsenic, antimony
  • group III element e.g., aluminum, gallium, indium
  • group V element e.g., nitrogen, phosphorus, arsenic, antimony
  • the bandgap material engineering may be performed for only the source side of the devices, such that the drain side may include material that is conventionally employed in the drain region, as will be apparent in light of this disclosure. Regardless, in some such embodiments, the S/D regions would still include dissimilar material relative to each other, where the source region would include material that is different than material from material included in the drain region. Note that the differences in material described herein for the S/D regions of a transistor are with reference to the bulk semiconductor material included in the S/D regions and not with respect to the impurity dopant(s) added to the bulk semiconductor material.
  • a conventional TFET device including a p-i-n or n-i-p doping scheme includes different impurity dopant types between the source and drain regions (e.g., one is n-type doped and the other is p-type doped); however, the bulk semiconductor material of the S/D regions in such a conventional TFET device is the same.
  • TFET devices are conventionally formed using a bulk semiconductor material of Si in both of the S/D regions, where one of the S/D regions is doped with a suitable n-type dopant (e.g., phosphorus) and the other S/D region is doped with a suitable p-type dopant (e.g., boron).
  • the source to drain material and doping scheme may include n-type doped Si then p-type doped SiGe in the source region, intrinsic Si in the channel region, and p-type doped Si in the drain region, in accordance with an embodiment employing a p-type FFFET device.
  • the source to drain material and doping scheme may include p-type doped GaAs then n- type doped InGaAs in the source region, intrinsic GaAs in the channel region, and n-type doped GaAs in the drain region, for instance.
  • Use of the techniques and structures provided herein may be detectable using tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SFMS); time-of-flight SFMS (ToF-SFMS); atom probe imaging or tomography; local electrode atom probe (LEAP) techniques; 3D tomography; or high resolution physical or chemical analysis, to name a few suitable example analytical tools.
  • tools such as: electron microscopy including scanning/transmission electron microscopy (SEM/TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; x-ray crystallography or
  • such tools may indicate an integrated circuit (IC) including a tunneling transistor including S/D regions employing different semiconductor material.
  • IC integrated circuit
  • the p/n-type doped source region may include a first semiconductor material (e.g., Si or GaAs) and the n/p-type doped drain region may include a second semiconductor material different than the first (e.g., SiGe or InGaAs).
  • the source region may include a bilayer structure including a first layer and a second layer, where one of the layers is p-type doped and the other is n-type doped.
  • the first and second layers may include different semiconductor material.
  • material engineering as described herein can make use of the different bandgaps and band offsets achievable to decrease leakage current for the off-state of transistor devices that utilize quantum tunneling and/or band-to-band tunneling (BTBT), such as TFETs and FFFETs, for example. Therefore, the techniques can be detected through cross-sections and material/chemical analysis. In some embodiments, the techniques and structures described herein may be detected based on the benefits derived therefrom, such as the relatively reduced off-state leakage that can be achieved. Numerous configurations and variations will be apparent in light of this disclosure.
  • BTBT quantum tunneling and/or band-to-band tunneling
  • Figure 1 illustrates a method 100 of forming an integrated circuit (IC) including at least one tunneling transistor including source/drain (S/D) regions employing different material, in accordance with some embodiments of the present disclosure.
  • Figures 2A-H illustrate example integrated circuit structures that are formed when carrying out method 100 of Figure 1, in accordance with some embodiments of the present disclosure.
  • the inclusion of different material in the S/D regions of a single transistor provides benefits as can be understood based on this disclosure, such as reducing off-state leakage in the form of source to drain leakage through the channel and source to ground/substrate leakage.
  • Method 100 of Figure 1 includes a primary vertical flow that illustrates a gate last transistor fabrication process flow, in accordance with some embodiments.
  • a gate first process flow may be used, as will be described herein (and which is illustrated with the alternative gate first flow 100' indicator in Figure 1).
  • the structures of Figures 2A-H are primarily depicted and described herein in the context of forming Fermi filter field-effect transistors (FFFETs) having finned configurations (e.g., FinFET or tri-gate), for ease of illustration and description.
  • FFETs Fermi filter field-effect transistors
  • the techniques can be used to form transistors of any suitable type and any suitable geometry or configuration, as can be understood based on this disclosure.
  • Figure 2G illustrates an example integrated circuit structure including transistors having nanowire configurations, as will be described in more detail below.
  • variations to the techniques used to form tunnel FET (TFET) devices are described herein and primarily relate to the S/D processing (box 114 of method 100).
  • the techniques described herein can benefit various different transistor types, such as a multitude of field-effect transistors (FETs) (e.g., TFETs, FFFETs), and any other transistor that operates by modulating quantum tunneling through a barrier, for example.
  • FETs field-effect transistors
  • Other suitable transistor types may benefit of the techniques described herein, where different material is formed in the source and drain regions.
  • various example transistor configurations that can benefit from the techniques described herein include, but are not limited to, planar, finned (e.g., FinFET, tri-gate, double-gate), and nanowire (or nanoribbon or gate-all-around).
  • the techniques can be used to benefit p-type devices (e.g., p-type FFFET and p-type TFET) and/or n-type devices (e.g., n-type FFFET and n-type TFET). Further yet, the techniques may be used to form complementary MOS (CMOS) devices/circuits, where either or both of the included p-type and n-type transistors are formed using the techniques described herein, such that either or both of the included p-type and n-type transistors include S/D regions having dissimilar material.
  • CMOS complementary MOS
  • Other example transistor devices can include few to single electron quantum transistor devices and devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example.
  • the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).
  • IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).
  • Method 100 of Figure 1 includes patterning 102 hardmask 210 on a substrate 200 to form the example resulting structure shown in Figure 2A, in accordance with an embodiment.
  • Hardmask 210 may be formed or deposited on substrate 200 using any suitable technique, as will be apparent in light of this disclosure.
  • hardmask 210 may be blanket deposited or otherwise grown on substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), spin-on processing, and/or any other suitable process to form hardmask 210 on substrate 200.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • spin-on processing and/or any other suitable process to form hardmask 210 on substrate 200.
  • the top surface of substrate 200 on which hardmask 210 is to be deposited may be treated (e.g., chemical treatment, thermal treatment, etc.) prior to deposition of the hardmask 210 material.
  • Hardmask 210 can be patterned 102 using any suitable techniques, such as one or more lithography and etch processes, for example.
  • Hardmask 210 may include of any suitable material, such as various oxide or nitride materials, for example. Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, or titanium nitride, just to name a few. In some cases, the hardmask 210 material may be selected based on the material of substrate 200, for example.
  • Substrate 200 may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), and/or at least one group III-V semiconductor material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V material).
  • group IV semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe)
  • XOI X on insulator
  • X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an
  • group IV semiconductor material includes at least one group IV element (e.g., silicon, germanium, carbon, tin), such as Si, Ge, SiGe, and so forth.
  • group IV element e.g., silicon, germanium, carbon, tin
  • group III-V semiconductor material includes at least one group III element (e.g., aluminum, gallium, indium) and at least one group V element (e.g., nitrogen, phosphorus, arsenic, antimony), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium phosphide (GaP), gallium antimonide (GaSb), and indium phosphide (InP), and so forth.
  • group III may also be known as the boron group or RJPAC group 13
  • group IV may also be known as the carbon group or RJPAC group 14
  • group V may also be known as the nitrogen family or R7PAC group 15, for example.
  • substrate 200 substrate 110 may include a surface crystalline orientation described by a Miller Index plane of ⁇ 001 ⁇ , ⁇ 011 ⁇ , or ⁇ 111 ⁇ , as will be apparent in light of this disclosure.
  • substrate 200 in this example embodiment, is shown as having a thickness (dimension in the Z-axis direction) similar to other layers for ease of illustration, in some instances, substrate 200 may be much thicker than the other layers, such as having a thickness in the range of 50 to 950 microns, for example, or any other suitable thickness as will be apparent in light of this disclosure.
  • substrate 200 may be used for one or more other IC devices, such as various diodes (e.g., light-emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC devices, depending on the end use or target application.
  • various diodes e.g., light-emitting diodes (LEDs) or laser diodes
  • transistors e.g., MOSFETs or TFETs
  • various capacitors e.g., MOSCAPs
  • MEMS microelectromechanical systems
  • NEMS nanoelectromechanical systems
  • RF radio frequency
  • the structures described herein may be included in a system-on-chip (SoC) application, as will be apparent in light of this
  • Method 100 of Figure 1 continues with performing 104 shallow trench recess (STR) etch to form fins 202 from substrate 200, thereby forming the resulting example structure shown in Figure 2B, in accordance with an embodiment.
  • the STR etch 104 used to form trenches 215 and fins 202 may include any suitable techniques, such as various masking processes and wet and/or dry etching processes, for example.
  • STR etch 104 may be performed in- situ/without air break, while in other cases, STR etch 104 may be performed ex-situ, for example.
  • Trenches 215 may be formed with varying widths (dimension in the X-axis direction) and depths (dimension in the Z-axis direction) as can be understood based on this disclosure.
  • multiple hardmask patterning 102 and STR etching 104 processes may be performed to achieve varying depths in the trenches 215 between fins 202.
  • Fins 202 may be formed to have varying widths Fw (dimension in the X-axis direction) and heights Fh (dimension in the Z-axis direction).
  • the fins may be formed to have particular height to width ratios such that when they are later removed or recessed, the resulting trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non- crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, if such an ART scheme is used.
  • defects in the replacement material deposited may terminate on a side surface as the material grows vertically, such as non- crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects, if such an ART scheme is used.
  • the fin widths Fw may be in the range of 5-400 nm, for example, or any other suitable value, as will be apparent in light of this disclosure.
  • the fin heights Fh may be in the range of 10-800 nm, for example, or any other suitable value, as will be apparent in light of this disclosure.
  • the fins may be formed to have particular height to width ratios such that when they are later recessed and/or removed, the resulting fin trenches formed allow for defects in the replacement material deposited to terminate on a side surface as the material grows vertically, such as non-crystalline/dielectric sidewalls, where the sidewalls are sufficiently high relative to the size of the growth area so as to trap most, if not all, of the defects.
  • the height to width ratio of the fins (Fh:Fw) may be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or any other suitable threshold ratio, as will be apparent in light of this disclosure.
  • the trenches 215 and fins 202 are each shown as having the same widths and depths/heights in this example structure for ease of illustration; however, the present disclosure is not intended to be so limited.
  • the fins 202 may be formed to have varying heights Fh and/or varying widths Fw.
  • any number of fins may be formed, such as one, two, ten, hundreds, thousands, millions, and so forth, as can be understood based on this disclosure.
  • Method 100 of Figure 1 continues with depositing 106 shallow trench isolation (STI) layer
  • deposition 106 of STI layer 220 may include any deposition process described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process.
  • the material of STI layer 220 may include any suitable insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), or nitride (e.g., silicon nitride) materials.
  • the material of STI layer 220 may selected based on the material of substrate 200. For instance, in the case of a Si substrate, STI material may be silicon dioxide or silicon nitride, to provide an example.
  • Method 100 of Figure 1 continues with recessing 108 the STI material 220 to cause at least a portion 204 of fins 202 to exude from the STI plane, thereby forming the resulting example structure shown in Figure 2D, in accordance with an embodiment.
  • the portion 204 of fin 202 exuding above the top plane of STI layer 220 (indicated as 204) has an active fin height indicated as Fah, which may be in the range of 10-750 nm, for example, or any other suitable value, as will be apparent in light of this disclosure.
  • the portion 203 of fin 202 that is below the top plane of STI layer 220 is the sub-fin portion (indicated as 203).
  • fins 202 are native to substrate 200.
  • fins 202 were formed from substrate 200 in this example embodiment and include the same material in the structure of Figure 2D, such that fins 202 (including portions 203 and 204) and substrate 200 are one homogenous structure.
  • some or all of fins 202 may be removed and replaced with replacement fins, for example.
  • the processing may continue from the structure of Figure 2C and include etching the fins 202 (e.g., using any suitable wet and/or dry etch processes) to form fin trenches between STI layer 220, where the etching either completely or partially removes fins 202 (e.g., either goes all the way to/past the bottom plane of STI layer 220 or does not, respectively).
  • the fin trenches can be used for the deposition of a replacement material, and continuing with recess process 108 would result in the fins of Figure 2D being replacement fins (which may include different material than what is included in substrate 200).
  • the replacement material may include group IV semiconductor material and/or group III-V semiconductor material, and/or any other suitable material as will be apparent in light of this disclosure.
  • replacement fins including SiGe may be formed by removing native Si fins during such processing and replacing them with the SiGe material, to provide an example.
  • an ART processing scheme may be employed, where the fin trenches have a high aspect ratio (e.g., heigh width ratio of greater than 1, 1.5, 2, 3, 4, 5, or a higher value).
  • Such an ART processing scheme may be employed, for example to trap dislocations, thereby preventing the dislocations from reaching the epitaxial film surface and greatly reducing the surface dislocation density within the trenches.
  • method 100 of Figure 1 may optionally continue with forming 110 vertical isolation structures 230 as shown in Figure 2D', in accordance with an embodiment.
  • Figure 2D' illustrates the example structure of Figure 2D, including vertical isolation structures 230. Therefore, the previous relevant description with respect to the example structure of Figure 2D is equally applicable to the example structure of Figure 2D'.
  • vertical isolation structures 230 may be formed to, for example, further isolate (or electrically insulate) single fins or groups of fins.
  • such vertical isolation structures are present and may be included to prevent the eventual S/D regions of one transistor device from shorting the S/D of another (e.g., adjacent) transistor device by ensuring the respective S/D regions stay separate.
  • such vertical isolation structures 230 may be formed using any suitable techniques and, when present the structures 230 may include any suitable electrical insulator material, such as a dielectric, oxide, nitride, and/or carbide material, for instance.
  • vertical isolation structures 230 are higher (dimension in the Z-axis direction) than fins 204, the present disclosure is not intended to be so limited. Also, because vertical isolation structure 230 need not be present in some disclosure, as they are optional, method 100 will continue to be described using IC structures without the vertical isolation structures 230, for ease of description.
  • method 100 is primarily described herein in the context of a gate last transistor fabrication process flow, where the processing includes forming a dummy gate stack, performing the S/D processing, and then forming the final gate stack after the S/D regions have been processed.
  • the techniques may be performed using a gate first process flow.
  • process 112 - forming a dummy gate stack - would not be performed, and thus, process 112 is optional in some embodiments (such as those employing the gate first process flow).
  • performing 116 the final gate stack processing 116 may be performed prior to performing 114 the S/D processing, for example.
  • the description of method 100 will continue using a gate last process flow, to allow for such a flow (which may include additional processes) to be adequately described.
  • Method 100 of Figure 1 continues with forming 112 a dummy gate stack, including dummy gate dielectric 242 and dummy gate electrode 244, thereby forming the example resulting structure of Figure 2E, in accordance with an embodiment.
  • process 112 is optional, because it need not be performed in all embodiments (such as those employing a gate first process flow).
  • dummy gate dielectric 242 e.g., dummy oxide material
  • dummy gate or dummy gate electrode 244 e.g., dummy poly- silicon material
  • side-wall spacers 250 referred to generally as gate spacers (or simply, spacers), on either side of the dummy gate stack were also formed, and such spacers 250 can help determine the channel length and can help with replacement gate processes, for example.
  • the dummy gate stack (and spacers 250) can help define the channel region and source/drain (S/D) regions of each fin, where the channel region is below the dummy gate stack (as it will be located below the final gate stack), and the S/D regions are on either side of the dummy gate stack.
  • Formation of the dummy gate stack may include depositing the dummy gate dielectric material 242 and dummy gate electrode material 244, patterning the dummy gate stack, depositing gate spacer material 250, and performing a spacer etch to form the structure shown in Figure 2E, for example.
  • Spacers 250 may include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure.
  • the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Regardless, the end structure will include the end gate stack, as will be apparent in light of this disclosure.
  • a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.
  • Method 100 of Figure 1 continues with performing 114 source/drain (S/D) processing to form the example resulting structure of Figure 2F, in accordance with an embodiment.
  • the structure includes source regions 261 that each include a bilayer stack structure including a first layer 262 and a second layer 264.
  • source region second layer 264 may be formed prior to source region first layer 262, in some embodiments, the layers 264, 262 are referred to as such due to the flow of current through the source region 261 (e.g., the current can flow from the source contact to the first layer 262 of the source region and then to the second layer 264 of the source region).
  • second layer 264 is below first layer 262, and thus, first layer 262 is above second layer 264; however, the present disclosure need not be so limited unless otherwise stated.
  • source regions 261 may be single layer structures, such as in the case of forming TFET devices, to provide an example.
  • the source region second layer 264 may be between the source region first layer 262 and at least one of the channel region and the substrate 200, as can be understood based on this disclosure.
  • the presence of second layer 264 may help prevent leakage from the first layer 262 to the channel region and/or substrate 200, in accordance with some such embodiments.
  • the structure includes drain regions 265 on the opposing side of the gate stack (and thus on the opposing side of the channel region) from each corresponding source region 261. Therefore, when discussing the S/D regions of a transistor herein, for ease of description, it will be assumed that a single transistor will be formed using a single fin structure, such that one source region 261 and its corresponding drain region 265 (e.g., aligned in the Y-axis direction) will be considered the S/D regions for that single transistor.
  • Figure 3 illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, and specifically taken along the A-A plane, which will be described in more detail below.
  • the cross-sectional view of Figure 3 may help in illustrating the S/D regions and the transistor structure in general, for instance.
  • the S/D regions may be formed using any suitable techniques, such as masking regions outside of the S/D regions to be processed, etching portions of the fins from the structure of Figure 2E (in this example case, active portions 204 were etched and removed, leaving only sub-fin portions 203, as shown), and forming/depositing/growing the S/D regions (e.g., using any suitable techniques, such as CVD, ALD, PVD), for example.
  • the source regions 261 may be processed separately from the drain regions 265, as they may include different material and different doping types, as can be understood based on this disclosure.
  • one set of the S/D regions may be masked off while processing occurs in the other set of S/D regions, and then the masking and processing can be switched.
  • processing may occur to both sets of the S/D regions 261 and 265 simultaneously, such as forming dopants in source layer 264 and drain 265 simultaneously, as such features may include the same dopant types, in accordance with some embodiments.
  • the native fin 204 material i.e., native to substrate 200
  • the material of the S/D regions may include native and/or replacement material, such that there may or may not be a distinct interface between the sub-fin portions 203 and the S/D regions (e.g., layers 264 and 265).
  • the material of the S/D regions is replacement material, there is a distinct interface between features 264 and 203 and between features 265 and 203, as shown in Figures 2F and 3. Note that even in embodiments where material native to substrate 200 is used in an S/D region, there may still be a distinct interface between the S/D region and the sub-fin 203, because of impurity dopants introduced into the S/D region, for example. Numerous different techniques for processing the S/D regions will be apparent in light of this disclosure.
  • the S/D regions may include any suitable material, such as group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., GaAs, InGaAs, InAs), and/or any other suitable semiconductor material, and may also include any suitable doping scheme, as will be apparent in light of this disclosure.
  • group IV semiconductor material e.g., Si, SiGe, Ge
  • group III-V semiconductor material e.g., GaAs, InGaAs, InAs
  • the impurity dopants can convert the semiconductor material to extrinsic semiconductor material (as opposed to intrinsic semiconductor material), as can be understood based on this disclosure.
  • Such doping intentionally introduces the impurities in semiconductor material to, for example, modulate the electrical properties of the semiconductor material.
  • impurity doping may be used to change the electrical properties of included group IV and/or group III-V semiconductor material, for instance.
  • doping semiconductor material may be achieved using any suitable techniques, such as via diffusion, ion implantation, depositing/growing the dopants with the primary semiconductor material, and/or any other suitable techniques as will be apparent in light of this disclosure.
  • the dopants may be introduced into native semiconductor material (native to the substrate) and/or replacement semiconductor material (e.g., that is epitaxially formed), for instance.
  • the impurity dopants may be implanted with or without preamorphizing treatments, for example. Any number of doping processes may be performed as desired to introduce suitable n-type and/or p-type dopant(s) into the semiconductor material of the source, drain, and/or channel regions, as will be apparent in light of this disclosure.
  • semiconductor material included in at least one of the layers/regions/features may not be intentionally doped, such that the semiconductor material is intrinsic or nominally undoped.
  • Such nominal doping may occur as a result of undesired diffusion, for example, and thus, the use of "nominally undoped" with reference to semiconductor material or a layer/region/feature including semiconductor material includes having an impurity dopant concentration of less than 1E15, 1E16, 1E17, or 1E18 atoms per cubic centimeter (cm), or less than some other suitable threshold amount, as will be apparent in light of this disclosure.
  • the dopants when dopants are present in the semiconductor material of any layer/region feature of a transistor device, the dopants may be present in any suitable concentration, such as in a concentration in the range of 1E15 to 5E22 atoms per cubic centimeter (cm), or any other suitable concentration as will be apparent in light of this disclosure.
  • Relatively high dopant concentrations e.g., greater than 1E19, 1E20, or 1E21
  • Conventional dopants for group IV semiconductor material includes phosphorous (P) and/or arsenic (As) for n-type dopant (donors) and boron (B) for p-type dopant (acceptors), to provide some examples.
  • conventional dopants for group III-V semiconductor material e.g., GaAs, InGaAs, InAs
  • group III-V semiconductor material includes Si for n-type dopant (donors) and beryllium (Be), zinc (Zn), and/or magnesium (Mg) for p-type dopant, to provide some examples.
  • the source region 261 may include a bilayer structure, such as is shown in Figures 2F and 3, where that bilayer source region includes first layer 262 and second layer 264.
  • the doping scheme for features 262/262-206-265 may be np-i-p (or np-n-p) or pn-i-n (or pn-p-n), where 'n' represents n-type doped semiconductor material, 'p' represents p-type doped semiconductor material, and 'i' represents intrinsic or nominally undoped semiconductor material, for example.
  • the source region first layer 262 may include one of n-type and p-type dopant and the source region second layer 264 includes the other of n-type and p-type dopant relative to the first layer 262.
  • the drain region 265 may include the same dopant type as the source region second layer 264, such that they both include n-type or p-type dopant, for example.
  • the drain region 265 may include the other of n-type and p-type dopant relative to the source region first layer 262, for example.
  • channel region 206 for FFFET devices or any other transistors that can be formed using the techniques described herein may be intrinsic or nominally undoped (e.g., with impurity dopant concentrations of less than 1E16, 1E17, or 1E18 atoms per cubic cm) or the channel region 206 may be doped with suitable n-type or p-type dopant, as will be apparent in light of this disclosure.
  • the source need not have a bilayer structure, such that the source region 261 is only one layer, for example.
  • the S/D regions may include opposite types of dopants in a source- channel-drain scheme of either p-i-n (e.g., for p-TFET) or n-i-p (e.g., for n-TFET), for example.
  • the S/D regions may each include the same type of dopant in a source-channel-drain doping scheme of either p-n-p (e.g., for p-MOS) or n-p-n (e.g.. for n-MOS), for example.
  • p-n-p e.g., for p-MOS
  • n-p-n e.g.. for n-MOS
  • conventional MOSFET devices may be included with tunnel transistor devices (e.g., FFFETs and/or TFETs) in the same circuit (e.g., for forming CMOS devices).
  • one or both of the S/D regions 261 and 265 may include a multilayer structure of two or more material layers, for example, such as is the case for source region 261 including a bilayer structure in the example embodiments of Figures 2F and 3.
  • one or both of the S/D regions 261 and 265 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the region(s), where the material graded may relate to the concentration of included semiconductor material (e.g., the concentration of Ge throughout the SiGe material) and/or included dopants, for example.
  • a multitude of transistor types may be employed, as can be understood based on this disclosure.
  • the configurations and/or properties e.g., included semiconductor material, doping, bandgap properties, relative location, and so forth
  • the configurations and/or properties e.g., included semiconductor material, doping, bandgap properties, relative location, and so forth
  • the configurations and/or properties e.g., included semiconductor material, doping, bandgap properties, relative location, and so forth
  • the configurations and/or properties e.g., included semiconductor material, doping, bandgap properties, relative location, and so forth
  • the source region 261 may include different semiconductor material relative to the drain region 265, such as Si in one of the regions and SiGe or Ge in the other.
  • the layers 262 and 264 may include different semiconductor material relative to the semiconductor material included in drain region 265, in accordance with some embodiments.
  • layers 262 and 264 may include the same or different semiconductor material (e.g., both include Si or one includes Si and the other includes SiGe).
  • semiconductor material in the S/D regions can allow for bandgap engineering to obtain a desired effect, such as increasing band offsets to decrease leakage current in the transistor off-state, as will be described in more detail with respect to Figures 4 and 5.
  • semiconductor material may be selected based on relative bandgaps, relative valence band edge (Ev) properties, and/or based on relative conduction band edge (Ec) properties.
  • the source region second layer 264 may be considered a filter element, such as in a FFFET device, where the filter element is relatively thin, having a thickness (e.g., dimension in the Z-axis direction and/or dimension between 262 and 206 in the Y-axis direction) in the range of 5-50 nm (e.g., 10-25 nm), or some other suitable thickness as will be apparent in light of this disclosure.
  • a thickness/height e.g., dimension in the Z-axis direction
  • the entirety of the thickness/height (e.g., dimension in the Z-axis direction) of the S/D regions may be any suitable thickness/height, which may be based on the active channel region height, for example. Additional material and doping example configurations will be described herein with reference to Figures 3', 4, and 5. Numerous transistor S/D configurations and variations will be apparent in light of this disclosure.
  • Method 100 of Figure 1 continues with performing 116 gate stack processing to form the example resulting structure of Figure 2G.
  • the processing in this example embodiment included depositing interlay er dielectric (ILD) layer 270 on the structure of Figure 2F, followed by optional planarization and/or polishing to reveal the dummy gate stack.
  • ILD layer 270 is shown as transparent in the example structure of Figure 2G to allow for the underlying features to be seen; however, the present disclosure is not intended to be so limited.
  • the ILD layer 270 may include any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide), and/or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure.
  • the gate stack processing in this example embodiment, continued with removing the dummy gate stack (including dummy gate 244 and dummy gate dielectric 242) to allow for the final gate stack to be formed.
  • the formation of the final gate stack which includes gate dielectric layer 282 and gate (or gate electrode) 284, may be performed using a gate first flow (also called up-front hi-k gate).
  • the gate processing may have been performed after process 108 or after optional process 110 (in embodiments where process 110 is performed) and prior to the S/D processing 114.
  • the gate stack is formed using a gate last flow (also called a replacement gate or replacement metal gate (RMG) process).
  • RMG replacement gate or replacement metal gate
  • the process may include dummy gate oxide deposition, dummy gate electrode (e.g., poly-Si) deposition, and, optionally, patterning hardmask deposition, as previously described.
  • the final gate stack can include gate dielectric layer 282 and gate 284 as shown in Figure 2G.
  • the channel region of fins 204 (that were covered by the dummy gate) are exposed to allow for any desired processing of the channel regions of the fins.
  • processing of the channel region may include various different techniques, such as removing and replacing the channel region with replacement material, doping the channel region of the fin as desired, forming the fin into one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, cleaning/polishing the channel region, and/or any other suitable processing as will be apparent in light of this disclosure.
  • GAA gate-all-around
  • finned channel region 206 is illustrated (which is the channel region of the right most finned structure), which may have been formed by doping the native fin 204 with a desired suitable n-type or p-type dopant, for example.
  • nanowire channel region 208 (which is the channel region of the left most finned structure) may have been formed after the dummy gate was removed and the channel regions of the fins were exposed, by converting the finned structure at that location using any suitable techniques, for example.
  • nanowire channel region 208 includes 2 nanowires (or nanoribbons).
  • a nanowire (or nanoribbon or GAA) transistor formed using the techniques disclosed herein may include any number of nanowires (or nanoribbons) such as 1-10 or more, depending on the desired configuration.
  • the channel region is at least below the gate stack in this example embodiment.
  • the channel region may be below and between the gate stack, as the stack is formed on three sides as is known in the art.
  • the gate and channel relationship may include a proximate relationship (which may or may not include intervening gate dielectric layer and/or other suitable layers), where the gate is near the channel region such that it can exert control over the channel region in some manner (e.g., in an electrical manner), in accordance with some embodiments.
  • the gate stack may substantially (or completely) surround each nanowire/nanoribbon in the channel region. Further still, in the case of a planar transistor configuration, the gate stack may simply be above the channel region.
  • the channel region may include group IV semiconductor material (e.g., Si, SiGe, Ge), group III-V semiconductor material (e.g., GaAs, InGaAs, InAs), and/or any other suitable material as will be apparent in light of this disclosure.
  • semiconductor material included in the channel region may be native to substrate 200 and/or semiconductor material included in the channel region may not be native to substrate 200 (e.g., such that it is replacement material or material formed above substrate 200).
  • the channel region may be doped (e.g., with any suitable n-type and/or p-type dopant) or intrinsic/nominally undoped, depending on the particular configuration.
  • the S/D regions are adjacent to either side of the channel region, as can be seen in Figure 2G and 3, for example. More specifically, the S/D regions are directly adjacent the channel region, such that there are no intervening layers between either of the S/D regions and the channel region, in the example embodiments.
  • the present disclosure is not intended to be so limited.
  • the configuration/geometry of a transistor formed using the techniques described herein may primarily be described based on the shape/configuration of the respective channel region of that transistor, for example.
  • a nanowire (or nanoribbon or GAA) transistor may be referred to as such because it includes one or more nanowires (or nanoribbons) in the channel region of that transistor.
  • transistor type e.g., MOSFET, FFFET, TFET or other suitable type
  • transistor type may be described based on the doping and/or operating scheme of the source, drain, and channel regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example.
  • MOSFET versus TFET transistors may structurally be very similar (or the same), but include different doping schemes (e.g., p-n-p or n-p-n for MOSFET versus p-i-n or n-i-p for TFET).
  • the final gate stack can be formed, in accordance with an embodiment.
  • the final gate stack includes gate dielectric layer 282 and gate 284, as shown in Figure 2G.
  • the gate dielectric layer 282 may include, for example, any suitable oxide (such as silicon dioxide), high-k gate dielectric material, and/or any other suitable material as will be apparent in light of this disclosure.
  • high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples.
  • an annealing process may be carried out on the gate dielectric layer 282 to improve its quality when high-k material is used.
  • the gate 284 may include a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), titanium nitride (TiN), or tantalum nitride (TaN), for example.
  • gate dielectric layer 282 and/or gate 284 may include a multilayer structure of two or more material layers, for example.
  • gate dielectric layer 282 and/or gate 284 may include grading (e.g., increasing and/or decreasing) the content/concentration of one or more materials in at least a portion of the feature(s).
  • Additional layers may be present in the final gate stack, in some embodiments, such as one or more work function layers or other suitable layers, for example.
  • gate dielectric layer 282 is only shown below gate 284 in the example embodiment of Figure 2G, in other embodiments, the gate dielectric layer 282 may also be present on one or both sides of gate 284, such that the gate dielectric layer 282 is between gate 284 and spacers 250, for example.
  • Method 100 of Figure 1 continues with performing 118 S/D contact processing to form the example resulting structure of Figure 2H, in accordance with an embodiment.
  • S/D contacts 290 were formed to make contact to each of the S/D regions, in this example embodiment.
  • S/D contacts 290 may be formed using any suitable techniques, such as forming contact trenches in ILD layer 270 over the respective S/D regions and depositing metal or metal alloy (or other suitable electrically conductive material) in the trenches.
  • S/D contact 290 formation may include silicidation, germinidation, and/or annealing processes, for example.
  • S/D contacts 290 may include aluminum or tungsten, although any suitable conductive metal or alloy can be used, such as silver, nickel-platinum, or nickel-aluminum, for example.
  • one or more of the S/D contacts 290 may include a resistance reducing metal and a contact plug metal, or just a contact plug, for instance.
  • Example contact resistance reducing metals include, for instance, nickel, aluminum, titanium, gold, gold-germanium, nickel-platinum, or nickel aluminum, and/or other such resistance reducing metals or alloys.
  • Example contact plug metals include, for instance, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used.
  • additional layers may be present in the S/D contact 290 regions, such as adhesion layers (e.g., titanium nitride) and/or liner or barrier layers (e.g., tantalum nitride), if so desired.
  • adhesion layers e.g., titanium nitride
  • liner or barrier layers e.g., tantalum nitride
  • Figure 2H' illustrates the example structure of Figure 2H, including vertical isolation structures 230 of Figure 2D', in accordance with an embodiment.
  • process 110 is optional, such that the vertical isolation structures 230 need not be included in the IC structure.
  • two such structures 230 are present.
  • the vertical isolation structures 230 may be etch resistant to the etch processes used during the IC fabrication (e.g., by the inclusion of an etch-resistant material, such as carbon), and thus, they may further isolate single fins or groups of fins.
  • the vertical isolation structures 230 are isolating the three right-most S/D regions from other portions of the IC structure (such as the left-most S/D regions).
  • Such a configuration may be desired where, for example, those three right-most S/D regions are all of the same polarity (e.g., all n- type or all p-type), thereby allowing those same polarity S/D regions to be isolated from other polarity S/D regions (such as if the left-most S/D regions were the other polarity of n-type and p- type).
  • the vertical isolation structures 230 may also allow for the material of adjacent S/D regions and/or S/D contacts to merge together, thereby providing barriers where desired to prevent said S/D region and/or S/D contact material from merging or contacting undesired material (such as S/D regions or contacts of another polarity). Numerous benefits of the vertical isolation structures 230 will be apparent in light of this disclosure and such vertical isolation structures 230 (where present) may be formed and included in the IC structure where desired.
  • Method 100 of Figure 1 continues with completing 120 integrated circuit (IC) processing, as desired, in accordance with some embodiments.
  • Such additional processing to complete the IC may include back-end or back-end-of-line (BEOL) processing to form one or more metallization layers and/or to interconnect the transistor devices formed, for example. Any other suitable processing may be performed, as will be apparent in light of this disclosure.
  • BEOL back-end or back-end-of-line
  • Any other suitable processing may be performed, as will be apparent in light of this disclosure.
  • the processes 102-120 of method 100 are shown in a particular order in Figure 1 for ease of description. However, one or more of the processes 102-120 may be performed in a different order or may not be performed at all.
  • box 110 is an optional process that need not be performed if the etch resistant vertical structures are not desired.
  • box 112 is an optional process that need not be performed in embodiments employing a gate first process flow, for example. Moreover, such a gate first process flow changes when process 116 is performed, as shown using alternative and optional gate first flow 100', whereby the final gate stack processing is performed 116 prior to performing 114 the S/D processing. Numerous variations on method 100 and the techniques described herein will be apparent in light of this disclosure.
  • the techniques may be used to form one or more transistor devices including any of the following: field-effect transistors (FETs), Fermi filter FETs (FFFETs), tunnel-FETs (TFETs), planar configurations, finned configurations (e.g., fin-FET, tri-gate, dual-gate), and/or nanowire (or nanoribbon or gate-all-around) configurations (having any number of nanowires).
  • FETs field-effect transistors
  • FFFFETs Fermi filter FETs
  • TFETs tunnel-FETs
  • planar configurations finned configurations (e.g., fin-FET, tri-gate, dual-gate), and/or nanowire (or nanoribbon or gate-all-around) configurations (having any number of nanowires).
  • the devices formed may include p-type transistor devices (e.g., p-FFFET or p-TFET) and/or n-type transistor devices (e.g., n
  • Figure 3 illustrates an example cross-sectional view taken along one fin of the IC structure of Figure 2H, specifically taken along the A-A plane, in accordance with some embodiments of the present disclosure.
  • Figure 3 is provided to assist in illustrating different components of the structure of Figure 2H. Therefore, the previous relevant description with respect to each similarly numbered feature is equally applicable to Figure 3.
  • the dimensions of the features shown in Figures 2H and 3 may differ, for ease of illustration.
  • some variations occur between the structures, such as the shape of spacers 250 and the S/D contacts 290 extending all the way to the spacers 250, for example, as is shown in Figure 3.
  • Figure 3' illustrates the IC structure of Figure 3, including shading and patterning to assist with visualizing the material and doping scheme of the S/D regions, in accordance with some embodiments of the present disclosure.
  • the previous relevant description with respect to each similarly numbered feature is equally applicable to Figure 3'.
  • bilayer source region 26 ⁇ including first layer 262' and second layer 264', and drain region 265' each have shading and patterning to assist in visually representing relative included material and doping schemes, in accordance with some embodiments.
  • source region first layer 262' includes diagonal line patterning with a positive slope (i.e., goes from a bottom-left to top-right direction) to visually indicate that it includes different type dopant relative to both source region second layer 264' and drain region 265', which both include diagonal line patterning with a negative slope (i.e., goes from a top-left to bottom-right direction), in accordance with some embodiments.
  • first layer 262' includes one of p-type and n-type dopant
  • second layer 264' and drain region 265' include the other of p-type and n-type dopant relative to the first layer 262', such that one of 262' and 2647265' includes p-type dopant and the other includes n-type dopant.
  • second layer 264' includes shading to indicate that it includes different semiconductor material relative to first layer 262' and drain region 265', in accordance with some embodiments.
  • first layer 262' and drain region 265' may thus include the same semiconductor material; however, the present disclosure need not be so limited, such that they may include different semiconductor material, in other embodiments.
  • source region 26 ⁇ may only include one primary portion similar to the configuration for drain region 265' (and not a bilayer structure as shown in Figure 3'), where the source region 26 ⁇ includes different semiconductor material relative to the drain region and includes different a dopant type.
  • the techniques may be applied to other suitable transistor types. For instance, conventional MOSFET devices may benefit from the inclusion of different semiconductor material in S/D regions, as will be apparent in light of this disclosure. Numerous variations and configurations will be apparent in light of the present disclosure.
  • Figures 4 and 5 illustrate example p-type and n-type FFFET energy band diagrams, respectively, for FFFET devices including S/D regions employing different semiconductor material, in accordance with some embodiments. Note that features from the structures of Figures 2H and 3 are included below the energy band diagrams in a schematic structure to show the different portions of the band diagrams and illustrate how current can flow through FFFET devices. However, the first number of related numerals for each feature has been changed to match the number of the corresponding figure, as the features in Figures 4 and 5 are described with reference to specific material and doping configurations as shown. Therefore, the previous relevant description with respect to those similar features is equally applicable to the schematic structure shown at the bottoms of Figures 4 and 5.
  • Figures 4 and 5 include the shading and patterning of Figure 3' to assist with visually identifying the material and doping differences between the S/D regions.
  • example p-type FFFET schematic structure of Figure 4 includes, from left to right (along with included material), S/D contact 490 (metal or metal alloy), source region first layer 462 (n-type Si), source region second layer 464 (p-type SiGe), channel region 406 (i-type Si), drain region 465 (p-type Si), and S/D contact 490 (metal or metal alloy).
  • the first S/D contact 490 is specifically the source region 261 contact and the second S/D contact 490 is specifically the drain region 265 contact, in this example embodiment.
  • the example n-type FFFET schematic structure of Figure 5 includes, from left to right (along with included material), S/D contact 590 (metal or metal alloy), source region first layer 562 (p-type GaAs), source region second layer 564 (n-type InGaAs), channel region 506 (i-type GaAs), drain region 565 (n-type GaAs), and S/D contact 590 (metal or metal alloy).
  • S/D contact 590 metal or metal alloy
  • source region first layer 562 p-type GaAs
  • source region second layer 564 n-type InGaAs
  • channel region 506 i-type GaAs
  • drain region 565 n-type GaAs
  • S/D contact 590 metal or metal alloy
  • the source regions 461 and 561 include a heterojunction structure, as the source region first layer 462/562 includes different semiconductor material relative to source region second layer 464/564 (e.g., Si compared to SiGe and GaAs compared to InGaAs, respectively). Further, the source regions 461/561 include different semiconductor material relative to the drain regions 465/565, respectively, in the example embodiments. For instance, using the example p-type FFFET device of Figure 4, SiGe is included in the source region 461 (specifically, in second layer 464 of the source region), while Si is the only semiconductor material in the drain region, in the example embodiment. Thus, they include different semiconductor material.
  • the source regions 461 and 561 include a bilayer structure that includes a p-n or n-p diode configuration, as can be understood based on this disclosure. Note that, as a result of the diode in the source region, FFFET devices are sometimes referred to as tunnel source MOSFETs.
  • the source region second layers 464/564 include the same type of doping as their respective drain regions 465/565 (e.g., both p- type and both n-type, respectively), which is the other of n-type and p-type relative to the respective source region first layer 462/562, such that the example p-type FFFET structure of Figure 4 includes a np-i-p doping scheme and the example n-type FFFET structure of Figure 5 includes a pn-i-n doping scheme.
  • the channel regions may be doped, such that the p-type FFFET device may include a np-n-p doping scheme and the n-type FFFET device may include a pn-p-n doping scheme, in accordance with some embodiments.
  • the energy band diagrams for the schematic FFFET structures of Figures 4 and 5 each include energy band diagrams for the off-states 400/500 and on-states 401/501 of the devices, respectively.
  • the energy (E) increases in an upward direction for all diagrams, as shown by the arrow on the left side of each figure.
  • the conduction band edge (Ec) and valence band edge (Ev) are both illustrated, as is common to plot key electron energy levels.
  • the bandgap is the energy difference (in electron volts) between Ec and Ev, as is known in the art.
  • Ev The increase in Ev relative to such a hypothetical homojunction Ev (indicated in dashed lines) is represented as delta Ev and provides the benefit of increasing the barrier height for the charge carriers at that 462/464 layer interface, thereby reducing off-state leakage (particularly for these FFFET devices that include carriers tunneling through the bilayer source tunnel-diode at all conditions or other devices that operate via band-to-band tunneling).
  • the Ge concentration in the SiGe material included in second layer 464 may be in the range of 10-50 percent to provide such bandgap engineering benefits, or any other suitable Ge concentration as will be apparent in light of this disclosure.
  • the channel region potential can block the low energy carriers, as can be understood.
  • the p-FFFET device can still effectively operate in the on-state 401, as can also be understood.
  • the example n-FFFET device of Figure 5 includes a similar principle, except that by including InGaAs in source region second layer 564 in a heterojunction configuration (as opposed to layer 564 including GaAs in a homojunction configuration), a decrease in Ec for that layer 564 can be obtained relative to a homojunction configuration, which is beneficial for the n- type device.
  • the decrease in Ec relative to such a hypothetical homojunction Ec is represented as delta Ec and provides the benefit of increasing the barrier height (albeit, in an inverted fashion relative to that in Figure 4) for the carriers at that 562/564 layer interface, thereby reducing off-state leakage (again, particularly for tunneling devices, such as FFFET devices, that include carriers tunneling at all conditions).
  • the In concentration in the InGaAs material included in second layer 564 may be in the range of 5-70 percent to provide such bandgap engineering benefits, or any other suitable In concentration as will be apparent in light of this disclosure.
  • the channel region potential can block the low energy carriers, as can be understood.
  • the n- FFFET device can still effectively operate in the on-state 501, as can also be understood.
  • the different material that created the heterojunction source region structures have a smaller bandgap than the other semiconductor material included in the source region (e.g., SiGe has a smaller bandgap than Si and InGaAs has a smaller bandgap than GaAs).
  • semiconductor material included in the source region of a transistor formed using the techniques described herein may have a smaller bandgap, a higher valence band edge (Ev), and/or a lower conduction band edge (Ec) relative to one or both of other semiconductor material included in the source region (e.g., the material of the other layer in a bilayer structure) and semiconductor material included in the drain region.
  • other semiconductor material included in the source region e.g., the material of the other layer in a bilayer structure
  • semiconductor material included in the drain region e.g., the material of the other layer in a bilayer structure
  • FIG. 6 illustrates a computing system 1000 implemented with integrated circuit structures and/or transistor devices formed using the techniques disclosed herein, in accordance with some embodiments of the present disclosure.
  • the computing system 1000 houses a motherboard 1002.
  • the motherboard 1002 may include a number of components, including, but not limited to, a processor 1004 and at least one communication chip 1006, each of which can be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein.
  • the motherboard 1002 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 1000, etc.
  • computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., ROM
  • graphics processor e.g., a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • any of the components included in computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques in accordance with an example embodiment.
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 1006 can be part of or otherwise integrated into the processor 1004).
  • the communication chip 1006 enables wireless communications for the transfer of data to and from the computing system 1000.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 1006 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • the computing system 1000 may include a plurality of communication chips 1006.
  • a first communication chip 1006 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1006 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • the processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 1006 also may include an integrated circuit die packaged within the communication chip 1006.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein.
  • multi -standard wireless capability may be integrated directly into the processor 1004 (e.g., where functionality of any chips 1006 is integrated into processor 1004, rather than having separate communication chips).
  • processor 1004 may be a chip set having such wireless capability.
  • any number of processor 1004 and/or communication chips 1006 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing system 1000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set -top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • an ultra-mobile PC a mobile phone
  • desktop computer a server
  • printer a printer
  • a scanner a monitor
  • a set -top box a set -top box
  • an entertainment control unit a digital camera
  • portable music player a digital video recorder
  • Example 1 is an integrated circuit (IC) including: a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region proximate the gate, and source and drain (S/D) regions adjacent the channel region, wherein the source region includes a first semiconductor material including one of n-type and p-type dopant, and wherein the drain region includes a second semiconductor material different than the first semiconductor material, the second semiconductor material including one of n-type and p-type dopant.
  • IC integrated circuit
  • Example 2 includes the subject matter of Example 1, wherein the first semiconductor material is silicon germanium (SiGe) and the second semiconductor material is silicon (Si).
  • Example 3 includes the subject matter of Example 1, wherein the first semiconductor material is indium gallium arsenide (InGaAs) and the second semiconductor material is gallium arsenide (GaAs).
  • Example 4 includes the subject matter of any of Examples 1-3, wherein the first semiconductor material has a smaller energy bandgap than the second semiconductor material.
  • Example 5 includes the subject matter of any of Examples 1-4, wherein the second semiconductor material includes the other of n-type and p-type dopant relative to the first semiconductor material.
  • Example 6 includes the subject matter of any of Examples 1-4, wherein the second semiconductor material includes the one of n-type and p-type dopant included in the first semiconductor material.
  • Example 7 includes the subject matter of any of Examples 1-6, wherein the source region includes a bilayer configuration, such that a third semiconductor material is included in a first layer in the source region and the first semiconductor material is included in a second layer in the source region, wherein the second layer is between the first layer and the channel region.
  • Example 8 includes the subject matter of Example 7, wherein the first layer includes the other of n-type and p-type dopant relative to the first semiconductor material.
  • Example 9 includes the subject matter of Example 7 or 8, wherein the third semiconductor material is the same as the second semiconductor material.
  • Example 10 includes the subject matter of any of Examples 7-9, wherein the second layer is between the first layer and the substrate.
  • Example 11 includes the subject matter of any of Examples 1-10, wherein the first and second semiconductor materials each include group IV semiconductor material.
  • Example 12 includes the subject matter of any of Examples 1-10, wherein the first and second semiconductor materials each include group III-V semiconductor material.
  • Example 13 includes the subject matter of any of Examples 1-12, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).
  • FinFET finned field-effect transistor
  • GAA gate-all-around
  • Example 14 includes the subject matter of any of Examples 1-13, wherein the transistor is a Fermi filter field-effect transistor (FFFET).
  • FFET Fermi filter field-effect transistor
  • Example 15 includes the subject matter of any of Examples 1-13, wherein the transistor is a tunnel field-effect transistor (TFET).
  • Example 16 is a complementary metal-oxide-semiconductor (CMOS) device including the subject matter of any of Examples 1-15.
  • CMOS complementary metal-oxide-semiconductor
  • Example 17 is a computing system including the subject matter of any of Examples 1-16.
  • Example 18 is an integrated circuit (IC) including: a substrate; and a transistor at least one of above and in the substrate, the transistor including a gate, a channel region proximate the gate, a source region adjacent the channel region, the source region including a first layer and a second layer between the first layer and the channel region, the first layer including a first semiconductor material and one of n-type and p-type dopant, the second layer including a second semiconductor material different than the first semiconductor material, wherein the second layer further includes the other of n-type and p-type dopant relative to the first layer, and a drain region adjacent the channel region, the drain region including a third semiconductor material and the other of n-type and p-type dopant relative to the first layer.
  • IC integrated circuit
  • Example 19 includes the subject matter of Example 18, wherein the first semiconductor material is silicon (Si) and the second semiconductor material is silicon germanium (SiGe).
  • Example 20 includes the subject matter of Example 18 or 19, wherein the third semiconductor material is silicon (Si).
  • Example 21 includes the subject matter of Example 18, wherein the first semiconductor material is gallium arsenide (GaAs) and the second semiconductor material is indium gallium arsenide (InGaAs).
  • the first semiconductor material is gallium arsenide (GaAs)
  • the second semiconductor material is indium gallium arsenide (InGaAs).
  • Example 22 includes the subject matter of Example 18 or 21, wherein the third semiconductor material is gallium arsenide (GaAs).
  • GaAs gallium arsenide
  • Example 23 includes the subject matter of any of Examples 18-22, wherein the second semiconductor material has a smaller bandgap than the first semiconductor material.
  • Example 24 includes the subject matter of any of Examples 18-23, wherein the second semiconductor material has a higher valence band edge (Ev) relative to the first semiconductor material.
  • Example 25 includes the subject matter of any of Examples 18-23, wherein the second semiconductor material has a lower conduction band edge (Ec) relative to the first semiconductor material.
  • Ec conduction band edge
  • Example 26 includes the subject matter of any of Examples 18-25, wherein the third semiconductor material is the same as the first semiconductor material.
  • Example 27 includes the subject matter of any of Examples 18-25, wherein the third semiconductor material is different than the first semiconductor material.
  • Example 28 includes the subject matter of any of Examples 18-26, wherein the first layer includes n-type dopant, the second layer includes p-type dopant, and the drain region includes p- type dopant.
  • Example 29 includes the subject matter of any of Examples 18-26, wherein the first layer includes p-type dopant, the second layer includes n-type dopant, and the drain region includes n- type dopant.
  • Example 30 includes the subject matter of any of Examples 18-29, wherein the channel region includes intrinsic or nominally undoped semiconductor material.
  • Example 31 includes the subject matter of any of Examples 18-29, wherein the channel region includes one of n-type and p-type dopant.
  • Example 32 includes the subject matter of any of Examples 18-31, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).
  • FinFET finned field-effect transistor
  • GAA gate-all-around
  • Example 33 includes the subject matter of any of Examples 18-32, wherein the transistor is a Fermi filter field-effect transistor (FFFET).
  • FFET Fermi filter field-effect transistor
  • Example 34 is a complementary metal-oxide-semiconductor (CMOS) device including the subject matter of any of Examples 18-33.
  • CMOS complementary metal-oxide-semiconductor
  • Example 35 is a computing system including the subject matter of any of Examples 18-34.
  • Example 36 is a method of forming an integrated circuit (IC), the method including: forming a source region adjacent a channel region of a transistor, wherein the source region includes a first semiconductor material including one of n-type and p-type dopant; and forming a drain region adjacent to the channel region of the transistor, wherein the drain region includes a second semiconductor material different than the first semiconductor material, the second semiconductor material including one of n-type and p-type dopant.
  • IC integrated circuit
  • Example 37 includes the subject matter of Example 36, wherein the first semiconductor material is silicon germanium (SiGe) and the second semiconductor material is silicon (Si).
  • Example 38 includes the subject matter of Example 36, wherein the first semiconductor material is indium gallium arsenide (InGaAs) and the second semiconductor material is gallium arsenide (GaAs).
  • Example 39 includes the subject matter of any of Examples 36-38, wherein the first semiconductor material has a smaller energy bandgap than the second semiconductor material.
  • Example 40 includes the subject matter of any of Examples 36-39, wherein the second semiconductor material includes the other of n-type and p-type dopant relative to the first semiconductor material.
  • Example 41 includes the subject matter of any of Examples 36-39, wherein the second semiconductor material includes the one of n-type and p-type dopant included in the first semiconductor material.
  • Example 42 includes the subject matter of any of Examples 36-41, wherein the source region includes a bilayer configuration, such that a third semiconductor material is included in a first layer in the source region and the first semiconductor material is included in a second layer in the source region, wherein the second layer is between the first layer and the channel region.
  • Example 43 includes the subject matter of Example 42, wherein the first layer includes the other of n-type and p-type dopant relative to the first semiconductor material.
  • Example 44 includes the subject matter of Example 42 or 43, wherein the third semiconductor material is the same as the second semiconductor material.
  • Example 45 includes the subject matter of any of Examples 42-44, wherein the second layer is between the first layer and the substrate.
  • Example 46 includes the subject matter of any of Examples 36-45, wherein the first and second semiconductor materials each include group IV semiconductor material.
  • Example 47 includes the subject matter of any of Examples 36-45, wherein the first and second semiconductor materials each include group III-V semiconductor material.
  • Example 48 includes the subject matter of any of Examples 36-47, wherein the channel region includes a configuration that is at least one of planar, finned, double-gate, tri-gate, finned field-effect transistor (FinFET), nanowire, nanoribbon, and gate-all-around (GAA).
  • FinFET finned field-effect transistor
  • GAA gate-all-around
  • Example 49 includes the subject matter of any of Examples 36-48, wherein the transistor is a Fermi filter field-effect transistor (FFFET).
  • FFET Fermi filter field-effect transistor
  • Example 50 includes the subject matter of any of Examples 36-48, wherein the transistor is a tunnel field-effect transistor (TFET).
  • TFET tunnel field-effect transistor

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne des techniques de formation de transistors à effet tunnel comprenant des régions de source et de drain (S/D) utilisant différents matériaux. À l'aide d'une ingénierie de bande interdite de matériau, les techniques améliorent la capacité de dispositifs de transistors qui utilisent une tunnellisation quantique, tels que des transistors à effet de champ tunnel (TFET) et des TEC à filtre de Fermi (FFFET), en vue de résister à des courants de fuite dans l'état bloqué de la source au drain (à travers le canal) et de la source à la masse/substrat. L'ingénierie de bande interdite de matériau peut incorporer un composant de décalage de bande à base de matériau en vue de commander une fuite dans l'état bloqué. Un tel décalage de bande peut s'étendre sur le décalage de bande d'énergie limitée pouvant être obtenu à l'aide de conceptions de matériau classiques (par exemple, des conceptions de matériau à composition unique), car au moyen de telles conceptions de matériau classiques, au-dessus d'une concentration de dopage de seuil, il n'y a pas de diminution supplémentaire du courant de fuite pour une source donnée à une tension de drain à des dimensions fixes. Par exemple, l'augmentation du décalage de bande peut augmenter la barrière que les porteuses doivent surmonter en vue d'atteindre la région de canal, ce qui permet de réduire les fuites dans l'état bloqué.
PCT/US2016/054724 2016-09-30 2016-09-30 Transistors à effet tunnel comprenant des régions de source/drain utilisant différents matériaux semi-conducteurs Ceased WO2018063310A1 (fr)

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TW106127969A TWI761363B (zh) 2016-09-30 2017-08-17 積體電路、ｃｍｏｓ裝置、電腦系統及形成積體電路的方法

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US20060258072A1 (en) * 2005-05-13 2006-11-16 Kavalieros Jack T Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions
US20100200916A1 (en) * 2009-02-12 2010-08-12 Infineon Technologies Ag Semiconductor devices
US20110084319A1 (en) * 2009-10-08 2011-04-14 Chartered Semiconductor Manufacturing, Ltd. Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current
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