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WO2015099744A1 - Dispositifs fet à effet tunnel complémentaires et leur procédé de formation - Google Patents

Dispositifs fet à effet tunnel complémentaires et leur procédé de formation Download PDF

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Publication number
WO2015099744A1
WO2015099744A1 PCT/US2013/077873 US2013077873W WO2015099744A1 WO 2015099744 A1 WO2015099744 A1 WO 2015099744A1 US 2013077873 W US2013077873 W US 2013077873W WO 2015099744 A1 WO2015099744 A1 WO 2015099744A1
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Prior art keywords
doped
tfet
type
region
semiconductor material
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PCT/US2013/077873
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English (en)
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Aleksandar Aleksov
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Intel Corp
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Intel Corp
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Application filed by Intel Corp filed Critical Intel Corp
Priority to KR1020167012963A priority Critical patent/KR102162676B1/ko
Priority to PCT/US2013/077873 priority patent/WO2015099744A1/fr
Priority to EP13900285.1A priority patent/EP3087611A4/fr
Priority to US15/036,058 priority patent/US9786769B2/en
Priority to TW106109794A priority patent/TWI620316B/zh
Priority to TW103140822A priority patent/TWI549292B/zh
Priority to TW105119211A priority patent/TWI587508B/zh
Priority to CN201410858223.1A priority patent/CN104752496B/zh
Priority to DE102014017506.5A priority patent/DE102014017506B4/de
Publication of WO2015099744A1 publication Critical patent/WO2015099744A1/fr
Anticipated expiration legal-status Critical
Priority to US15/673,359 priority patent/US10269942B2/en
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    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/474—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure
    • H10K10/476—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising a multilayered structure comprising at least one organic layer and at least one inorganic layer
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    • H10K10/481—Insulated gate field-effect transistors [IGFETs] characterised by the gate conductors
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    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
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Definitions

  • tri-gate transistors In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down.
  • tri-gate transistors In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and because they enable a less complicated tri-gate fabrication process.
  • the fabrication process for tri-gate transistors often encounters problems when aligning the bottom of the metal gate electrode with the source and drain extension tips at the bottom of the transistor body (i.e., the "fin").
  • the tri-gate transistor is formed on a bulk substrate, proper alignment is needed for optimal gate control and to reduce short-channel effects.
  • the source and drain extension tips are deeper than the metal gate electrode, punch-through may occur. Alternately, if the metal gate electrode is deeper than the source and drain extension tips, the result may be an unwanted gate capacitance parasitic. Many different techniques have been attempted to reduce junction leakage of transistors. However, significant improvements are still needed in the area of junction leakage suppression.
  • Tunneling Field Effect Transistors are promising devices in that they promise significant performance increase due to a steeper sub-threshold slope.
  • the two materials used to manufacture a TFET device heteroj unction are GaSb (p-type) and InAs (n-type).
  • the current TFET devices suffer from lower currents than Si-FETs at the same technology node and from a parasitic tunneling leakage current at pinch-off i.e., a reduced on/off ratio. The reason for this lies mainly in the low bandgap energy and the low conduction band density of states (CBDOS or Nc) of InAs.
  • Fig. 1A illustrates a general TFET structure for n-type TFET.
  • Fig. IB illustrates a general TFET structure for p-type TFET.
  • Fig. 2 illustrates a plot of band diagram for an n-TFET, according to one embodiment of the disclosure.
  • Figs. 3A-D illustrate plots with band alignment for p-type and n-type
  • Figs. 4A-D illustrate plots with band alignment for p-type and n-type
  • TFETs using oxide and/or organic semiconductor materials according to one embodiment of the disclosure.
  • Fig. 5A illustrates band diagrams of oxides and comparative semiconductors aligned according to their charge neutrality levels.
  • Fig. 5B illustrates band diagrams of oxides and comparative semiconductors aligned according to their vacuum levels.
  • Figs. 6A-H illustrate a manufacturing process flow when using oxide semiconductor materials to form a TFET, according to one embodiment of the disclosure.
  • Figs. 7A-H illustrate a manufacturing process flow when using organic semiconductor materials to form a TFET, according to one embodiment of the disclosure.
  • Fig. 8 is a smart device or a computer system or an SoC (System-on-
  • the embodiments describe materials comprising the TFET junction that have a heterojunction with broken band alignment.
  • "broken band alignment" for n-TFET refers to gap between valance band energy of material used for source active region and conduction band energy of material used for channel region (the channel region is the semiconductor material of the gate-region including gate underlap).
  • the channel and drain region material is usually the same (with different doping levels), however in general it can be comprised out of different materials according to various embodiments).
  • the broken band i.e., difference between one band to another band
  • the broken gap is the gap from the conduction band of the source region (which is n-doped) to the valence band of the channel region.
  • the materials forming the heterojunction have a high effective valence band density of states (VBDOS or Nv) for the p-type and high effective conduction band density of states (CBDOS or Nc) for the n-type to obtain high currents comparable to or exceeding current Si-FETs.
  • the materials for forming TFETs have bandgaps that are wider than the potential difference created by the operating voltage (VDD) to suppress unwanted leakage currents at pinch off.
  • TFET enabling C-TFET logic i.e., complementary TFET logic
  • device performance substantially equal to or exceeding that of Si-FETs at the same technology node, while retaining or improving the sub-threshold slope and minimizing the off-state leakage current of the devices/circuit.
  • alternative materials i.e., groups of materials other than what are used today for forming TFETs (i.e., standard Group IV or IV-IV alloys or classical III-V materials).
  • transparent inorganic semiconductor oxide materials in combination with classic standard Group III-V, IV-IV, and IV materials are used for forming TFETs.
  • transparent inorganic semiconductor oxide materials in combination with organic semiconductor materials are used for forming TFETs.
  • only organic semiconductor materials are used for forming active regions of TFETs to alleviate aforementioned TFET device drawbacks.
  • the embodiments enable broken bandgap alignment for TFET devices.
  • the embodiments exhibit high DOS (density of states) for high performance in the conduction and the valence bands (not necessarily in the same material) such that both high performance p-TFETs and n-TFETs enable complementary tunneling FET logic (C-TFET) with currents at higher levels than current TFETs.
  • C-TFET complementary tunneling FET logic
  • the currents may well reach or exceed the current levels in Si-FETs at an identical technology node.
  • Some embodiments use materials with higher bandgaps to suppress off- state leakage currents. Such embodiments show superior leakage performance to current TFETs. Some embodiments enable such logic devices on different substrates than Si (such as but not limited to glass, polymers) and/or transparent devices (using electrodes made from transparent or semi/transparent material). For example, transparent semiconducting oxides and organic semiconductors can be combined to achieve transparent devices. In one embodiment, only organic semiconductors are used for forming the active regions of TFETs. Some embodiments describe methods for fabricating TFETs with low temperature processes which allow for making higher performance devices on flexible substrates. In such embodiments, higher performance flexible logic can be achieved that may become crucial for extending the computing continuum to the wearable and flexible electronic space.
  • semiconductor/organic heterojunction may allow for vertically stacked devices to be manufactured. In such embodiments, significant reduction is achieved in the circuit footprint at the same technology node.
  • the embodiments describe materials that exhibit more efficient gate control than traditional TFET materials because the described materials have a lower ⁇ ⁇ than classical III-V semiconductors GaSb and InAs used in TFETs today.
  • organic semiconductors described have extremely low ⁇ ⁇ of 2.5 to 3.5 which allow for better gate control for both n- TFET or p-TFET (with a p " or intrinsic control layer) as the voltage drop is divided between the gate dielectric and the gate-channel layer (i.e., the semiconductor).
  • signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting.
  • any represented signal may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
  • connection means a direct electrical connection between the things that are connected, without any intermediary devices.
  • coupled means either a direct electrical connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices.
  • circuit means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
  • signal means at least one current signal, voltage signal or data/clock signal.
  • scaling generally refers to converting a design (schematic and layout) from one process technology to another process technology.
  • scaling generally also refers to downsizing layout and devices within the same technology node.
  • scaling may also refer to adjusting (e.g., slow down) of a signal frequency relative to another parameter, for example, power supply level.
  • substantially generally refer to being within +/- 20% of a target value.
  • the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals.
  • MOS metal oxide semiconductor
  • the transistors also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, TFETs, or other devices implementing transistor functionality like carbon nano tubes or spintronic devices.
  • Source and drain terminals may be identical terminals and are interchangeably used herein.
  • transistors for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure.
  • MN indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term “MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).
  • Fig. 1A illustrates a general TFET structure 100 for n-type TFET.
  • a TFET has a gate terminal formed from Gate metal over a dielectric material (e.g., high-K material).
  • the dielectric material couples an intrinsic or lightly doped n-type active region formed of Material B.
  • the minimum effective channel length under the gate i.e., LG
  • n + doped active region On either side of the slightly doped n-type active region (i.e., n ⁇ doped) are p + doped active region forming the source region and n + doped active region forming the drain region.
  • the p + doped region is formed of Material A while the n + doped region is formed of Material B.
  • Metal contacts are coupled to each of the p + and n + doped regions to provide source and drain contacts, respectively.
  • the n " doped active region under the Gate metal may overextend forming a Gate underlap as shown.
  • Material C (different from Materials A and B) can also be used to form drain region which is n-i- doped region.
  • Material A is selected from the classic Group
  • III-V, IV-IV, and IV e.g., Ge, GaSb, etc.
  • Material B is selected from transparent oxide semiconductors (e.g., a-Ga203, P-Ga203, ⁇ 2 0 3 , or SnC ).
  • Material A is selected from organic semiconductors (e.g., P3HT, PCBM, PEDOT:PSS, CuPc, CoPc or other organic materials with a broken band alignment to the oxide semiconductors (i.e., valance band of these organic semiconductors is above (i.e., closer to vacuum level) the conduction band of the oxides), where P3HT is Poly(3-hexylthiophene-2,5-diyl); PCBM is Phenyl-C61- butyric acid methyl ester; PEDOT:PSS is poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate), CuPc is Copper(II) phthalocyanine; CoPc is Cobolt phthalocyanine)
  • Material B is selected from transparent or semi-transparent oxide semiconductors (e.g., Ga2 ( 3 ⁇ 4, ln 2 0 3 , or SnC ).
  • Material A is selected from organic semiconductors (e.g., p++ P3HT, PCBM, PEDOT:PSS, CuPc, CoPc, etc.,) while Material B is also selected from organic semiconductors (e.g., F16CuPc, SnCbPc, etc., where F16CuPc is Copper hexadecafluoro phthalocyanine).
  • organic semiconductors e.g., p++ P3HT, PCBM, PEDOT:PSS, CuPc, CoPc, etc.
  • Material B is also selected from organic semiconductors (e.g., F16CuPc, SnCbPc, etc., where F16CuPc is Copper hexadecafluoro phthalocyanine).
  • Fig. IB illustrates a general TFET structure 120 for p-type TFET.
  • a TFET has a gate terminal formed from Gate metal over a dielectric material (e.g., high-K material).
  • the dielectric material couples a slightly doped p-type active region (i.e., p " doped) formed of Material A.
  • the minimum effective channel length under the gate i.e., LG
  • n + doped active region forming the source region and p + doped active region forming the drain region.
  • the n + doped region is formed of Material B while the p + doped region is formed of Material A.
  • Material C (different from Materials A and B) can also be used to form drain region which is n-i- doped region. Materials A and B are described with reference to Fig. 1A. Referring back to Fig. IB, metal contacts are coupled to each of the n + and p + doped regions to provide source and drain contacts respectively. The p " doped active region under the Gate metal may overextend forming a Gate underlap as shown.
  • the TFET n-TFET and/or p-TFET is a FinFet, Tri-Gate, or square nano-wire based device.
  • Fig. 2 illustrates a plot 200 showing band diagram for a TFET, according to one embodiment of the disclosure. It is pointed out that those elements of Fig. 2 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • x-axis is distance and y-axis is bandgap energy E in electron
  • the solid lines indicate band alignment without applied external voltage (i.e. neutral/off state).
  • the dashed lines indicate band alignment when operating voltage to drain region is applied and when no voltage is applied to the gate region (i.e., off state).
  • the dotted lines indicate band alignment when operating voltage is applied to both drain and gate regions (i.e., on state).
  • the solid, dashed, and dotted lines refer to the same device in different modes of operation.
  • the Plot 200 shows band alignment for a p-type TFET having a source region made from highly doped p-type (i.e., p ++ doped) Material A from classic Group III-V, IV-IV, and IV (e.g., Ge, GaSb).
  • p ++ doped Ge energy for the conductance band (i.e., E C Ge) is about 4eV while the energy for valance band (i.e., EvGe) is lower than E C Ge but higher than the energy for the conductance band of the drain region.
  • the drain region is made from highly doped n- type (i.e., n + doped) transparent oxide semiconductor material (e.g., a-Ga203, ⁇ - Ga203, ⁇ ⁇ 2 0 3 , or SnC ).
  • n- type i.e., n + doped
  • transparent oxide semiconductor material e.g., a-Ga203, ⁇ - Ga203, ⁇ ⁇ 2 0 3 , or SnC .
  • the energy of conductance band for SnC i.e., E c s n o2
  • E V Ge forming a broken bandgap.
  • the region between the drain region and the source region is a lightly doped n-type region (i.e., n ) made from transparent oxide semiconductor material (e.g., a-Ga203, -Ga203, ln 2 0 3 , or SnC ).
  • n lightly doped n-type region
  • transparent oxide semiconductor material e.g., a-Ga203, -Ga203, ln 2 0 3 , or SnC .
  • the gate in a device like this would usually/ideally go all around the channel material/region (e.g., lightly doped part of Material B) or at least be contacting this region from one side. There will be a dielectric material (high-k or not) between gate metal and the channel material/region (i.e., the lightly doped region of Material B).
  • the gate is a placeholder showing where the gate spatially would be located along the X-Axis.
  • Figs. 3A-D illustrate band alignments for p-type and n-type TFETs using oxide semiconductor materials, according to one embodiment of the disclosure. It is pointed out that those elements of Figs. 3A-D having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • Fig. 3A illustrates a plot 300 showing band alignment for p-TFET, according to one embodiment.
  • Fig. 3B illustrates a plot 320 showing band alignment for n-TFET, according to one embodiment.
  • Fig. 3C illustrates a plot 330 showing band alignment for p-TFET, according to another embodiment.
  • FIG. 3D illustrates a plot 340 showing band alignment for n-TFET, according to another embodiment.
  • transparent oxide semiconductor materials are used for n-type material while classic Group III-V, IV-IV, and IV semiconductor materials are used for p-type materials.
  • the top of each box or rectangle representing the semiconductor material is the conduction band (CB) and the bottom of each box is the valance band (VB).
  • the transparent oxide semiconductor materials are selected from a group comprising: P-Ga203, ln 2 0 3 or Sn02.
  • -Ga203 has a single conduction band minimum at ⁇ -point (i.e., gamma point).
  • Nc of -Ga203 is approximately 5.7xl0 18 cm "3 due to the high effective mass of about 0.34mo. This is about two orders of magnitude higher than Nc of InAs.
  • ⁇ ⁇ of -Ga203 is about 10, which is lower than ⁇ ⁇ of InAs which is about 15.2.
  • -Ga203 has a wide bandgap of about 4.7eV to 4.9eV and a high breakdown field of about 8xl0 6 V/cm.
  • the electron affinity of -Ga203 is in the range of 4.7eV to 5.1eV.
  • direct bandgap of Sn02 is about 3.6eV and its electron affinity is about 4.7eV to 5.0eV.
  • the effective mass (i.e., DOS) of SnC is about 0.275mo, yielding an Nc of about 4.1xl0 18 cm 3 , which is lower than in ⁇ - Ga203, but still over one order of magnitude higher than in InAs.
  • SnC may have n- type doping concentrations as high as 2-8xl0 20 cm ⁇ 3 .
  • the source region is formed from any one of highly doped classic Group III-V, IV-IV, and IV material (e.g., p ++ doped Ge)
  • the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of a-Ga203, -Ga203, SnC , In2 ( 3 ⁇ 4).
  • the gate overlapping region is formed from slightly doped (i.e., n " doped) n-type transparent oxide semiconductor material.
  • the source region is formed from any one of highly doped classic Group III-V, IV- IV, and IV materials (e.g., p ++ doped Ge)
  • the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of a- Ga203, -Ga203, SnC , In2(3 ⁇ 4).
  • the gate overlapping region is formed from slightly doped (i.e., p ⁇ doped) p-type material from any one of classic Group III-V, IV-IV, and IV materials.
  • the source region is formed from any one of highly doped classic Group III-V, IV-IV, and IV material (e.g., p ++ doped GaSb)
  • the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of a-Ga203, P-Ga2(3 ⁇ 4, GaGdOx, Sn02, ImCb).
  • the gate overlapping region is formed from slightly doped (i.e., n ⁇ doped) n-type transparent oxide semiconductor material.
  • the source region is formed from any one of highly doped classic Group III-V, IV-IV, and IV material (e.g., p ++ doped GaSb)
  • the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of a-Ga203, P-Ga2(3 ⁇ 4, GaGdOx, SnC , ImCb).
  • the gate overlapping region is formed from slightly doped (i.e., p " doped) p-type material from any one of classic Group III-V, IV-IV, and IV material (e.g., p " doped Ge).
  • Ga203 i.e., GaGdOx where 'x' is an integer, is a dielectric to enable
  • GaAs MOSFETs to achieve low interface density for a GaSb/ -Ga203 or GaSb/a- Ga203 junction.
  • a-Ga203, or -Ga203 acts like GaSb oxide.
  • interface state passivation methods are used to reduce or eliminate interface states at the transition from one material to the other material at the heteroj unction interface.
  • the valence band of GaSb is at about 4.9eV which provides a GaSb/ -Ga203 p/n heterojunction with a broken bandgap with a break between the p " doped GaSb valance band and the n " doped -Ga203 conduction band of up to 0.2eV.
  • p-type doped Ge, SiGe, or Si is combined with n-type doped Sn02 to form a TFET.
  • Sn is a Group IV element and as such isoelectric to Ge and Si, and Sn02 has a similar structure to Ge02 and S1O2. This electronic and structural similarity between Si, Ge, SiGe, and Sn on one side and
  • Figs. 5A-B illustrate plots for estimating band alignment for different material combinations.
  • Figs. 4A-D illustrate plots of band alignment for p-type and n-type
  • Fig. 4A illustrates a plot 400 showing band alignment for p-TFET, according to one embodiment.
  • Fig. 4B illustrates a plot 420 showing band alignment for n-TFET, according to one embodiment.
  • Fig. 4C illustrates a plot 430 showing band alignment for p-TFET, according to another embodiment.
  • Fig. 4D illustrates a plot 440 showing band alignment for n-TFET, according to another embodiment.
  • transparent oxide semiconductor materials are used for n-type material while organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • organic semiconductor materials are used for p-type materials.
  • semiconductor materials are used for both p-type and n-type materials.
  • the top of each box or rectangle representing the semiconductor material is the conduction band (CB) and the bottom of each box is the valance band (VB).
  • the source region is formed from organic semiconductor material
  • the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of -Ga203, Sn02, ImCb).
  • p-type organic semiconductor materials include P3HT, MDMO-PPV (i.e., Poly[2-methoxy-5-(3,7-dimethyloctyloxy)-l,4-phenylene- vinylene]), PEDOT:PSS, CuPc, CoPc.
  • the HOMO energies are about 4.7eV to 5. leV for P3HT, MDMO-PPV, and Pentacene.
  • HOMO refers to the highest occupied molecular orbital.
  • LUMO refers to highest unoccupied molecular orbital.
  • LUMO is the equivalent of the conduction band edge Ec.
  • the HOMO energies for PEDOT:PSS is about 5.0eV to 5.3eV.
  • the band positions may be affected by deposition methods and post deposition treatment. P3HT, PEDOT:PSS can be heavily doped (i.e., PDOT:PSS hole concentrations greater than 3xl0 20 cm ⁇ 3 ).
  • PEDOT:PSS is about 1.7eV to 2.0eV.
  • N v of HOMO is well above several 10 18 cm 3 .
  • the gate region is formed from lightly doped (i.e., n ⁇ doped) n- type transparent oxide semiconductor material.
  • Other organic material not listed here, but with suitable band alignments and doping properties, can also be utilized.
  • the source region is formed from p-type organic semiconductor material (e.g., one of p ++ doped P3HT, MDMO- PPV, PEDOT:PSS), the drain region is formed from highly doped (i.e., n + doped) transparent oxide semiconductor material (e.g., one of a-Ga20, P-Ga203, Sn02, ⁇ 2 ⁇ 3).
  • the gate overlapping region is formed from slightly doped (i.e., p- doped) p-type material from p-type organic semiconductor material.
  • Other organic material not mentioned here, but with suitable band alignments and doping properties can also be utilized.
  • the band alignment shows a broken gap between OeV to 0.3eV with values around OeV to O.leV when using PEDOT:PSS and higher with P3HT, CuPc, or CoPc.
  • undoped P3HT also serves as the p- material which can also be CoPc or CuPc.
  • Other organic material not mentioned here, but with suitable band alignments and doping properties can also be utilized.
  • adding a surface segregated organic monolayer allows tuning of the surface dipole and thus of the band alignment.
  • the source region is formed from organic semiconductor material (e.g., one of p ++ doped P3HT, MDMO-PPV, PEDOT:PSS)
  • the drain region is formed from highly doped (i.e., n + doped) organic semiconductor material (e.g., F16CuPc, SnCbPc, etc.).
  • the gate overlapping region is formed from slightly doped (i.e., n ⁇ doped) n-type organic semiconductor material (e.g., F16CuPc, SnCkPc, etc.).
  • the source region is formed from any one of highly doped organic semiconductor material (e.g., one of p ++ doped P3HT, MDMO-PPV, PEDOT:PSS), the drain region is formed from highly doped (i.e., n + doped) organic semiconductor material (e.g., F16CuPc, SnCbPc, etc.).
  • the gate region is formed from slightly doped (i.e., p ⁇ doped) p-type material from organic semiconductor material (e.g., one of p ++ doped P3HT, MDMO-PPV, PEDOT:PSS).
  • organic n-type semiconductors such as F16CuPc with LUMO of about 4.9eV below Ev ac form an excellent fit to the HOMO level e.g., of P3HT.
  • mobility of organic materials is very low, in one embodiment, the intrinsic device performance may not be defined by it for TFETs provided the gate is within the length of the carrier wavelength and the gate underlap is shorter than that.
  • the heavily doped regions reduce parasitic resistance due to the high carrier
  • PDOT-PSS can have conductivities approaching those of ITO.
  • Fig. 5A illustrates a plot 500 with band diagrams of oxides and comparative semiconductors aligned according to their charge neutrality levels. It is pointed out that those elements of Fig. 5A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • each box representing the semiconductor oxide is the conduction band (CB) and the bottom of each box is the valance band (VB).
  • CB conduction band
  • VB valance band
  • the difference between CB and VB for each box is the bandgap energy for that semiconductor oxide.
  • Fig. 5B illustrates a plot 520 with band diagrams of oxides and comparative semiconductors aligned according to their vacuum levels. It is pointed out that those elements of Fig. 5B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • a number of semiconductors are listed according to their vacuum levels and their bandgap energies in eV are plotted on the y-axis.
  • the top of each box representing the semiconductor oxide is the conduction band (CB) and the bottom of each box is the valance band (VB).
  • CB conduction band
  • VB valance band
  • the difference between CB and VB for each box is the work function for that semiconductor oxide.
  • the actual band offsets and band alignments may be somewhere in-between the results in Fig. 5A and Fig. 5B. In most cases, the better guidance for the band offsets is given by the band alignments according to their charge neutrality level (CNL).
  • CNL charge neutrality level
  • FIGs. 6A-H illustrate a manufacturing process flow when using oxide semiconductor materials to form a TFET, according to one embodiment of the disclosure. It is pointed out that those elements of Figs. 6A-H having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • n- Electrode e.g., metal
  • a metal is formed on a first electrode
  • n-type transparent semiconductor oxide material layer e.g., n + doped P-Ga203
  • a slightly doped n-type transparent semiconductor oxide material layer e.g., n " doped P-Ga2(3 ⁇ 4) is formed over the highly doped transparent semiconductor oxide material layer (e.g., n + P-Ga203).
  • a highly doped p-type semiconductor material from the classic Group III-V, IV-IV, or IV (e.g., p + doped Ge) material is deposited over the slightly doped n-type transparent semiconductor oxide material layer (e.g., n " doped P-Ga203).
  • a photo-resist (PR) layer is deposited over the highly doped p-type semiconductor material. The manufacturing process is described with reference to the stack of layers 600 in Fig. 6A.
  • Fig. 6B illustrates process 620 when F-based (Fluorine based) ICP
  • RIE Inductively Coupled Plasma
  • This process is applied to remove the photo-resist layer and etch the highly doped p-type semiconductor material (p + doped Ge).
  • ICP-RIE stops at the lightly doped n " P-Ga2C>3 transparent semiconductor oxide layer.
  • Fig. 6C illustrates process 630 in which n " P-Ga203 transparent semiconductor oxide layer is selectively etched.
  • Cl-based (Chlorine based) RIE process may be used for selectively etching layer of n ⁇ ⁇ - Ga203.
  • F-gas is used into the mix to slightly etch Ge.
  • a beveled etched wall is formed which is used for gate metal self alignment.
  • Fig. 6D illustrates process 640 in which high-K gate dielectric material (e.g., ALD— atomic layer deposition) 641 is deposited over the beveled etched n ⁇ ⁇ -
  • Fig. 6E illustrates process 650 in which gate metal 651 is deposited over layer 641 of high-K gate dielectric material.
  • Fig. 6F illustrates process 660 in which low-K ILD 661 material is deposited over layer 651, where ILD is Inter Layer Dielectric which is a low-K material used for interconnect stack.
  • Fig. 6G illustrates process 670 in which excess material over the layer of low-K ILD 661 material is removed i.e., planarized.
  • Fig. 6H illustrates process 680 in which electrode 681 is formed by depositing metal over the planaized surface. In this example, a p-Electrode is formed. Not all processes are shown. For example, formation of vias and vertical connections for n-Electrodes. However, those processes can be performed using well known methods.
  • FIGs. 7A-H illustrate a manufacturing process flow when using organic semiconductor materials to form a TFET, according to one embodiment of the disclosure. It is pointed out that those elements of Figs. 7A-H having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.
  • n-Electrode e.g., metal
  • a Substrate e.g., Si Substrate
  • highly n-type doped transparent semiconductor oxide material layer e.g., n + doped P-Ga2(3 ⁇ 4) is formed over the n-Electrode.
  • a slightly doped n-type transparent semiconductor oxide material layer e.g., n " ⁇ - Ga203 is formed over the highly doped transparent semiconductor oxide material layer (e.g., n + P-Ga203).
  • a highly doped p-type organic semiconductor material e.g., p + P3HT
  • n-type transparent semiconductor oxide material layer e.g., n " P-Ga203
  • a photo-resist layer is deposited over the highly doped p-type semiconductor material.
  • Fig. 7B illustrates process 720 when F-based ICP RIE is applied to the photo-resist. This process is applied to remove the photo-resist layer and etch the highly doped p-type organic semiconductor material (p + P3HT). The process of ICP-RIE stops at the lightly doped n ⁇ P-Ga2(3 ⁇ 4 transparent semiconductor oxide layer.
  • Fig. 7C illustrates process 730 in which n ⁇ P-Ga2C>3 transparent semiconductor oxide layer is selectively etched.
  • Cl-based RIE process may be used for selectively etching layer of n " P-Ga203.
  • C -gas is used into the mix to slightly etch the p-type organic semiconductor (e.g., p + doped P3HT).
  • a beveled etched wall is formed which is used for gate metal self alignment.
  • Fig. 7D illustrates process 740 in which high-K gate dielectric material (e.g., ALD— atomic layer deposition) 741 is deposited over the beveled etched n " -Ga203 and p + P3HT.
  • Fig. 7E illustrates process 750 in which gate metal 751 is deposited over layer 741 of high-K gate dielectric material.
  • Fig. 7F illustrates process 760 in which low-K ILD 761 is deposited over layer 751.
  • FIG. 7G illustrates process 770 in which excess material over the layer of low-K ILD 761 is removed i.e., planarized.
  • Fig. 7H illustrates process 780 in which electrode 781 is formed by depositing metal over the planaized surface.
  • a p-Electrode is formed. Not all processes are shown. For example, formation of vias and vertical connections for n- Electrodes. However, those processes can be performed using well known methods.
  • Fig. 8 is a smart device or a computer system or an SoC (System-on-
  • Fig. 8 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used.
  • computing device 1700 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1700.
  • computing device 1700 includes a first processor
  • the various embodiments of the present disclosure may also comprise a network interface within 1770 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.
  • processor 1710 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means.
  • the processing operations performed by processor 1710 include the execution of an operating platform or operating system on which applications and/or device functions are executed.
  • the processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1700 to another device.
  • the processing operations may also include operations related to audio I/O and/or display I O.
  • computing device 1700 includes audio subsystem 1720, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1700, or connected to the computing device 1700. In one embodiment, a user interacts with the computing device 1700 by providing audio commands that are received and processed by processor 1710. [0066] Display subsystem 1730 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1700.
  • audio subsystem 1720 represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1700,
  • Display subsystem 1730 includes display interface 1732, which includes the particular screen or hardware device used to provide a display to a user.
  • display interface 1732 includes logic separate from processor 1710 to perform at least some processing related to the display.
  • display subsystem 1730 includes a touch screen (or touch pad) device that provides both output and input to a user.
  • I/O controller 1740 represents hardware devices and software components related to interaction with a user. I/O controller 1740 is operable to manage hardware that is part of audio subsystem 1720 and/or display subsystem 1730. Additionally, I/O controller 1740 illustrates a connection point for additional devices that connect to computing device 1700 through which a user might interact with the system. For example, devices that can be attached to the computing device 1700 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
  • I/O controller 1740 can interact with audio subsystem 1720 and/or display subsystem 1730.
  • input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1700.
  • audio output can be provided instead of, or in addition to display output.
  • display subsystem 1730 includes a touch screen
  • the display device also acts as an input device, which can be at least partially managed by I/O controller 1740.
  • I/O controller 1740 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1700.
  • the input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
  • computing device 1700 includes power management 1750 that manages battery power usage, charging of the battery, and features related to power saving operation.
  • Memory subsystem 1760 includes memory devices for storing information in computing device 1700. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1760 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1700.
  • Elements of embodiments are also provided as a machine -readable medium (e.g., memory 1760) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein).
  • the machine- readable medium e.g., memory 1760
  • embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
  • BIOS a computer program
  • a remote computer e.g., a server
  • a requesting computer e.g., a client
  • a communication link e.g., a modem or network connection
  • Connectivity 1770 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1700 to communicate with external devices.
  • the computing device 1700 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.
  • Connectivity 1770 can include multiple different types of connectivity.
  • the computing device 1700 is illustrated with cellular connectivity 1772 and wireless connectivity 1774.
  • Cellular connectivity 1772 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards.
  • Wireless connectivity (or wireless interface) 1774 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.
  • Peripheral connections 1780 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1700 could both be a peripheral device ("to" 1782) to other computing devices, as well as have peripheral devices ("from” 1784) connected to it.
  • the computing device 1700 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1700. Additionally, a docking connector can allow computing device 1700 to connect to certain peripherals that allow the computing device 1700 to control content output, for example, to audiovisual or other systems.
  • the computing device 1700 can make peripheral connections 1780 via common or standards-based connectors.
  • Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Fire wire, or other types.
  • USB Universal Serial Bus
  • MDP MiniDisplayPort
  • HDMI High Definition Multimedia Interface
  • Fire wire or other types.
  • first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or
  • a TFET which comprises: a substrate; a doped first region, disposed above the substrate, having p-type material selected from a group consisting of Group III-V, IV-IV, and only IV of a periodic table; a doped second region, disposed above the substrate, having transparent or semi- transparent oxide n-type semiconductor material; and a gate stack coupled to the doped first and second regions.
  • the transparent or semi-transparent oxide n-type semiconductor material is selected from a group consisting of a-Ga2-03, P-Ga2-03, ⁇ 2 0 3 , and SnC .
  • the TFET is a FinFET, Tri-Gate, or square nano-wire based device.
  • the TFET further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the first and second doped regions from one another.
  • the TFET further comprises a lightly doped p-type material coupled to the gate stack, the lightly doped p-type material separating the first and second doped regions from one another.
  • the doped first region is a source region, and wherein the doped second region is a drain region.
  • a TFET which comprises: a substrate; a doped first region, disposed above the substrate, having p-type organic semiconductor material; a doped second region, disposed above the substrate, having n-type transparent or semi-transparent oxide semiconductor material; and a gate stack coupled to the doped source and drain regions.
  • the p-type organic semiconductor material is selected from a group consisting of P3HT, MDMO-PPV, PEFOT:PSS, CoPc, and CuPc.
  • the n-type transparent or semi-transparent oxide semiconductor material is selected from a group consisting of a-Ga2-03, -Ga2-03, ln 2 0 3 , and SnC .
  • the TFET is a FinFET, Tri-Gate, or square nano-wire based device.
  • the TFET further comprises a lightly doped n-type material coupled to the gate stack, the lightly doped n-type material separating the doped first and second regions from one another.
  • the TFET further comprises a lightly doped p- type material coupled to the gate stack, the lightly doped p-type material separating the doped first and second regions from one another.
  • the lightly doped p-type material is undoped P3HT, or CuPc or CoPc material.
  • the doped first region is a source region, and wherein the doped second region is a drain region.
  • a TFET which comprises: a substrate; a doped first region, disposed above the substrate, having p-type organic semiconductor material; a doped second region, disposed above the substrate, having n-type organic semiconductor material; and a gate stack coupled to the doped source and drain regions.
  • the p-type organic semiconductor material is selected from a group consisting of P3HT, MDMO-PPV, and PEDOT:PSS, CuPc, and CoPc .
  • the n-type organic semiconductor material is one of F16CuPc or SnChPc.
  • the TFET is a FinFET, Tri-Gate, or square nano-wire based device.
  • the TFET further comprises a lightly doped n-type organic semiconductor material coupled to the gate stack, the lightly doped n-type material separating the doped first and second regions from one another.
  • the TFET further comprises a lightly doped p-type organic semiconductor material coupled to the gate stack, the lightly doped p-type material separating the doped first and second regions from one another.
  • the lightly doped p-type material is undoped PFHT material.
  • the doped first region is a source region, and wherein the doped second region is a drain region.
  • a system which comprises a memory; a processor coupled to the memory, the processor having TFETs according to the TFETs discussed above of various embodiments; and a wireless antenna for allowing the processor to communicate with another device.

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un appareil de formation de transistors à effet de champ à effet tunnel complémentaires (TFET) au moyen d'un matériau semi-conducteur à oxyde et/ou organique. Un type de TFET comprend : un substrat ; une première région dopée, formée sur le substrat, comportant un matériau de type p sélectionné parmi un groupe constitué des groupes III-V, IV-IV et IV d'un tableau périodique ; une seconde région dopée, formée sur le substrat, comportant un matériau semi-conducteur de type n à oxyde transparent ; et un empilement de grille couplé aux première et seconde régions dopées. Un autre type de TFET comprend : un substrat ; une première région dopée, formée sur le substrat, comportant un matériau semi-conducteur organique de type p ; une seconde région dopée, formée sur le substrat, comportant un matériau semi-conducteur à oxyde de type n ; et un empilement de grille couplé aux régions dopées de source et de drain. Selon un autre exemple, un TFET est conçu au moyen de matériaux semi-conducteurs uniquement organiques en ce qui concerne les régions actives.
PCT/US2013/077873 2013-12-26 2013-12-26 Dispositifs fet à effet tunnel complémentaires et leur procédé de formation Ceased WO2015099744A1 (fr)

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KR1020167012963A KR102162676B1 (ko) 2013-12-26 2013-12-26 상보형 터널링 fet 디바이스와 그 형성 방법
PCT/US2013/077873 WO2015099744A1 (fr) 2013-12-26 2013-12-26 Dispositifs fet à effet tunnel complémentaires et leur procédé de formation
EP13900285.1A EP3087611A4 (fr) 2013-12-26 2013-12-26 Dispositifs fet à effet tunnel complémentaires et leur procédé de formation
US15/036,058 US9786769B2 (en) 2013-12-26 2013-12-26 Complementary tunneling FET devices and method for forming the same
TW103140822A TWI549292B (zh) 2013-12-26 2014-11-25 互補式穿隧ｆｅｔ裝置及其形成方法
TW106109794A TWI620316B (zh) 2013-12-26 2014-11-25 互補式穿隧ｆｅｔ裝置及其形成方法
TW105119211A TWI587508B (zh) 2013-12-26 2014-11-25 互補式穿隧ｆｅｔ裝置及其形成方法
CN201410858223.1A CN104752496B (zh) 2013-12-26 2014-11-26 互补隧道fet器件及其制造方法
DE102014017506.5A DE102014017506B4 (de) 2013-12-26 2014-11-26 Tunnel-FET-Geräte und System
US15/673,359 US10269942B2 (en) 2013-12-26 2017-08-09 Complementary tunneling FET devices and method for forming the same

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TWI549292B (zh) 2016-09-11
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EP3087611A4 (fr) 2017-05-17
US20170365694A1 (en) 2017-12-21
CN104752496B (zh) 2018-06-26
US10269942B2 (en) 2019-04-23
DE102014017506A1 (de) 2015-07-02
KR20160101896A (ko) 2016-08-26
CN104752496A (zh) 2015-07-01
TW201703254A (zh) 2017-01-16
EP3087611A1 (fr) 2016-11-02
US9786769B2 (en) 2017-10-10
TWI587508B (zh) 2017-06-11
US20160268401A1 (en) 2016-09-15
TWI620316B (zh) 2018-04-01

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