[go: up one dir, main page]

WO2018125082A1 - Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si - Google Patents

Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si Download PDF

Info

Publication number
WO2018125082A1
WO2018125082A1 PCT/US2016/068886 US2016068886W WO2018125082A1 WO 2018125082 A1 WO2018125082 A1 WO 2018125082A1 US 2016068886 W US2016068886 W US 2016068886W WO 2018125082 A1 WO2018125082 A1 WO 2018125082A1
Authority
WO
WIPO (PCT)
Prior art keywords
regions
contact
rich
layer
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2016/068886
Other languages
English (en)
Inventor
Glenn A. Glass
Anand S. Murthy
Karthik JAMBUNATHAN
Scott J. MADDOX
Tahir Ghani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2016/068886 priority Critical patent/WO2018125082A1/fr
Publication of WO2018125082A1 publication Critical patent/WO2018125082A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6219—Fin field-effect transistors [FinFET] characterised by the source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/158—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/021—Manufacture or treatment of gated diodes, e.g. field-controlled diodes [FCD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the Si-rich cladding layer can improve S/D contact resistance by at least two times (or, in other words, the Si-rich cladding layer can lower the contact resistance at that location by at least half).
  • the Si-rich layer may be formed either before or after S/D contact trench etch processing.
  • the Si-rich layer may be formed on at least one ⁇ 111 ⁇ faceted surface of a Ge-rich S/D region after the region has been formed.
  • the thickness and C concentration may be inversely related, such that if a relatively thicker carbon-based etch stop layer is employed (e.g., with a thickness of at least 8, 10, 12, or 15 nm, such as having a thickness in the range of 8-20 nm), then relatively lower C concentration may be used to ensure the etch stop layer is adequately robust/resilient enough to effectively function (e.g., C concentration in the range of 1-5%).
  • such devices may employ semiconductor materials that are three dimensional crystals as well as two dimensional crystals or nanotubes, for example.
  • the techniques may be used to benefit devices of varying scales, such as IC devices having critical dimensions in the micrometer (micron) range and/or in the nanometer (nm) range (e.g., formed at the 22, 14, 10, 7, 5, or 3 nm process nodes, or beyond).
  • Substrate 200 may include: a bulk substrate including group IV semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure; an X on insulator (XOI) structure where X is one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material) and the insulator material is an oxide material or dielectric material or some other electrically insulating material; or some other suitable multilayer structure where the top layer includes one of the aforementioned materials (e.g., group IV and/or group III-V semiconductor material).
  • group IV semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or silicon carbide (SiC), and/or group III-V material and/or any other suitable material(s) as will be apparent in light of this disclosure
  • XOI X on
  • Methods 100A-B of Figures 1A-B continue with etching 108 fins 202 to form fin-shaped trenches 225 between the STI material 220 as shown in the resulting example structure of Figure 2D, in accordance with some embodiments.
  • etching 108 may be performed using any suitable techniques, such as one or more wet and/or dry etch processes that selectively remove the material of fins 202 relative to the STI material 220 to form fin-shaped trenches 225, and/or any other suitable processing as will be apparent in light of this disclosure.
  • a sub-fin portion 203 from fins 202 remains below fin-shaped trenches 225, where the height (dimension in the Y-axis direction) of the sub- fin portion 203 may be based on the etch processing 108 used form fin-shaped trenches 225.
  • the etch processing 108 may be performed with characteristics (e.g., a longer etch duration) that removes relatively more of fins 202, such that a shorter (by height) sub-fin portion 203 may remain or the fins 202 may be completely removed, such that the fin-shaped trenches 225 extend to the bottom of STI material 220 and possibly beyond.
  • the end structure will include the final gate stack, as will be apparent in light of this disclosure.
  • a hardmask (not shown) may be formed over the dummy gate stack (which may also be formed over spacers 250) to protect the dummy gate stack during subsequent processing, for example.
  • the transistor type (e.g., MOSFET, TFET, HEMT, or other suitable type) may be described based on the doping and/or operating scheme of the source, channel, and drain regions, and thus those respective regions may be used to determine the type or classification of a given transistor, for example.
  • MOSFET versus TFET transistors may structurally be very similar (or the same), but include different doping schemes (e.g., source-drain doping schemes for MOSFET of p-p or n-n versus p-n or n-p for TFET).
  • Method 100B of Figure IB includes similar processing as method 100A of Figure 1A, with a few variations related to the S/D regions and contact processing, as previously described. More specifically, method 100 A includes forming the Si-rich layer 264 on ⁇ 111 ⁇ faceting of S/D regions 261/262 prior to the initiation of the S/D contact loop processing (e.g., prior to performing S/D contact processing 124), while method 100B includes forming the Si-rich layer 264' on ⁇ 111 ⁇ faceting of S/D regions 261/262 after the initiation of the S/D contact loop processing (e.g., during the S/D contact processing 124, through the contact trenches).
  • Method 100B of Figure IB continues from box 116 and structure 2H by forming 117 etch stop layer 265 on the S/D regions 261/262, thereby forming the example resulting structure of Figure 3A, in accordance with some embodiments.
  • the previous relevant description with respect to forming 120 the etch stop layer is equally applicable to formation process 117, except that for process 117, the etch stop layer 265 is formed directly on the S/D regions 261/262 as the Si-rich layer has not yet been formed (as compared to formation process 120, for example). Further, the previous relevant description with respect to etch stop layer 265 is equally applicable to the structure of Figure 3A.
  • Method 100B of Figure IB continues with performing 122 final gate stack processing to form the example resulting structure of Figure 3B, in accordance with some embodiments. The previous relevant description with respect to final gate stack processing 122 is equally applicable here.
  • Example 19 includes the subject matter of Example 18, wherein the first semiconductor material is Ge that is p-type doped.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne des techniques de formation de transistors permettant de former des transistors riches en Ge utilisant une couche de réduction de résistance de contact source/drain (S/D) riche en Si. Comme il est possible de le comprendre sur la base de cette invention, la couche riche en Si peut être utilisée à une interface de contact S/D donnée pour améliorer la résistance de contact, étant donné qu'un matériau riche en Si (par exemple, du Si ou du SiGe ayant moins de 50 % de concentration en Ge par pourcentage atomique) peut être plus fortement dopé qu'un matériau riche en Ge (par exemple, du Ge ou du SiGe ayant une concentration en Ge supérieure à 50 % en pourcentage atomique). Les techniques peuvent consister à former la couche riche en Si sur le facettage {111} d'une région de S/D riche en Ge donnée, sachant qu'un tel facettage fournit une densité améliorée d'états (DOS) se chevauchant entre les matériaux. Les techniques peuvent consister à utiliser une couche d'arrêt de gravure pour préserver la couche riche en Si pendant le traitement de gravure de tranchée de contact ou pour préserver le facettage {111} de S/D afin de permettre la formation de la couche riche en Si sur ce dernier à travers la tranchée de contact.
PCT/US2016/068886 2016-12-28 2016-12-28 Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si Ceased WO2018125082A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068886 WO2018125082A1 (fr) 2016-12-28 2016-12-28 Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2016/068886 WO2018125082A1 (fr) 2016-12-28 2016-12-28 Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si

Publications (1)

Publication Number Publication Date
WO2018125082A1 true WO2018125082A1 (fr) 2018-07-05

Family

ID=62709673

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/068886 Ceased WO2018125082A1 (fr) 2016-12-28 2016-12-28 Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si

Country Status (1)

Country Link
WO (1) WO2018125082A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113206043A (zh) * 2020-01-31 2021-08-03 台湾积体电路制造股份有限公司 半导体器件及方法
EP4109553A1 (fr) * 2021-06-25 2022-12-28 INTEL Corporation Couche de recouvrement riche en silicium à faible teneur en germanium et à haute teneur en bore pour la stabilité thermique de résistance de contact pmos
US11887993B2 (en) 2019-05-13 2024-01-30 Hewlett-Packard Development Company, L.P. Thin-film transistors

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
US20160049476A1 (en) * 2012-12-17 2016-02-18 Intel Corporation Semiconductor devices with germanium-rich active layers & doped transition layers
US20160071933A1 (en) * 2014-09-10 2016-03-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Finfet transistor comprising portions of sige with a crystal orientation [111]
US20160111537A1 (en) * 2014-10-15 2016-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20160049476A1 (en) * 2012-12-17 2016-02-18 Intel Corporation Semiconductor devices with germanium-rich active layers & doped transition layers
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
US20160071933A1 (en) * 2014-09-10 2016-03-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Finfet transistor comprising portions of sige with a crystal orientation [111]
US20160111537A1 (en) * 2014-10-15 2016-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11887993B2 (en) 2019-05-13 2024-01-30 Hewlett-Packard Development Company, L.P. Thin-film transistors
CN113206043A (zh) * 2020-01-31 2021-08-03 台湾积体电路制造股份有限公司 半导体器件及方法
EP4109553A1 (fr) * 2021-06-25 2022-12-28 INTEL Corporation Couche de recouvrement riche en silicium à faible teneur en germanium et à haute teneur en bore pour la stabilité thermique de résistance de contact pmos
US12426342B2 (en) 2021-06-25 2025-09-23 Intel Corporation Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Similar Documents

Publication Publication Date Title
US11705518B2 (en) Isolation schemes for gate-all-around transistor devices
US11588052B2 (en) Sub-Fin isolation schemes for gate-all-around transistor devices
US11495672B2 (en) Increased transistor source/drain contact area using sacrificial source/drain layer
US10734412B2 (en) Backside contact resistance reduction for semiconductor devices with metallization on both sides
US11101268B2 (en) Transistors employing non-selective deposition of source/drain material
US11699756B2 (en) Source/drain diffusion barrier for germanium nMOS transistors
US11101350B2 (en) Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements
US20190348415A1 (en) Transistors employing cap layer for ge-rich source/drain regions
US11121030B2 (en) Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch
US11430868B2 (en) Buried etch-stop layer to help control transistor source/drain depth
US20190348501A1 (en) Germanium-rich channel transistors including carbon-based dopant diffusion barrier
US11757004B2 (en) Transistors including source/drain employing double-charge dopants
WO2018063248A1 (fr) Transistors en matériau du groupe iii-v utilisant une couche barrière de diffusion de dopant à base de nitrure
CN111133587A (zh) 用以降低锗nmos晶体管的掺杂剂扩散的非选择性外延源极/漏极沉积
US11404575B2 (en) Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer
KR102490902B1 (ko) 희생 ⅳ족 재료 층들을 이용하여 ⅲ-ⅴ족 재료 나노와이어들을 포함하는 트랜지스터들을 형성하기 위한 기술들
WO2019005059A1 (fr) Régulation des fuites de sous-ailette dans des dispositifs à semi-conducteur
WO2018125081A1 (fr) Transistors utilisant une couche tampon métamorphique à croissance de couverture
WO2018125082A1 (fr) Transistors riches en ge utilisant une couche de réduction de résistance de contact source/drain riche en si
US20200365711A1 (en) Doped sti to reduce source/drain diffusion for germanium nmos transistors
WO2018063333A1 (fr) Transistors à effet tunnel comprenant des régions de source/drain traitées par l'intermédiaire de tranchées de contact
WO2018182627A1 (fr) Transistors comprenant des entretoises de grille asymétriques
WO2018125035A1 (fr) Transistors comprenant un matériau de source/drain final traité après traitement de grille de remplacement
WO2018063335A1 (fr) Transistors à effet tunnel comprenant des régions de source/drain utilisant une couche d'arrêt de gravure à base de carbone

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16925817

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16925817

Country of ref document: EP

Kind code of ref document: A1