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WO2016119324A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2016119324A1
WO2016119324A1 PCT/CN2015/077903 CN2015077903W WO2016119324A1 WO 2016119324 A1 WO2016119324 A1 WO 2016119324A1 CN 2015077903 W CN2015077903 W CN 2015077903W WO 2016119324 A1 WO2016119324 A1 WO 2016119324A1
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Prior art keywords
photoresist
region
insulating layer
layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2015/077903
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English (en)
French (fr)
Inventor
王玉亮
崔大永
刘增利
李道杰
陈士娟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/897,525 priority Critical patent/US9698178B2/en
Publication of WO2016119324A1 publication Critical patent/WO2016119324A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H10P50/282—
    • H10P50/73—
    • H10W20/081—
    • H10W20/089—
    • H10W72/00—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10P76/2041—

Definitions

  • the present disclosure relates to the field of display technologies, and in particular to an array substrate, a method of fabricating the same, and a display device.
  • Oxide TFT (Oxide Thin Film Transistor) is distinguished from conventional amorphous silicon semiconductor technology by using a metal oxide such as IGZO as a semiconductor layer. Oxide TFT has become a new favorite in the display field due to its advantages of full transparency, insensitivity to light, increased aperture ratio, improved brightness, reduced power consumption, and high electron mobility.
  • an ESL (Etch Stop Layer)-etch barrier layer needs to be disposed on the metal oxide semiconductor layer.
  • a gate electrode 2 and a common electrode line 3 are first formed on a base substrate 1, followed by forming a gate insulating layer 4; and forming on the gate insulating layer 4.
  • An oxide semiconductor layer 6; an etch barrier layer 5 is formed on the base substrate 1 on which the oxide semiconductor layer 6 is formed; after that, a source electrode via 8 and a drain electrode via 9 penetrating through the etch barrier layer 5 are required to penetrate through
  • the common electrode via 10 of the barrier layer 5 and the gate insulating layer 4 is etched so that the source electrode is connected to the oxide semiconductor layer 6 through the source electrode via 8, and the drain electrode is connected to the oxide semiconductor layer 6 through the drain electrode via 9.
  • the common electrode is connected to the common electrode line 3 through the common electrode via 10.
  • the source electrode via 8, the drain via 9 and the common via 10 are formed by the same etching process.
  • the common electrode via 10 is a deep hole, the etching barrier 5 and the gate insulating layer are required to penetrate. 4, therefore, a longer etching time is required, and the source electrode via 8 and the drain electrode via 9 are shallow holes, and only the etching barrier layer 5 is required. As shown in FIG. 1, a long etching time is possible.
  • Lead to the source electrode The oxide semiconductor layer 6 at the position of the hole 8 and the drain electrode via 9 is etched, and the gate insulating layer 4 at the position of the source electrode via 8 and the drain electrode via 9 is continuously erased to cause the source or drain electrode and the gate electrode. Connected together, resulting in DGS (data line and gate line short).
  • the related art generally increases the patterning process of the gate insulating layer, that is, first patterning the gate insulating layer, forming a via hole penetrating the gate insulating layer at a position corresponding to the common electrode via 10, and then passing the same time
  • the etching process forms source electrode vias 8, drain electrode vias 9, and common electrode vias 10 through the etch barrier.
  • this increases the number of patterning processes of the array substrate and increases the production cost of the array substrate.
  • the technical problem to be solved by the present disclosure is to provide an array substrate, a manufacturing method thereof, and a display device, thereby effectively avoiding shallow holes and deep holes simultaneously etching without increasing the number of patterning processes of the array substrate, because The etching causes the oxide semiconductor layer and the gate insulating layer at the shallow hole position to be etched, causing a problem that the signal line and the gate line are short-circuited.
  • an embodiment of the present disclosure provides a method of fabricating an array substrate, comprising the steps of:
  • the method further includes:
  • the remaining photoresist overlying the insulating layer is removed.
  • the method before the step of performing the second etching, the method further includes:
  • the photoresist of the remaining portion of the photoresist is removed.
  • the insulating layer includes a gate insulating layer and an etch barrier layer, the first via hole penetrates the etch barrier layer, and the second via hole penetrates the etch barrier layer and the gate insulating layer Floor.
  • the step of performing the first etching to form the intermediate hole further comprises:
  • the step of performing the second etching to form the first via hole and forming the second via hole at the intermediate hole position further includes:
  • the thickness of the remaining gate insulating layer corresponding to the position of the intermediate hole is equal to the thickness of the etch stop layer corresponding to the remaining portion of the photoresist portion.
  • the method before the step of coating the photoresist on the insulating layer, the method further includes:
  • the etch stop layer is formed on the oxide semiconductor layer.
  • the method further includes:
  • the conductive pattern is the common electrode line
  • the semiconductor pattern is the oxide semiconductor layer
  • the source electrode and the drain electrode respectively pass through respective
  • the first via is connected to the oxide semiconductor layer
  • the common electrode is connected to the common electrode line through the second via;
  • a pixel electrode is formed on the passivation layer.
  • the exposing step is performed using a halftone mask.
  • the halftone mask comprises a semi-transmissive region corresponding to a first via formed on the array substrate and a completely transparent region corresponding to a second via formed on the array substrate, wherein the semi-transmissive region
  • the exposure amount is less than the exposure amount of the completely transparent region
  • the exposing to at least form the photoresist partial retention region and the photoresist completely removed region further includes:
  • Embodiments of the present disclosure also provide an array substrate which is fabricated by the above method.
  • Embodiments of the present disclosure also provide a display device including the above array substrate.
  • the shallow holes and shallow holes are formed by one exposure and two etchings, so that shallow holes and deep holes can be effectively avoided without increasing the number of patterning processes of the array substrate.
  • the shallow hole is over-etched due to long-time etching.
  • the oxide semiconductor layer and the gate insulating layer can be prevented from being pierced by the shallow hole position, resulting in signal lines and gates. The problem of short circuit.
  • 1 is a schematic view of a related art for performing dry etching to form via holes
  • FIG. 2 is a schematic diagram of exposing a photoresist on an etch barrier layer using a halftone mask according to an embodiment of the present disclosure
  • FIG. 3 is a schematic view of a photoresist after development according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a first etching of an etch barrier layer according to an embodiment of the present disclosure
  • FIG. 5 is a schematic view of a photoresist that ashes away a portion of a photoresist remaining region, in accordance with an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a second etching of an etch barrier layer according to an embodiment of the present disclosure
  • FIG. 7 is a schematic view of a photoresist after removing an etch barrier layer according to an embodiment of the present disclosure
  • FIG. 8 is a schematic view of a source electrode, a drain electrode, a common electrode, and a passivation layer formed on a base substrate, in accordance with an embodiment of the present disclosure.
  • the method for fabricating an array substrate and the method thereof and the display device provided by the embodiments of the present disclosure can effectively prevent shallow holes and deep holes from being simultaneously etched due to long-time etching without increasing the number of patterning processes of the array substrate.
  • the oxide semiconductor layer and the gate insulating layer at the shallow hole position are etched so that the signal line and the gate line are short-circuited.
  • This embodiment provides a method for fabricating an array substrate, including the following steps:
  • the thickness of the photoresist in the remaining portion of the photoresist is smaller than the thickness of the photoresist in the completely remaining region of the photoresist, and the thickness of the photoresist in the remaining portion of the photoresist is greater than that in the photoresist The thickness of the photoresist in the completely removed region;
  • At least partially removing the insulating layer corresponding to the completely removed region of the photoresist which may be to remove all the insulating layers, directly forming the intermediate via as the second via, and exposing the conductive pattern or semi-conducting a body pattern; or a portion of the insulating layer may be removed first to form an intermediate hole.
  • the remaining insulating layer at the intermediate hole position is further etched during the formation of the first via hole, A second via hole is formed, and a semiconductor pattern and/or a conductive pattern are respectively exposed at positions of the first via hole and the second via hole.
  • the method further comprises: removing the remaining photoresist covered on the insulating layer.
  • the method further includes: removing the photoresist of the remaining portion of the photoresist portion.
  • the photoresist in the remaining portion of the photoresist may be removed by an ashing process, and a mixed gas of oxygen and sulfur hexafluoride may be used for the ashing, wherein the ratio of oxygen to sulfur hexafluoride may be 30:1.
  • the embodiment passes the same patterning process.
  • Two etchings are performed to form deep holes (ie, second via holes) and shallow holes (ie, first via holes).
  • a portion of the deep holes may be formed during the first etching, during the second etching The remaining portions of the shallow and deep holes are formed.
  • the method for forming an array substrate in the embodiment is suitable for manufacturing an oxide thin film transistor array substrate, so that in the manufacturing process of the oxide thin film transistor array substrate, the oxide semiconductor layer and the gate insulating layer corresponding to the shallow hole position can be prevented from being The problem of short-circuiting the signal line and the gate line.
  • the insulating layer includes a gate insulating layer and an etch barrier layer, the first via hole penetrating through the etch barrier layer for connecting the source electrode and the oxide semiconductor layer, the drain electrode and the oxide semiconductor layer, The second via penetrates through the etch barrier layer and the gate insulating layer for connecting the common electrode and the common electrode line.
  • the first via is formed by etching, the oxide semiconductor layer is exposed, and the second via is etched to expose the Common electrode line.
  • the step of performing the first etching to form the intermediate hole further comprises:
  • the step of performing the second etching to form the first via hole and forming the second via hole at the intermediate hole position comprises:
  • the thickness of the remaining gate insulating layer corresponding to the position of the intermediate hole is equal to the thickness of the etch stop layer corresponding to the remaining portion of the photoresist portion.
  • the gate insulating layer and the etch stop layer can be made of the same material, and the thickness of the remaining gate insulating layer is equal to the thickness of the etch stop layer, so that the second etch can be performed to ensure that the remaining gate is etched away.
  • the simultaneous etch stop layer of the insulating layer can also be completely etched away without incomplete etching or over-etching.
  • the method further includes:
  • the etch stop layer is formed on the oxide semiconductor layer.
  • the method further includes:
  • a source electrode, a drain electrode, and a common electrode on the base substrate, wherein the conductive pattern is the common electrode line, the semiconductor pattern is the oxide semiconductor layer, and the source electrode and the drain electrode respectively pass Each of the corresponding first vias is connected to the oxide semiconductor layer, and the common electrode is connected to the common electrode line through the second via;
  • a pixel electrode is formed on the passivation layer.
  • the exposing step is performed using a halftone mask.
  • the halftone mask includes a semi-transmissive region corresponding to a first via formed on the array substrate and a completely transparent region corresponding to a second via formed on the array substrate, wherein the semi-transmissive region has an exposure amount less than a complete The amount of exposure of the light-transmitting area.
  • the steps in addition to the area further include:
  • an array substrate is used as an oxide thin film transistor array substrate as an example, and a method for fabricating the array substrate of the present embodiment will be described in detail with reference to the accompanying drawings. It is apparent that the described embodiments are only a part of the embodiments of the present disclosure, and not all of them. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure without departing from the inventive scope are the scope of the disclosure.
  • Step E As shown in FIG. 2, a photoresist 7 is coated on the base substrate 1 on which the gate insulating layer 4 and the etch barrier layer 5 are formed, and the photoresist is exposed by the mask 11 to form a mask.
  • 11 includes a semi-transmissive region corresponding to the source electrode via and the drain electrode via on the array substrate and a completely transparent region corresponding to the common electrode via on the array substrate, wherein the source via and the drain via
  • the common electrode via is formed by the same patterning process, and the depth of the source electrode via/the drain via is less than the depth of the common via;
  • the mask 11 is a halftone mask comprising a semi-transmissive region corresponding to the first via formed on the array substrate and a completely transparent region corresponding to the second via formed on the array substrate, wherein The exposure amount of the semi-transmissive region is smaller than the exposure amount of the completely transparent region.
  • Step F as shown in FIG. 3, after the development, a photoresist portion reserved region corresponding to the source electrode via and the drain electrode via, and a photoresist unreserved region corresponding to the common electrode via are formed. That is, the photoresist completely removes the region) and the photoresist retention region corresponding to other regions;
  • Step G As shown in FIG. 4, a first etching is performed to remove all of the etch barrier layer 5 and a portion of the gate insulating layer 4 corresponding to the position of the photoresist unretained region of the common electrode via to form an intermediate hole.
  • the first etching performed in this step is dry etching, further, in this step, all the etch barrier layers and all the gate insulating layers 4 may be removed, and the common electrode lines 3 are exposed;
  • Step H as shown in FIG. 5, ashing off the photoresist corresponding to the remaining portion of the photoresist of the source electrode via and the drain electrode via;
  • the ashing may use a mixed gas of oxygen and sulfur hexafluoride, wherein the ratio of oxygen to sulfur hexafluoride may be 30:1.
  • Step I as shown in FIG. 6, performing a second etching to remove all etch barriers corresponding to the remaining portions of the ashed photoresist portion corresponding to the source electrode via and the drain electrode via a layer 5, and a remaining gate insulating layer 4 corresponding to a region of the common electrode via (ie, an intermediate hole position) to expose the oxide semiconductor layer 6 at a position of the source electrode via and the drain electrode via
  • the common electrode line 3 is exposed at the position of the common electrode via, thereby forming the source electrode via 8, the drain electrode via 9, and the common electrode via 10.
  • the second etching performed in this step may be dry etching.
  • the second etch in this step does not have to remove the remaining gate insulating of the region corresponding to the common electrode via.
  • the intermediate hole formed by the layer is the common electrode via 10. Since this step is a dry etching, it does not affect the common electrode line 3 composed of the gate metal layer.
  • the gate insulating layer and the etch barrier layer may be made of the same material, for example, the thickness of the remaining gate insulating layer corresponding to the position of the intermediate hole and the thickness of the etch stop layer corresponding to the remaining portion of the photoresist portion. Equally, when the second etching is performed, it can be ensured that the etching barrier layer can be completely etched away while etching the remaining gate insulating layer, and the etching is not completed or the etching is not performed.
  • Step J As shown in FIG. 7, the remaining photoresist is removed.
  • step E the method further includes:
  • Step A providing a base substrate 1 on which a pattern of the gate electrode 2 and the common electrode line 3 is formed;
  • the base substrate 1 may be a glass substrate or a quartz substrate. Specifically, the thickness of the substrate substrate 1 can be deposited by sputtering or thermal evaporation.
  • the gate metal layer, the gate metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals, and the gate metal layer may be a single layer structure or multiple layers. Structure, multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, etc.
  • a photoresist is coated on the gate metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to The region where the pattern of the gate electrode 2 and the common electrode line 3 is located, the region where the photoresist is not reserved corresponds to the region other than the above-mentioned pattern; the development process, the photoresist in the unretained region of the photoresist is completely removed, and the photoresist retention region is completely removed.
  • the thickness of the photoresist remains unchanged; the gate metal film of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the gate electrode 2 and the common electrode line 3.
  • Step B forming a gate insulating layer 4 on the substrate 1 on which the step A is completed;
  • a plasma enhanced chemical vapor deposition (PECVD) method can be used to deposit a thickness on the substrate on which step a is completed.
  • the gate insulating layer 4, the gate insulating layer 4 may be an oxide, a nitride or an oxynitride compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • Step C forming a pattern of the oxide semiconductor layer 6 on the base substrate 1 on which the step B is completed;
  • the oxide semiconductor layer 6 is deposited on the base substrate 1 subjected to the step B, and the oxide semiconductor layer may be IGZO, ITZO or ZnON, and the thickness of the oxide semiconductor layer is A photoresist is coated on the oxide semiconductor layer 6, and the photoresist is exposed by a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region Corresponding to the region where the pattern of the oxide semiconductor layer 6 is located, the photoresist unretained region corresponds to a region other than the above-mentioned pattern; for development processing, the photoresist in the unretained region of the photoresist is completely removed, and the photoresist remaining region is The thickness of the photoresist remains unchanged; the gate metal film of the unretained region of the photoresist is completely etched away by an etching process, and the remaining photoresist is stripped to form a pattern of the oxide semiconductor layer 6.
  • Step D forming an etch stop layer 5 on the base substrate 1 on which the step C is completed.
  • a plasma enhanced chemical vapor deposition (PECVD) method can be used to deposit a thickness on the substrate on which step c is completed.
  • the etch barrier layer 5, the etch barrier layer 5 may be an oxide, a nitride or an oxynitride compound, and the corresponding reaction gas is SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • step J the method further includes:
  • Step K forming a source electrode 12, a drain electrode 13 and a common electrode 14 on the substrate 1 on which the step J is completed;
  • a thickness of about a thickness can be deposited by magnetron sputtering, thermal evaporation, or other film formation methods.
  • the source/drain metal layer, the source/drain metal layer may be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and an alloy of these metals.
  • the source/drain metal layer may be a single layer structure or a multilayer structure such as Cu ⁇ Mo, Ti ⁇ Cu ⁇ Ti, Mo ⁇ Al ⁇ Mo, or the like.
  • a layer of photoresist is coated on the source/drain metal layer, and the photoresist is exposed by using a mask to form a photoresist unretained region and a photoresist retention region, wherein the photoresist retention region corresponds to In the region where the pattern of the source electrode 12, the drain electrode 13 and the common electrode 14 is located, the photoresist unretained region corresponds to a region other than the above-mentioned pattern; for development processing, the photoresist in the unretained region of the photoresist is completely removed, and the light is completely removed.
  • the thickness of the photoresist in the glue-retained region remains unchanged; the source-drain metal layer of the unretained region of the photoresist is completely etched away by the etching process, and the remaining photoresist is stripped to form the source electrode 12, the drain electrode 13 and the common
  • the source electrode 12 is connected to the oxide semiconductor layer 6 through the source electrode via 8
  • the drain electrode 13 is connected to the oxide semiconductor layer 6 through the drain electrode via 9
  • the common electrode 14 passes through the common electrode via 10 and the common electrode line. 3 connections.
  • Step L as shown in FIG. 8, forming a passivation layer 15 including a passivation layer via hole on the base substrate 1 on which step K is completed;
  • the thickness of the substrate substrate 1 on which the step K is completed may be deposited by magnetron sputtering, thermal evaporation, PECVD, or other film formation methods.
  • the passivation layer 15, the passivation layer 15 may be selected from an oxide, a nitride or an oxynitride.
  • the passivation layer material may be SiNx, SiOx or Si(ON)x, and the passivation layer 15 may also use Al 2 . O 3 .
  • the passivation layer may be a single layer structure or a two layer structure composed of silicon nitride and silicon oxide.
  • the reaction gas corresponding to the oxide of silicon may be SiH 4 or N 2 O; the corresponding gas of the nitride or the oxynitride may be SiH 4 , NH 3 , N 2 or SiH 2 Cl 2 , NH 3 , N 2 .
  • a pattern of the passivation layer 15 including the passivation layer via holes is formed by one patterning process, and specifically, the passivation layer 15 may be coated with a thickness of about
  • the organic resin, the organic resin may be benzocyclobutene (BCB), or other organic photosensitive material, and after exposure and development, a passivation layer 15 having a passivation layer via hole is formed by an etching process.
  • Step M A pattern of pixel electrodes is formed on the base substrate 1 on which the step L is completed.
  • the thickness is deposited by sputtering or thermal evaporation on the substrate 1 on which the step L is completed.
  • Transparent conductive layer the transparent conductive layer may be ITO, IZO or other transparent metal oxide, a layer of photoresist is coated on the transparent conductive layer, and the photoresist is exposed by a mask to form a photoresist.
  • the photoresist-unretained region corresponds to a region where the pattern of the pixel electrode is located, and the photoresist-unretained region corresponds to a region other than the above-mentioned pattern; development processing, photoresist
  • the photoresist in the unreserved area is completely removed, and the thickness of the photoresist in the photoresist remaining area remains unchanged; the transparent conductive layer film in the unretained area of the photoresist is completely etched by the etching process, and the remaining lithography is peeled off.
  • the glue forms a pattern of the pixel electrode, and the pixel electrode is connected to the drain electrode through the passivation layer via.
  • deep holes ie, common electrode vias
  • shallow holes ie, source electrode vias and drain electrode vias
  • the oxide semiconductor layer and the gate insulating layer at the hole position are etched through the problem of causing the signal line and the gate line to be short-circuited.
  • This embodiment provides an array substrate which is fabricated by using the above-described method for fabricating an array substrate.
  • the display device may be any product or component having a display function such as a liquid crystal panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, a navigator, an electronic paper, or the like.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本公开提供了一种阵列基板及其制作方法、显示装置。本公开在覆盖有导电图形和/或半导体图形的绝缘层上涂布光刻胶；进行曝光，以至少形成光刻胶部分保留区域、光刻胶完全去除区域；进行第一刻蚀，以至少部分地去除所述光刻胶完全去除区域对应的所述绝缘层，从而形成中间孔；进行第二刻蚀，以形成所述第一过孔，并在所述中间孔位置形成所述第二过孔，从而在所述第一过孔和所述第二过孔的位置分别暴露出所述半导体图形和/所述导电图形，其中所述第一过孔的深度小于所述第二过孔的深度。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2015年01月26日在中国提交的中国专利申请号No.201510038372.8的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板及其制作方法、显示装置。
背景技术
Oxide TFT(氧化物薄膜晶体管)区别于传统的非晶硅半导体技术，使用金属氧化物(如IGZO)做为半导体层。Oxide TFT具有全透明、对光不敏感、增加开口率、提高亮度、降低功耗、电子迁移率高等优点，已经成为显示领域的新宠。
但金属氧化物半导体层对环境要求比较高，空气中的氧和水都会影响其特性，因此需要在金属氧化物半导体层上设置ESL(Etch Stop Layer)-刻蚀阻挡层。如图1所示，相关技术中，制作氧化物薄膜晶体管阵列基板时，首先在衬底基板1上形成栅电极2和公共电极线3；之后形成栅绝缘层4；在栅绝缘层4上形成氧化物半导体层6；在形成有氧化物半导体层6的衬底基板1上形成刻蚀阻挡层5；之后需要形成贯穿刻蚀阻挡层5的源电极过孔8和漏电极过孔9，贯穿刻蚀阻挡层5和栅绝缘层4的公共电极过孔10，以便源电极通过源电极过孔8与氧化物半导体层6连接，漏电极通过漏电极过孔9与氧化物半导体层6连接，公共电极通过公共电极过孔10与公共电极线3连接。相关技术中源电极过孔8、漏电极过孔9和公共电极过孔10为采用同一次刻蚀工艺形成，由于公共电极过孔10为深孔，需要贯穿刻蚀阻挡层5和栅绝缘层4，因此需要较长的刻蚀时间，而源电极过孔8、漏电极过孔9为浅孔，仅需要贯穿刻蚀阻挡层5，如图1所示，较长的刻蚀时间有可能导致源电极过 孔8和漏电极过孔9位置的氧化物半导体层6被刻穿，进而继续将源电极过孔8和漏电极过孔9位置的栅绝缘层4刻掉导致源电极或漏电极与栅电极连接在一起，导致DGS(data line and gate line short，数据线和栅线短路)。
为了解决上述问题，相关技术一般是增加一次栅绝缘层的构图工艺，即先对栅绝缘层进行构图，在对应公共电极过孔10的位置形成贯穿栅绝缘层的过孔，之后再通过同一次刻蚀工艺形成贯穿刻蚀阻挡层的源电极过孔8、漏电极过孔9和公共电极过孔10。但这样就增加了阵列基板的构图工艺次数，提高了阵列基板的生产成本。
发明内容
本公开要解决的技术问题是提供一种阵列基板及其制作方法、显示装置，从而在不增加阵列基板构图工艺次数的前提下，有效避免浅孔和深孔同时进行刻蚀时，因为长时间刻蚀而导致浅孔位置的氧化物半导体层和栅绝缘层被刻穿，使得信号线和栅线短路的问题。
一方面，本公开的实施例提供了一种制作阵列基板的方法，包括以下步骤：
在覆盖有导电图形和/或半导体图形的绝缘层上涂布光刻胶；
进行曝光，以至少形成光刻胶部分保留区域、光刻胶完全去除区域，其中所述光刻胶部分保留区域对应于形成第一过孔的区域，所述光刻胶完全去除区域对应于形成第二过孔的区域；
进行第一刻蚀，以至少部分地去除所述光刻胶完全去除区域对应的所述绝缘层，从而形成中间孔；以及
进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔，从而在所述第一过孔和所述第二过孔的位置分别暴露出所述半导体图形和/或所述导电图形，其中所述第一过孔的深度小于所述第二过孔的深度。
可选地，在进行第二刻蚀以形成所述第一过孔和所述第二过孔的步骤之后，所述方法还包括：
去除所述绝缘层上覆盖的剩余的光刻胶。
可选地，进行第二刻蚀的步骤之前还包括：
去除所述光刻胶部分保留区域的光刻胶。
可选地，所述绝缘层包括栅绝缘层和刻蚀阻挡层，所述第一过孔贯穿所述刻蚀阻挡层，所述第二过孔贯穿所述刻蚀阻挡层和所述栅绝缘层。
可选地，进行第一刻蚀以形成所述中间孔的步骤进一步包括：
去除所述光刻胶完全去除区域对应的全部所述刻蚀阻挡层和部分所述栅绝缘层以形成所述中间孔，
进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔的步骤进一步包括：
去除所述光刻胶部分保留区域所对应的全部的所述刻蚀阻挡层以形成所述第一过孔，和去除所述中间孔位置对应的剩余的所述栅绝缘层以形成所述第二过孔。
可选地，对应于中间孔位置的所述剩余的栅绝缘层的厚度与对应于所述光刻胶部分保留区域的所述刻蚀阻挡层的厚度相等。
可选地，在绝缘层上涂布光刻胶的步骤之前还包括：
提供衬底基板；
在所述衬底基板上形成栅电极和公共电极线；
在形成有所述栅电极和公共电极线的衬底基板上形成所述栅绝缘层；
在所述栅绝缘层上形成氧化物半导体层；以及
在所述氧化物半导体层上形成所述刻蚀阻挡层。
可选地，所去除所述绝缘层上覆盖的剩余的光刻胶的步骤之后还包括：
在所述衬底基板上形成源电极、漏电极和公共电极，所述导电图形为所述公共电极线，所述半导体图形为所述氧化物半导体层，所述源电极和漏电极分别通过各自对应的所述第一过孔与所述氧化物半导体层连接，所述公共电极通过所述第二过孔与所述公共电极线连接；
形成钝化层；以及
在所述钝化层上形成像素电极。
可选地，所述曝光步骤是采用半色调掩膜板进行的。
可选地，所述半色调掩膜板包括对应于形成阵列基板上第一过孔的半透光区域和对应于形成阵列基板上第二过孔的完全透光区域，其中半透光区域 的曝光量小于完全透光区域的曝光量，进行曝光以至少形成光刻胶部分保留区域、光刻胶完全去除区域的步骤进一步包括：
利用所述半色调掩膜板对绝缘层上涂布的光刻胶进行曝光，对应于所述完全透光区域形成所述光刻胶完全去除区域，对应于所述半透光区域形成所述光刻胶部分保留区域。
本公开实施例还提供了一种阵列基板，为采用上述方法制作得到。
本公开实施例还提供了一种显示装置，包括上述的阵列基板。
本公开具有以下有益的技术效果：
上述方案中，在同一次构图工艺中，通过一次曝光，两次刻蚀来形成深孔和浅孔，从而能够在不增加阵列基板构图工艺次数的前提下，有效避免浅孔和深孔同时进行刻蚀时因为长时间刻蚀而导致浅孔位置过刻的情况，对于氧化物薄膜晶体管阵列基板来说，能够避免浅孔位置的氧化物半导体层和栅绝缘层被刻穿导致信号线和栅线短路的问题。
附图说明
图1为相关技术进行干法刻蚀形成过孔的示意图；
图2为根据本公开一个实施例的利用半色调掩膜板对刻蚀阻挡层上的光刻胶进行曝光的示意图；
图3为根据本公开一个实施例的对光刻胶进行显影后的示意图；
图4为根据本公开一个实施例的对刻蚀阻挡层进行第一刻蚀后的示意图；
图5为根据本公开一个实施例的灰化掉光刻胶部分保留区域的光刻胶的示意图；
图6为根据本公开一个实施例的对刻蚀阻挡层进行第二刻蚀后的示意图；
图7为根据本公开一个实施例的去除刻蚀阻挡层上的光刻胶后的示意图；以及
图8为根据本公开一个实施例的在衬底基板上形成源电极、漏电极、公共电极和钝化层后的示意图。
具体实施方式
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的″第一″、″第二″以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，″一个″或者″一″等类似词语也不表示数量限制，而是表示存在至少一个。″连接″或者″相连″等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。″上″、″下″、″左″、″右″、″内″、″外″等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
本公开实施例提供的一种制作阵列基板及其方法、显示装置，能够在不增加阵列基板构图工艺次数的前提下，有效避免浅孔和深孔同时进行刻蚀时因为长时间刻蚀而导致浅孔位置的氧化物半导体层和栅绝缘层被刻穿使得信号线和栅线短路的情况。
实施例一
本实施例提供了一种制作阵列基板的方法，包括以下步骤：
在覆盖有导电图形和/或半导体图形的绝缘层上涂布光刻胶；
进行曝光，以至少形成光刻胶部分保留区域、光刻胶完全去除区域，其中光刻胶部分保留区域对应于形成第一过孔的区域，光刻胶完全去除区域对应于形成第二过孔的区域，具体地来说，光刻胶部分保留区域的光刻胶的厚度小于光刻胶完全保留区域的光刻胶的厚度，光刻胶部分保留区域的光刻胶的厚度大于光刻胶完全去除区域的光刻胶的厚度；
进行第一刻蚀，以至少部分地去除光刻胶完全去除区域对应的绝缘层，从而形成中间孔；
进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔，从而在所述第一过孔和所述第二过孔的位置分别暴露出所述半导体图形和/或所述导电图形，其中所述第一过孔的深度小于所述第二过孔的深度。
至少部分地去除光刻胶完全去除区域对应的绝缘层，可以是去除全部的绝缘层，直接使得所形成的中间孔就是第二过孔，并暴露出导电图形或半导 体图形；也可以是先去除部分绝缘层，以形成中间孔，在进行第二刻蚀时，在形成第一过孔的过程中，也会对中间孔位置的剩余绝缘层继续刻蚀，以形成第二过孔，并在所述第一过孔和所述第二过孔的位置分别暴露出半导体图形和/或导电图形。通过这样的蚀刻过程，能够有效避免出现同时刻蚀深度不同的两个孔时，浅孔被过刻的问题。
进一步的，在进行第二刻蚀以形成所述第一过孔和所述第二过孔的步骤之后，所述方法还包括：去除所述绝缘层上覆盖的剩余的光刻胶。
进一步地，在进行第二刻蚀的步骤之前还包括：去除所述光刻胶部分保留区域的光刻胶。
具体地，可以采用灰化工艺去除光刻胶部分保留区域的光刻胶，灰化可以使用氧气加六氟化硫的混合气体，其中氧气和六氟化硫的比例可以是30∶1。
如果通过同一次刻蚀来同时形成深孔和浅孔，由于深孔较深，刻蚀时间长，势必会导致在浅孔位置出现过刻的情况，而本实施例通过同一次构图工艺中的两次刻蚀来形成深孔(即第二过孔)和浅孔(即第一过孔)，特别地，可以在第一次刻蚀时形成深孔的一部分，在第二次刻蚀时形成浅孔和深孔的剩余部分。通过本公开所提供的制造方法，能够在不增加阵列基板构图工艺次数的前提下，有效避免浅孔和深孔同时进行刻蚀时因为长时间刻蚀而导致浅孔位置过刻的情况。本实施例中的阵列基板形成方法，适用于制造氧化物薄膜晶体管阵列基板，这样在氧化物薄膜晶体管阵列基板的制造过程中，能够避免对应于浅孔位置的氧化物半导体层和栅绝缘层被刻穿而导致信号线和栅线短路的问题。
进一步地，所述绝缘层包括栅绝缘层和刻蚀阻挡层，所述第一过孔贯穿刻蚀阻挡层，用于连接源电极和氧化物半导体层、漏电极和氧化物半导体层，所述第二过孔贯穿刻蚀阻挡层和栅绝缘层，用于连接公共电极和公共电极线。一个具体的实施例中，在制造氧化物薄膜晶体管阵列基板的过程中，蚀刻形成第一过孔，裸露出的是所述氧化物半导体层，蚀刻形成第二过孔，裸露出的是所述公共电极线。
进一步地，进行第一刻蚀以形成所述中间孔的步骤进一步包括：
去除所述光刻胶完全去除区域对应的全部所述刻蚀阻挡层和部分所述栅 绝缘层以形成所述中间孔，
进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔的步骤包括：
去除所述光刻胶部分保留区域所对应的全部的所述刻蚀阻挡层以形成所述第一过孔，和去除所述中间孔位置对应的剩余的所述栅绝缘层以形成所述第二过孔。
可选地，对应于中间孔位置的所述剩余栅绝缘层的厚度与对应于所述光刻胶部分保留区域的所述刻蚀阻挡层的厚度相等。一般来说，栅绝缘层与刻蚀阻挡层可以采用相同的材料，剩余栅绝缘层的厚度与刻蚀阻挡层的厚度相等，这样在进行第二刻蚀时，可以保证在刻蚀掉剩余栅绝缘层的同时刻蚀阻挡层也刚好能够被完全刻蚀掉，不会出现刻蚀不完全或者过刻的情况。
进一步地，在绝缘层上涂布光刻胶的步骤之前还包括：
提供衬底基板；
在所述衬底基板上形成栅电极和公共电极线；
在形成有所述栅电极和公共电极线的衬底基板上形成所述栅绝缘层；
在所述栅绝缘层上形成氧化物半导体层；以及
在所述氧化物半导体层上形成所述刻蚀阻挡层。
进一步地，在去除所述绝缘层上覆盖的剩余的光刻胶的步骤之后还包括：
在所述衬底基板上形成源电极、漏电极和公共电极，其中所述导电图形为所述公共电极线，所述半导体图形为所述氧化物半导体层，所述源电极和漏电极分别通过各自对应的所述第一过孔与所述氧化物半导体层连接，所述公共电极通过所述第二过孔与所述公共电极线连接；
形成钝化层；以及
在所述钝化层上形成像素电极。
具体地，所述曝光步骤是采用半色调掩膜板进行的。所述半色调掩膜板包括对应于形成阵列基板上第一过孔的半透光区域和对应于形成阵列基板上第二过孔的完全透光区域，其中半透光区域的曝光量小于完全透光区域的曝光量。
进一步地，进行曝光，以至少形成光刻胶部分保留区域、光刻胶完全去 除区域的步骤进一步包括：
利用所述半色调掩膜板对绝缘层上涂布的光刻胶进行曝光，对应于所述完全透光区域形成所述光刻胶完全去除区域，对应于所述半透光区域形成所述光刻胶部分保留区域。
实施例二
下面以阵列基板为氧化物薄膜晶体管阵列基板为例，结合附图对本实施例的阵列基板的制作方法进行详细介绍。显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本实施例的制造方法包括以下步骤：
步骤E：如图2所示，在形成有栅绝缘层4和刻蚀阻挡层5的衬底基板1上涂布光刻胶7，利用掩膜板11对光刻胶进行曝光，掩膜板11包括对应阵列基板上源电极过孔和漏电极过孔的半透光区域和对应阵列基板上公共电极过孔的完全透光区域，其中所述源电极过孔、所述漏电极过孔与所述公共电极过孔是采用同一次构图工艺形成的，并且所述源电极过孔/所述漏电极过孔的深度小于公共电极过孔的深度；
掩膜板11为半色调掩膜板，半色调掩膜板包括对应于形成阵列基板上第一过孔的半透光区域和对应于形成阵列基板上第二过孔的完全透光区域，其中，半透光区域的曝光量小于完全透光区域的曝光量。
步骤F：如图3所示，显影后形成对应所述源电极过孔、所述漏电极过孔的光刻胶部分保留区域、对应所述公共电极过孔的光刻胶未保留区域(亦即光刻胶完全去除区域)和对应其他区域的光刻胶保留区域；
步骤G：如图4所示，进行第一刻蚀，去除对应于公共电极过孔的光刻胶未保留区域位置的全部刻蚀阻挡层5和部分的栅绝缘层4形成中间孔。本步骤中进行的第一刻蚀为干法刻蚀，进一步地，本步骤中，也可以去除全部的刻蚀阻挡层和全部的栅绝缘层4，裸露出公共电极线3；
步骤H：如图5所示，灰化掉对应于所述源电极过孔和所述漏电极过孔位置的光刻胶部分保留区域的光刻胶；
具体地，灰化可以使用氧气加六氟化硫的混合气体，其中氧气和六氟化硫的比例可以为30∶1。
步骤I：如图6所示，进行第二刻蚀，去除对应于所述源电极过孔和所述漏电极过孔的，灰化后的光刻胶部分保留区域所对应的全部刻蚀阻挡层5，和对应于公共电极过孔的区域(亦即中间孔位置)的剩余栅绝缘层4，以在所述源电极过孔和所述漏电极过孔的位置暴露出氧化物半导体层6并在公共电极过孔的位置的暴露出公共电极线3，从而形成源电极过孔8、漏电极过孔9和公共电极过孔10。其中，本步骤中进行的第二刻蚀可以是干法刻蚀。如果步骤G中的第一刻蚀已经去除对应于公共电极过孔的区域的全部栅绝缘层，那么本步骤中的第二刻蚀不必再去除对应于公共电极过孔的区域的剩余的栅绝缘层，所形成的中间孔就是公共电极过孔10。由于本步骤采取的是干法刻蚀，因此并不会对由栅金属层构成的公共电极线3造成影响。
其中，栅绝缘层与刻蚀阻挡层可以采用相同的材料，例如，对应于所述中间孔位置的剩余栅绝缘层的厚度与对应于所述光刻胶部分保留区域的刻蚀阻挡层的厚度相等，这样在进行第二刻蚀时，可以保证在刻蚀掉剩余栅绝缘层的同时刻蚀阻挡层也刚好能够被完全刻蚀掉，不会出现刻蚀不完全或者过刻的情况。
步骤J：如图7所示，去除剩余的光刻胶。
进一步地，步骤E之前还包括：
步骤A：提供衬底基板1，在衬底基板1上形成栅电极2和公共电极线3的图形；
其中，衬底基板1可为玻璃基板或石英基板。具体地，可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为
Figure PCTCN2015077903-appb-000001
的栅金属层，栅金属层可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中光刻胶保留区域对应于栅电极2和公共电极线3的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区 域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成栅电极2和公共电极线3的图形。
步骤B：在完成步骤A的衬底基板1上形成栅绝缘层4；
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤a的基板上沉积厚度为
Figure PCTCN2015077903-appb-000002
的栅绝缘层4，栅绝缘层4可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤C：在完成步骤B的衬底基板1上形成氧化物半导体层6的图形；
具体地，在经过步骤B的衬底基板1上沉积氧化物半导体层6，氧化物半导体层可以采用IGZO、ITZO或ZnON，氧化物半导体层的厚度为
Figure PCTCN2015077903-appb-000003
Figure PCTCN2015077903-appb-000004
在氧化物半导体层6上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中光刻胶保留区域对应于氧化物半导体层6的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成氧化物半导体层6的图形。
步骤D、在完成步骤C的衬底基板1上形成刻蚀阻挡层5。
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤c的基板上沉积厚度为
Figure PCTCN2015077903-appb-000005
的刻蚀阻挡层5，刻蚀阻挡层5可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
进一步地，步骤J之后还包括：
步骤K：在完成步骤J的衬底基板1上形成源电极12、漏电极13和公共电极14；
具体地，可以采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为
Figure PCTCN2015077903-appb-000006
的源漏金属层，源漏金属层可以是Cu、Al、Ag、Mo、Cr、Nd、Ni、Mn、Ti、Ta、W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo、Ti\Cu\Ti、Mo\Al\Mo等。在源 漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中光刻胶保留区域对应于源电极12、漏电极13和公共电极14的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成源电极12、漏电极13和公共电极14，源电极12通过源电极过孔8与氧化物半导体层6连接，漏电极13通过漏电极过孔9与氧化物半导体层6连接，公共电极14通过公共电极过孔10与公共电极线3连接。
步骤L：如图8所示，在完成步骤K的衬底基板1上形成包括有钝化层过孔的钝化层15；
具体地，可以在完成步骤K的衬底基板1上采用磁控溅射、热蒸发、PECVD或其它成膜方法沉积厚度为
Figure PCTCN2015077903-appb-000007
的钝化层15，钝化层15可以选用氧化物、氮化物或者氧氮化合物，具体地，钝化层材料可以是SiNx、SiOx或Si(ON)x，钝化层15还可以使用Al2O3。钝化层可以是单层结构，也可以是采用氮化硅和氧化硅构成的两层结构。其中，硅的氧化物对应的反应气体可以为SiH4、N2O；氮化物或者氧氮化合物对应气体可以是SiH4、NH3、N2或SiH2Cl2、NH3、N2。通过一次构图工艺形成包括有钝化层过孔的钝化层15的图形，具体地，可以在钝化层15上涂覆一层厚度约为
Figure PCTCN2015077903-appb-000008
的有机树脂，有机树脂可以是苯并环丁烯(BCB)，也可以是其他的有机感光材料，曝光显影后，通过一次刻蚀工艺形成有钝化层过孔的钝化层15的图形。
步骤M：在完成步骤L的衬底基板1上形成像素电极的图形。
具体地，在完成步骤L的衬底基板1上通过溅射或热蒸发的方法沉积厚度约为
Figure PCTCN2015077903-appb-000009
的透明导电层，透明导电层可以是ITO、IZO或者其他的透明金属氧化物，在透明导电层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于像素电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未 保留区域的透明导电层薄膜，剥离剩余的光刻胶，形成像素电极的图形，像素电极通过钝化层过孔与漏电极连接。
本实施例通过同一次构图工艺中的两次刻蚀来形成深孔(即公共电极过孔)和浅孔(即源电极过孔和漏电极过孔)，从而能够在不增加阵列基板构图工艺次数的前提下，有效避免浅孔和深孔同时进行刻蚀时因为长时间刻蚀而导致对应于浅孔位置的过刻的情况，对于氧化物薄膜晶体管阵列基板来说，能够避免对应于浅孔位置的氧化物半导体层和栅绝缘层被刻穿导致信号线和栅线短路的问题。
实施例三
本实施例提供了一种阵列基板，为采用上述的阵列基板的制作方法制作得到。
实施例四
本实施例提供了一种显示装置，包括上述的阵列基板。所述显示装置可以为：液晶面板、液晶电视、液晶显示器、数码相框、手机、平板电脑、导航仪、电子纸等任何具有显示功能的产品或部件。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视本公开的保护范围。

Claims (12)

  1. 一种制作阵列基板的方法，包括以下步骤：
    在覆盖有导电图形和/或半导体图形的绝缘层上涂布光刻胶；
    进行曝光，以至少形成光刻胶部分保留区域、光刻胶完全去除区域，其中所述光刻胶部分保留区域对应于形成第一过孔的区域，所述光刻胶完全去除区域对应于形成第二过孔的区域；
    进行第一刻蚀，以至少部分地去除所述光刻胶完全去除区域对应的所述绝缘层，从而形成中间孔；以及
    进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔，从而在所述第一过孔和所述第二过孔的位置分别暴露出所述半导体图形和/或所述导电图形，其中所述第一过孔的深度小于所述第二过孔的深度。
  2. 根据权利要求1所述的方法，其中在进行第二刻蚀以形成所述第一过孔和所述第二过孔的步骤之后，所述方法还包括：
    去除所述绝缘层上覆盖的剩余的光刻胶。
  3. 根据权利要求1或2所述的方法，其中在进行第二刻蚀的步骤之前还包括：
    去除所述光刻胶部分保留区域的光刻胶。
  4. 根据权利要求1至3任一项所述的方法，其中所述绝缘层包括栅绝缘层和刻蚀阻挡层，所述第一过孔贯穿所述刻蚀阻挡层，所述第二过孔贯穿所述刻蚀阻挡层和所述栅绝缘层。
  5. 根据权利要求4所述的方法，其中进行第一刻蚀以形成所述中间孔的步骤进一步包括：
    去除所述光刻胶完全去除区域对应的全部所述刻蚀阻挡层和部分所述栅绝缘层以形成所述中间孔，
    进行第二刻蚀，以形成所述第一过孔并在所述中间孔位置形成所述第二过孔的步骤进一步包括：
    去除所述光刻胶部分保留区域所对应的全部的所述刻蚀阻挡层以形成所述第一过孔，以及去除所述中间孔位置对应的剩余的所述栅绝缘层以形成所 述第二过孔。
  6. 根据权利要求5所述的方法，其中对应于所述中间孔位置的所述剩余的栅绝缘层的厚度与对应于所述光刻胶部分保留区域的所述刻蚀阻挡层的厚度相等。
  7. 根据权利要求4-6任一项所述的方法，其中在所述绝缘层上涂布光刻胶的步骤之前还包括：
    提供衬底基板；
    在所述衬底基板上形成栅电极和公共电极线；
    在形成有所述栅电极和公共电极线的衬底基板上形成所述栅绝缘层；
    在所述栅绝缘层上形成氧化物半导体层；以及
    在所述氧化物半导体层上形成所述刻蚀阻挡层。
  8. 根据权利要求2所述的方法，其中在去除所述绝缘层上覆盖的剩余的光刻胶的步骤之后还包括：
    在所述衬底基板上形成源电极、漏电极和公共电极，所述导电图形为所述公共电极线，所述半导体图形为所述氧化物半导体层，所述源电极和漏电极分别通过各自对应的所述第一过孔与所述氧化物半导体层连接，所述公共电极通过所述第二过孔与所述公共电极线连接；
    形成钝化层；以及
    在所述钝化层上形成像素电极。
  9. 根据权利要求1至8任一项所述的方法，其中所述曝光步骤是采用半色调掩膜板进行的。
  10. 根据权利要求9所述的方法，其中所述半色调掩膜板包括对应于形成所述阵列基板上所述第一过孔的半透光区域和对应于形成所述阵列基板上所述第二过孔的完全透光区域，其中半透光区域的曝光量小于完全透光区域的曝光量，
    进行曝光以至少形成光刻胶部分保留区域、光刻胶完全去除区域的步骤进一步包括：
    利用所述半色调掩膜板对绝缘层上涂布的光刻胶进行曝光，对应于所述完全透光区域形成所述光刻胶完全去除区域，对应于所述半透光区域形成所 述光刻胶部分保留区域。
  11. 一种阵列基板，为采用如权利要求1-10中任一项所述的方法制作得到。
  12. 一种显示装置，包括如权利要求11所述的阵列基板。
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