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WO2015192549A1 - Substrat de réseau, son procédé de fabrication et dispositif d'affichage - Google Patents

Substrat de réseau, son procédé de fabrication et dispositif d'affichage Download PDF

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Publication number
WO2015192549A1
WO2015192549A1 PCT/CN2014/088369 CN2014088369W WO2015192549A1 WO 2015192549 A1 WO2015192549 A1 WO 2015192549A1 CN 2014088369 W CN2014088369 W CN 2014088369W WO 2015192549 A1 WO2015192549 A1 WO 2015192549A1
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WO
WIPO (PCT)
Prior art keywords
layer
photoresist
active layer
region
array substrate
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Ceased
Application number
PCT/CN2014/088369
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English (en)
Chinese (zh)
Inventor
高涛
陈立强
周伟峰
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2015192549A1 publication Critical patent/WO2015192549A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • LCDs liquid crystal displays
  • organic electroluminescent displays or inorganic electroluminescent displays
  • thin film transistors are generally used as switching elements.
  • silicon-based semiconductors such as amorphous silicon (a-Si) and polycrystalline silicon (poly-Si)
  • metal oxide semiconductors are attracting more and more attention.
  • a channel etch protection type structure is mainly used, and the principle of the structure is to cover an etch protection layer on the metal oxide semiconductor for the purpose of the source.
  • the drain electrode can protect the metal oxide semiconductor from being damaged by the metal etching solution.
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device, wherein a pattern of a gate insulating layer and an active layer is simultaneously formed by using a patterning process, that is, etching of a gate insulating layer and a metal oxide semiconductor layer The etching uses the same mask process, which shortens the process and improves yield.
  • an embodiment of the present invention provides an array substrate including: a substrate; a gate electrode, a gate insulating layer, and an active layer sequentially formed on the substrate, wherein the active layer is formed of a metal oxide, The gate insulating layer and the active layer are conformal.
  • an embodiment of the present invention provides a method for fabricating an array substrate, comprising: step S1: forming a pattern of a gate electrode on a substrate; and step S2, simultaneously forming a pattern of a gate insulating layer and an active layer by one patterning process Wherein the active layer is formed of a metal oxide.
  • an embodiment of the present invention further provides a display device including the above array substrate.
  • 1 to 7 are schematic views of respective manufacturing steps in a method of fabricating an array substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic plan view of an array substrate according to an embodiment of the invention.
  • an embodiment of the present invention provides an array substrate including: a substrate 1 , a gate electrode 2 a sequentially formed on the substrate 1 , a gate insulating layer 3 , an active layer 4 , and an etch barrier The layer 5, the source electrode 6a and the drain electrode 6b, the passivation layer 7, and the pixel electrode 8a.
  • the active layer is formed of a metal oxide, and the gate insulating layer 3 and the active layer 4 are conformal, that is, simultaneously formed by the same patterning process.
  • a first via hole 112 is disposed in the etch barrier layer 5, and the source electrode 6a and the drain electrode 6b are electrically connected to the active layer 4 through the first via hole 112.
  • a second via 113 is disposed in the passivation layer 7, and the pixel electrode 8a is connected to the drain electrode 6b through the second via 113.
  • the active layer comprises a single layer of metal oxide, such as IGZO, ITZO, IZO, Cu2O, GZO, AZO or ZnON; or the active layer comprises a plurality of metal oxides, the multilayer metal
  • the oxide is a laminate formed of at least two metal oxides selected from the group consisting of IGZO, ITZO, IZO, Cu 2 O, GZO, AZO or ZnON.
  • embodiments of the present invention also provide a display device including the above array substrate.
  • the display device includes, but is not limited to, a liquid crystal display, a liquid crystal television, etc., and may also be a digital photo frame. Products or parts with display functions such as electronic paper, OLED panels, and mobile phones.
  • an embodiment of the present invention further provides a method for fabricating an array substrate, including the following steps:
  • Step S1 forming a pattern of a gate electrode on the substrate
  • Step S2 simultaneously forming a pattern of a gate insulating layer and an active layer by one patterning process, wherein the active layer is a metal oxide.
  • the step S2 includes:
  • Exposing and developing the photoresist by a common mask process wherein a region corresponding to the pattern of the gate insulating layer and the active layer is formed as a photoresist completely reserved region, except for the photoresist completely reserved region
  • the area is the complete removal area of the photoresist
  • the metal oxide semiconductor layer corresponding to the completely removed region of the photoresist is removed, and the gate insulating film corresponding to the completely removed region of the photoresist is removed by the second etching;
  • Peeling of the remaining photoresist is performed to form a pattern of the gate insulating layer and the active layer.
  • the pattern of the gate insulating layer and the active layer is formed by sharing a mask, thereby avoiding the residue of the photoresist, reducing the number of the mask, shortening the process time, and improving the production. effectiveness.
  • Step 1001 depositing a gate metal film on the substrate 1 (such as a glass substrate or a quartz substrate);
  • the thickness of the gate metal film is 1500 angstroms to 2500 angstroms, and the gate metal film may be selected from the group consisting of Cu, Cu alloy, Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated structure, Al, Al alloy, Forming one or more of Mo/Nd/Cu/Ti/Cu alloys;
  • the remaining photoresist is peeled off to form the gate electrode 2a as shown in FIG.
  • Step 1002 depositing a gate insulating layer 3 by plasma enhanced chemical vapor deposition (PECVD);
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating layer 3 has a thickness of 1000 angstroms to 3,000 angstroms, and may be formed of a single layer film of SiNx or SiOx, or may be formed of a composite of SiNx and SiOx, and the corresponding reaction gas may be SiH 4 , NH 3 , N. 2 or a mixed gas of SiH 2 Cl 2, NH 3, N 2 gas mixture.
  • the metal oxide semiconductor layer has a thickness of 300 angstroms to 1000 angstroms, and the metal oxide semiconductor layer may be oxidized by IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), or Cu 2 O (oxidized).
  • IGZO indium gallium zinc oxide
  • ITZO indium tin zinc oxide
  • IZO indium zinc oxide
  • Cu 2 O oxidized
  • a single-layer metal oxide formed of cuprous, GZO (gallium zinc oxide), AZO (aluminum-doped zinc oxide), HfIZO (yttrium indium zinc oxide) or ZnON (zinc oxynitride) may also be selected from A composite film layer composed of one or more metal oxides of IGZO, ITZO, IZO, Cu 2 O, GZO, AZO, HfIZO, and ZnON.
  • the photoresist is exposed and developed by a common mask process, and after development, a photoresist completely reserved region and a photoresist completely removed region are formed.
  • the photoresist completely reserved region corresponds to the pattern of the gate insulating layer and the active layer, and the photoresist completely removed region corresponds to other regions;
  • etching for example, dry etching
  • Step 1003 depositing a layer of an etch barrier material by, for example, plasma enhanced chemical vapor deposition (PECVD);
  • PECVD plasma enhanced chemical vapor deposition
  • the etching barrier material layer has a thickness of 2000 angstroms to 3000 angstroms, and the material may be a single layer film of SiOx or a composite of SiNx and SiOx, and the corresponding reaction gas may be SiH 4 , NH 3 , N 2 .
  • the photoresist is coated by a common mask process to expose the photoresist, and after the development, the photoresist completely removed region and the photoresist remaining region are formed, and the photoresist completely removed region corresponds to the active layer and the source and drain electrodes.
  • the first via and the gate lead region are in contact with each other, and the photoresist completely reserved region corresponds to other regions.
  • the remaining photoresist is stripped to form an etch stop layer 5 including a first via, as shown in FIG.
  • Step 1004 depositing a source/drain metal film by a method such as sputtering or thermal evaporation;
  • the source-drain metal film has a thickness of 2000 angstroms to 3,000 angstroms, and the material may be a metal such as Mo, Al, Cu, W, or a composite film of several metals. After exposure and development and etching, the source electrode 6a is formed and the leakage is formed. Pole 6b, data line, as shown in Figure 5.
  • Step 1005 depositing a passivation layer 7 by PECVD to a thickness of 1000 angstroms to 3,000 angstroms, and the composition may be SiNx, SiOx, or a composite thereof, and then performing exposure, development, dry etching, and finally forming a drain electrode and A via that contacts the pixel electrode.
  • the passivation layer 7 can also be formed using a photosensitive insulating resin as shown in FIG.
  • Step 1006 depositing a transparent conductive film by using, for example, a magnetron sputtering device, which may be selected from indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum oxide zinc, and has a thickness of 500-1500 angstroms, and then is generally used.
  • a magnetron sputtering device which may be selected from indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum oxide zinc, and has a thickness of 500-1500 angstroms, and then is generally used.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • aluminum oxide zinc aluminum oxide zinc
  • Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device.
  • the patterns of the active layer and the gate insulating layer are formed by the same patterning process using the same mask, thereby avoiding photoresist residue and reducing The number of reticle plates, and the process time is shortened, and the production efficiency is improved.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

La présente invention concerne un substrat de réseau et son procédé de fabrication, ainsi qu'un dispositif d'affichage. Ledit substrat de réseau comprend : un substrat (1) et une électrode de grille (2a), une couche d'isolation de grille (3) et une couche active (4) qui sont formées de manière séquentielle sur le substrat (1). Ladite couche active (4) est formée par un oxyde métallique. Ladite couche d'isolation de grille (3) et la couche active (4) sont conformes. Ladite couche active (4) et la couche d'isolation de grille (3) sont formées en utilisant le même masque à travers le même procédé de formation de motifs, de sorte qu'il n'y a pas de résidu de résine photosensible, le nombre de masques est réduit, le temps de traitement est raccourci et le rendement est amélioré.
PCT/CN2014/088369 2014-06-19 2014-10-11 Substrat de réseau, son procédé de fabrication et dispositif d'affichage Ceased WO2015192549A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410276954.5 2014-06-19
CN201410276954.5A CN104051472A (zh) 2014-06-19 2014-06-19 一种显示装置、阵列基板及其制作方法

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WO2015192549A1 true WO2015192549A1 (fr) 2015-12-23

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WO (1) WO2015192549A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104051472A (zh) * 2014-06-19 2014-09-17 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法
CN104269413B (zh) * 2014-09-22 2017-08-11 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶显示装置
CN106409682A (zh) * 2016-10-11 2017-02-15 深圳市华星光电技术有限公司 一种薄膜晶体管的制作方法
CN107293592A (zh) * 2017-06-12 2017-10-24 深圳市华星光电技术有限公司 显示装置、阵列基板、薄膜晶体管及其制作方法
CN109524356B (zh) * 2018-09-03 2021-08-31 重庆惠科金渝光电科技有限公司 一种阵列基板的制造方法、阵列基板及显示面板

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CN103236440A (zh) * 2013-04-12 2013-08-07 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法、显示装置
US20130242220A1 (en) * 2012-03-15 2013-09-19 Wintek Corporation Thin-film transistor, method of manufacturing the same and active matrix display panel using the same
CN203351574U (zh) * 2013-07-26 2013-12-18 京东方科技集团股份有限公司 阵列基板和显示装置
CN104051472A (zh) * 2014-06-19 2014-09-17 京东方科技集团股份有限公司 一种显示装置、阵列基板及其制作方法

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CN1151406C (zh) * 2000-11-03 2004-05-26 友达光电股份有限公司 薄膜晶体管液晶显示器及其制造方法
CN1185534C (zh) * 2002-05-28 2005-01-19 友达光电股份有限公司 液晶显示装置的有源阵列基板及其制造方法
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CN102651401B (zh) * 2011-12-31 2015-03-18 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制造方法和显示器件
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US20130242220A1 (en) * 2012-03-15 2013-09-19 Wintek Corporation Thin-film transistor, method of manufacturing the same and active matrix display panel using the same
CN103236440A (zh) * 2013-04-12 2013-08-07 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及其制造方法、显示装置
CN203351574U (zh) * 2013-07-26 2013-12-18 京东方科技集团股份有限公司 阵列基板和显示装置
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