WO2015192549A1 - Array substrate and manufacturing method therefor, and display device - Google Patents

Abstract

An array substrate and a manufacturing method therefor, and a display device. The array substrate comprises: a substrate (1) and a gate electrode (2a), a gate insulation layer (3) and an active layer (4) that are sequentially formed on the substrate (1). The active layer (4) is formed by a metal oxide. The gate insulation layer (3) and the active layer (4) are conformal. The active layer (4) and the gate insulation layer (3) are formed by using the same mask through the same patterning process, so that there is no photoresist residue, the number of the masks is reduced, the process time is shortened, and the production efficiency is improved.

Description

Array substrate, manufacturing method thereof and display device Technical field

Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.

Background technique

In liquid crystal displays (LCDs), organic electroluminescent displays, or inorganic electroluminescent displays, thin film transistors are generally used as switching elements. In addition to silicon-based semiconductors such as amorphous silicon (a-Si) and polycrystalline silicon (poly-Si), metal oxide semiconductors are attracting more and more attention.

In the existing thin film transistor using a metal oxide semiconductor, a channel etch protection type structure is mainly used, and the principle of the structure is to cover an etch protection layer on the metal oxide semiconductor for the purpose of the source. The drain electrode can protect the metal oxide semiconductor from being damaged by the metal etching solution. After adopting such a structure, the etching of the gate lead and the etching of the gate insulating layer and the etching of the etching protective layer must be performed by using two mask processes due to the difference in thickness of the film to be etched, not only the process time Long, and also because the photoresist is coated twice on a film, resulting in residual photoresist, destroying device characteristics.

Summary of the invention

Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device, wherein a pattern of a gate insulating layer and an active layer is simultaneously formed by using a patterning process, that is, etching of a gate insulating layer and a metal oxide semiconductor layer The etching uses the same mask process, which shortens the process and improves yield.

In one aspect, an embodiment of the present invention provides an array substrate including: a substrate; a gate electrode, a gate insulating layer, and an active layer sequentially formed on the substrate, wherein the active layer is formed of a metal oxide, The gate insulating layer and the active layer are conformal.

In another aspect, an embodiment of the present invention provides a method for fabricating an array substrate, comprising: step S1: forming a pattern of a gate electrode on a substrate; and step S2, simultaneously forming a pattern of a gate insulating layer and an active layer by one patterning process Wherein the active layer is formed of a metal oxide.

In still another aspect, an embodiment of the present invention further provides a display device including the above array substrate.

DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly described below. It is obvious that the drawings in the following description relate only to some embodiments of the present invention, and are not intended to limit the present invention. .

1 to 7 are schematic views of respective manufacturing steps in a method of fabricating an array substrate according to an embodiment of the present invention;

FIG. 8 is a schematic plan view of an array substrate according to an embodiment of the invention.

detailed description

The technical solutions of the embodiments of the present invention will be clearly and completely described in the following with reference to the accompanying drawings. It is apparent that the described embodiments are part of the embodiments of the invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present invention without departing from the scope of the invention are within the scope of the invention.

Embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The following examples are intended to illustrate the embodiments of the invention, but are not intended to limit the scope of the embodiments of the invention.

As shown in FIG. 7 and FIG. 8 , an embodiment of the present invention provides an array substrate including: a substrate 1 , a gate electrode 2 a sequentially formed on the substrate 1 , a gate insulating layer 3 , an active layer 4 , and an etch barrier The layer 5, the source electrode 6a and the drain electrode 6b, the passivation layer 7, and the pixel electrode 8a.

Wherein the active layer is formed of a metal oxide, and the gate insulating layer 3 and the active layer 4 are conformal, that is, simultaneously formed by the same patterning process.

Illustratively, a first via hole 112 is disposed in the etch barrier layer 5, and the source electrode 6a and the drain electrode 6b are electrically connected to the active layer 4 through the first via hole 112. A second via 113 is disposed in the passivation layer 7, and the pixel electrode 8a is connected to the drain electrode 6b through the second via 113.

Illustratively, the active layer comprises a single layer of metal oxide, such as IGZO, ITZO, IZO, Cu2O, GZO, AZO or ZnON; or the active layer comprises a plurality of metal oxides, the multilayer metal The oxide is a laminate formed of at least two metal oxides selected from the group consisting of IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO or ZnON.

In addition, embodiments of the present invention also provide a display device including the above array substrate. The display device includes, but is not limited to, a liquid crystal display, a liquid crystal television, etc., and may also be a digital photo frame. Products or parts with display functions such as electronic paper, OLED panels, and mobile phones.

In another aspect, an embodiment of the present invention further provides a method for fabricating an array substrate, including the following steps:

Step S1, forming a pattern of a gate electrode on the substrate;

Step S2: simultaneously forming a pattern of a gate insulating layer and an active layer by one patterning process, wherein the active layer is a metal oxide.

Illustratively, the step S2 includes:

Depositing a gate insulating film,

Depositing a layer of metal oxide semiconductor,

Coating a photoresist;

Exposing and developing the photoresist by a common mask process, wherein a region corresponding to the pattern of the gate insulating layer and the active layer is formed as a photoresist completely reserved region, except for the photoresist completely reserved region The area is the complete removal area of the photoresist;

After the first etching, the metal oxide semiconductor layer corresponding to the completely removed region of the photoresist is removed, and the gate insulating film corresponding to the completely removed region of the photoresist is removed by the second etching;

Peeling of the remaining photoresist is performed to form a pattern of the gate insulating layer and the active layer.

In the method for fabricating the array substrate provided by the embodiment of the invention, the pattern of the gate insulating layer and the active layer is formed by sharing a mask, thereby avoiding the residue of the photoresist, reducing the number of the mask, shortening the process time, and improving the production. effectiveness.

Illustratively, an example of a method of fabricating an array substrate is given below.

Step 1001: depositing a gate metal film on the substrate 1 (such as a glass substrate or a quartz substrate);

The thickness of the gate metal film is 1500 angstroms to 2500 angstroms, and the gate metal film may be selected from the group consisting of Cu, Cu alloy, Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated structure, Al, Al alloy, Forming one or more of Mo/Nd/Cu/Ti/Cu alloys;

Coating a photoresist;

Exposing the photoresist with a common mask;

Wet etching the gate metal film;

The remaining photoresist is peeled off to form the gate electrode 2a as shown in FIG.

Step 1002: depositing a gate insulating layer 3 by plasma enhanced chemical vapor deposition (PECVD);

The gate insulating layer 3 has a thickness of 1000 angstroms to 3,000 angstroms, and may be formed of a single layer film of SiNx or SiOx, or may be formed of a composite of SiNx and SiOx, and the corresponding reaction gas may be SiH ₄ , NH ₃ , N. ₂ or a mixed gas of _{SiH 2 Cl 2, NH 3,} N ₂ gas mixture.

Depositing a layer of a metal oxide semiconductor;

The metal oxide semiconductor layer has a thickness of 300 angstroms to 1000 angstroms, and the metal oxide semiconductor layer may be oxidized by IGZO (indium gallium zinc oxide), ITZO (indium tin zinc oxide), IZO (indium zinc oxide), or Cu 2 O (oxidized). a single-layer metal oxide formed of cuprous, GZO (gallium zinc oxide), AZO (aluminum-doped zinc oxide), HfIZO (yttrium indium zinc oxide) or ZnON (zinc oxynitride) may also be selected from A composite film layer composed of one or more metal oxides of IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO, HfIZO, and ZnON.

Coating a photoresist;

The photoresist is exposed and developed by a common mask process, and after development, a photoresist completely reserved region and a photoresist completely removed region are formed. Wherein the photoresist completely reserved region corresponds to the pattern of the gate insulating layer and the active layer, and the photoresist completely removed region corresponds to other regions;

Removing the metal oxide semiconductor layer of the photoresist completely removed region by a first etching, for example, wet etching;

Then removing the gate insulating layer of the photoresist completely removed region by a second etching, for example, dry etching;

Finally, the peeling of the remaining photoresist is performed to form the pattern 3 of the gate insulating layer and the pattern 4a of the active layer as shown in FIGS. 2 and 3.

Step 1003: depositing a layer of an etch barrier material by, for example, plasma enhanced chemical vapor deposition (PECVD);

The etching barrier material layer has a thickness of 2000 angstroms to 3000 angstroms, and the material may be a single layer film of SiOx or a composite of SiNx and SiOx, and the corresponding reaction gas may be SiH ₄ , NH ₃ , N ₂ . A mixed gas or a mixed gas of SiH ₂ Cl ₂ , NH ₃ , and N ₂ .

Then, the photoresist is coated by a common mask process to expose the photoresist, and after the development, the photoresist completely removed region and the photoresist remaining region are formed, and the photoresist completely removed region corresponds to the active layer and the source and drain electrodes. The first via and the gate lead region are in contact with each other, and the photoresist completely reserved region corresponds to other regions.

Dry etching the etch barrier material layer;

The remaining photoresist is stripped to form an etch stop layer 5 including a first via, as shown in FIG.

Step 1004: depositing a source/drain metal film by a method such as sputtering or thermal evaporation;

The source-drain metal film has a thickness of 2000 angstroms to 3,000 angstroms, and the material may be a metal such as Mo, Al, Cu, W, or a composite film of several metals. After exposure and development and etching, the source electrode 6a is formed and the leakage is formed. Pole 6b, data line, as shown in Figure 5.

Step 1005: depositing a passivation layer 7 by PECVD to a thickness of 1000 angstroms to 3,000 angstroms, and the composition may be SiNx, SiOx, or a composite thereof, and then performing exposure, development, dry etching, and finally forming a drain electrode and A via that contacts the pixel electrode. The passivation layer 7 can also be formed using a photosensitive insulating resin as shown in FIG.

Step 1006: depositing a transparent conductive film by using, for example, a magnetron sputtering device, which may be selected from indium tin oxide (ITO), indium zinc oxide (IZO), or aluminum oxide zinc, and has a thickness of 500-1500 angstroms, and then is generally used. The reticle is subjected to an exposure process, developed and wet etched to form a pixel electrode 8a as shown in FIG.

Embodiments of the present invention provide an array substrate, a method for fabricating the same, and a display device. The patterns of the active layer and the gate insulating layer are formed by the same patterning process using the same mask, thereby avoiding photoresist residue and reducing The number of reticle plates, and the process time is shortened, and the production efficiency is improved.

The above is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention. It should also be considered as the scope of protection of the present invention.

The present application claims the priority of the Chinese Patent Application No. 201410276954.5 filed on Jun. 19, 2014, the content of

Claims (18)

An array substrate comprising: Substrate a gate electrode, a gate insulating layer and an active layer are sequentially formed on the substrate, Wherein the active layer is formed of a metal oxide, and the gate insulating layer and the active layer are conformal. The array substrate of claim 1 further comprising: Etching the barrier layer, the source electrode and the drain electrode, disposed on the active layer, A first via hole is formed in the etch barrier layer, and the source electrode and the drain electrode are connected to the active layer through the first via hole. The array substrate of claim 2, further comprising: a passivation layer and a pixel electrode are sequentially disposed on the source electrode and the drain electrode, A second via hole is formed in the passivation layer, and the pixel electrode is electrically connected to the drain electrode through the second via hole. The array substrate according to any one of claims 1 to 3, wherein the active layer comprises a single layer of metal oxide. The array substrate according to any one of claims 1 to 3, wherein the active layer comprises a plurality of metal oxides. The array substrate according to claim 4, wherein the single layer metal oxide is IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO or ZnON. The array substrate according to claim 5, wherein the multilayer metal oxide is a stack of at least two metal oxides selected from the group consisting of IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO or ZnON Floor. A method for fabricating an array substrate, comprising: Step S1, forming a pattern of a gate electrode on the substrate; Step S2: simultaneously forming a pattern of a gate insulating layer and an active layer by one patterning process, wherein the active layer is formed of a metal oxide. The production method according to claim 8, wherein the step S2 comprises: Depositing a gate insulating film, Depositing a layer of metal oxide semiconductor, Coating a photoresist; Exposing and developing the photoresist by a common mask process, wherein a region corresponding to the pattern of the gate insulating layer and the active layer is formed as a photoresist completely reserved region except the photoresist completely reserved region a region other than the photoresist is completely removed; Removing the metal oxide semiconductor layer corresponding to the completely removed region of the photoresist by a first etching, and removing the gate insulating film corresponding to the completely removed region of the photoresist by a second etching; The remaining photoresist is stripped to form a pattern of the gate insulating layer and the active layer. The manufacturing method according to claim 8, further comprising: Step S3, forming a pattern of an etch barrier layer, a source electrode and a drain electrode on the pattern of the active layer, a first via hole formed in the etch barrier layer, and the source electrode and the drain electrode pass The first via is connected to the pattern of the active layer. The manufacturing method according to claim 10, wherein the step S3 comprises: Depositing a layer of etch barrier material; Coating a photoresist; Exposing and developing the photoresist by a common mask process, wherein a region corresponding to the first via hole in the etch barrier layer and a gate lead region are formed as a photoresist completely removed region, except the light The region outside the completely removed region of the engraved gel is formed as a completely reserved region of the photoresist; Dry etching the etch barrier material layer; The remaining photoresist is stripped to form an etch stop layer including the first via. The production method according to claim 8, wherein the step S1 comprises: Depositing a gate metal film on the substrate; Coating a photoresist; Exposing and developing the photoresist by a common mask process, wherein a region corresponding to the gate electrode is formed as a photoresist completely removed region, and a region other than the photoresist completely removed region is formed as a photoresist Completely reserved area; Etching the gate metal film; The remaining photoresist is stripped to form the gate electrode. The fabricating method according to claim 12, wherein the gate metal film is selected from the group consisting of Cu, Cu alloy, Mo, Mo-Al-Mo alloy, Mo/Al-Nd/Mo laminated structure, Al, Al alloy, One or more of Mo/Nd/Cu/Ti/Cu alloys are formed. The fabricating method according to claim 9, wherein the metal oxide semiconductor layer is a single-layer metal oxide formed of IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO, HfIZO or ZnON. The fabricating method according to claim 9, wherein the metal oxide semiconductor layer is composed of one or more metal oxides selected from the group consisting of IGZO, ITZO, IZO, Cu ₂ O, GZO, AZO, HfIZO, and ZnON. Composite film layer. The fabricating method according to claim 11, wherein the etch barrier material layer is a single layer film formed of SiOx. The fabricating method according to claim 11, wherein the etch barrier material layer is a composite film formed of SiNx and SiOx. A display device comprising the array substrate of any one of claims 1-7.

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