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WO2015140329A1 - Production de structures stratifiées de type semi-conducteur sur isolant - Google Patents

Production de structures stratifiées de type semi-conducteur sur isolant Download PDF

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Publication number
WO2015140329A1
WO2015140329A1 PCT/EP2015/056006 EP2015056006W WO2015140329A1 WO 2015140329 A1 WO2015140329 A1 WO 2015140329A1 EP 2015056006 W EP2015056006 W EP 2015056006W WO 2015140329 A1 WO2015140329 A1 WO 2015140329A1
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WIPO (PCT)
Prior art keywords
layer
germanium
mesa
containing group
semiconductor layer
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Ceased
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PCT/EP2015/056006
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German (de)
English (en)
Inventor
Yuji Yamamoto
Bernd Tillack
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IHP GmbH
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IHP GmbH
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    • H10P14/3411—
    • H10P14/271—
    • H10P14/276—
    • H10P14/3211—
    • H10P14/3421—

Definitions

  • the invention relates to a method for producing a germanium-containing group IV semiconductor layer on an insulator, hereinafter referred to as IV-OI layer structure, an IV-OI layer structure and an IV-OI chip and a III-V-Ol chip.
  • IV-OI layer structure a germanium-containing group IV semiconductor layer on an insulator, hereinafter referred to as IV-OI layer structure, comprising the steps:
  • the present invention provides a method for producing an IV-OI layer structure by which a germanium-containing group IV semiconductor layer having a particularly low dislocation density, or even dislocation-free, is grown directly vertically adjacent to an insulator layer. In this sense, it can be said that the germanium-containing group IV semiconductor layer is grown "on top" of the insulator layer.
  • the present lateral epitaxial growth method it is possible to grow a germanium-containing group IV semiconductor layer over a large area on an insulator layer.
  • the fabrication of the IV-OI layer structure can be integrated into existing CMOS technologies.
  • the invention enables the production of low-dislocation or even dislocation-free germanium-containing group-IV semiconductor layers having a comparatively particularly smooth surface on an insulator.
  • the cavity in which the lateral growth of the germanium-containing group IV semiconductor layer begins at the side surface of the mesa Si layer in particular acts close to the interface of mesa Si layer and germanium-containing group IV semiconductor layer as a so-called trap for dislocation , in particular for screw dislocations.
  • the process makes it possible to produce dislocation-free germanium-containing group-IV semiconductor layers with areal extents of several ⁇ m 2 .
  • the term "masked exposure of the buried insulator layer" means that the buried insulator layer is exposed in such, but not necessarily all, areas in which no mesa is to be left in. For the definition of the areas to be exposed, known methods of masked structuring be used.
  • the material of the germanium-containing group IV semiconductor layer is pure germanium.
  • Further advantageous materials which are to be produced by the process according to the invention are, for example, silicon germanium compounds, in particular those with a predominant germanium content. Due to its direct band gap of approx. 0.8 eV, germanium is a promising material for optoelectronic components. To reduce the dark current of SiGe or Ge photodiodes, a high crystal quality of SiGe or germanium is required.
  • Germanium-on-insulator (GeOI) substrates are widely used for the production of optoelectronic semiconductor devices with pure germanium. In general, however, these GeOI substrates are produced by wafer bonding techniques, since the required high quality of germanium deposition in the prior art could be achieved predominantly on silicon. In the present case, instead of this known complicated production technology, a method is proposed which, as can be seen below with reference to further exemplary embodiments, can be integrated into existing industrial production technologies and therefore means significantly less expenditure. As already mentioned, the embodiments described below are not limited to the case of a pure germanium layer, but can also be used for alloys with other group IV materials. Nevertheless, for the sake of simplicity, the special case of the germanium layer is often described below, this being understood merely as an advantageous example of a germanium-containing group IV semiconductor layer.
  • the lateral extent of the cavity is greater than 0.8 times the height of the cavity and thus the thickness of the mesa. Si layer, in particular greater than the height of the cavity.
  • the side surface of the mesa Si layer is oriented in the [100] or [1 10] direction, even a ratio of lateral expansion to the height of the cavity of 0.8 already favors the growth of dislocation-free regions.
  • dislocation-free thin germanium-containing group IV semiconductor layers can be produced with the lateral growth used here.
  • the germanium-containing group IV semiconductor layers grow exclusively in the cavity.
  • the thickness of the semiconductor layers corresponds to the height of the cavity and can thus be adjusted without further measures.
  • the thickness of the semiconductor layers can be adjusted over a wide range according to the requirements for subsequent use of the semiconductor layers, for example, thicknesses in the range of 50 nm to 5 ⁇ adjustable.
  • the germanium-containing group-IV semiconductor layer is prevented, for example by setting suitable process parameters.
  • the layer thickness can be better controlled and the formation of additional dislocations avoided.
  • the insulator layer consists of Si0 2 at least at its interface to the Si layer.
  • the covering layer therefore consists of Si0 2 . Deposition methods for Si0 2 on silicon are known from the prior art and are compatible with CMOS processes, so that known methods can be used here.
  • the cavity is shaped by selective etching of the silicon. By selectively etching the silicon, complete removal of the silicon at the interface with the cap layer as well as at the interface with the insulator layer can be achieved. This can be used to ensure that apart from the side surface of the mesa-Si layer, no further Si-seed sites are provided for the epitaxial growth of germanium. Hereby transfers are even better avoided.
  • the lateral surface of the mesa Si layer offered for the lateral growth of the germanium-containing group IV semiconductor is oriented in the [100] direction, that is to say that the surface vector of this side surface points in the [100] direction.
  • the lateral epitaxial growth of the germanium-containing group-IV semiconductor layer then takes place with a growth front, which is also oriented in the [100] -direction.
  • Another, likewise advantageous orientation direction of the side surface of the mesa Si layer and the growth front of the germanium-containing group IV semiconductor layer is the [1 10] direction. Since possible dislocations in the germanium-containing group IV semiconductor layer predominantly proceed in the [1 10] direction, extensive areas of the germanium-containing group IV result from the protruding orientations of the side surface of the mesa Si layer and the growth direction of the germanium. Semiconductor layer, which are dislocation-free.
  • the lateral epitaxial growth of the germanium-containing group-IV semiconductor layer takes place according to the method according to the invention on a side surface of the mesa-Si layer.
  • the selectivity of the growth process such that only silicon is suitable as an ankerage surface is achieved in preferred embodiments of the method via a suitable adjustment of the growth parameters.
  • Preferred manipulated variable In order to achieve selectivity, growth temperature and, in preferred gas phase epitaxial processes such as MOCVD, the choice of precursor of the group IV semiconductor to be produced.
  • germanium is advantageously carried out at 650 ° C.
  • a preferred precursor is GeH 4 . This is used, for example, together with HCl as a process gas in the ratio 1:10. HCl thereby improves the selectivity of the growth of germanium on silicon.
  • GeH 2 Cl 2 , GeHCl 3 or GeCl 3 can be used as precursor for growth of germanium.
  • germanium-containing group-IV semiconductor layers which additionally contain silicon, SiH 4 , SiH 2 Cl 2 , SiHCl 3 or SiCl 3 are suitable, for example
  • the germanium-containing group IV semiconductor layer is doped in situ during the lateral epitaxial growth. This enables the setting of suitable doping profiles in germanium. Particularly preferably, the temporal variation of the dopant concentration achieves a lateral doping profile of the epitaxially grown germanium-containing group IV semiconductor layer.
  • a so-called HF dip takes place, in which case oxides adhering to the side walls of the mesa-Si layer are removed.
  • the growth of the germanium-containing group IV semiconductor layer is stopped when the cavity is completely filled with the germanium-containing group IV semiconductor layer. At least parts of the germanium-containing group IV semiconductor layer grow without dislocation.
  • growth of the germanium-containing group IV semiconductor layer is stopped before the cavity is completely filled by the germanium-containing group IV semiconductor layer.
  • Subsequent clipping produces at least one IV-OI chip, wherein the IV-OI chip comprises a dislocation-free region of the germanium-containing group IV semiconductor layer together with underlying regions of the substrate.
  • the method described enables the production of IV-OI chips with dislocation-free germanium-containing group-IV semiconductor layers directly on a Insulator layer.
  • IV-OI chips with dimensions of several square microns can be achieved.
  • the cutting can be done for example via photolithography processes.
  • a substrate having a cavity which does not completely fill the germanium-containing group IV semiconductor layer is used as the starting point, in order to produce in a further step a group III-V semiconductor layer starting from a side surface of the germanium-containing group IV thus produced - Semiconductor layer grow epitaxially laterally.
  • the produced IV-OI layer structure is used as a growth substrate for a group III-V semiconductor.
  • at least one III-V-Ol chip can then be produced by singulation, the III-V-Ol chip comprising a dislocation-free region of the group II-V layer together with underlying regions of the substrate.
  • the mesa cap layer can be removed to expose the germanium-containing group IV semiconductor layer or group III-V layer. This can be done for example by further Litographie redesigne or by an etching process.
  • the invention relates to a layer structure with a germanium-containing group IV semiconductor layer on an insulator, hereinafter referred to as IV-OI layer structure having
  • a substrate having an insulator layer and at least one mesa, which has a mesa cover layer and a mesa Si layer on the insulator layer, and with a cavity in the mesa under the mesa cover layer, as well as
  • germanium-containing group IV semiconductor layer grown laterally epitaxially from at least one side surface of the mesa Si layer.
  • the germanium-containing group IV semiconductor layer extends completely within the cavity. In particular, it does not extend beyond the cavity.
  • the germanium-containing group IV semiconductor layer completely fills the cavity in one of these embodiments.
  • the germanium containing group IV semiconductor layer in the lateral direction only parts of the cavity. In the vertical direction, however, it prefers to completely fill the cavity.
  • a development of this embodiment comprises at least one group III-V semiconductor layer grown laterally epitaxially on the side surface of the germanium-containing group IV semiconductor layer that is located in the cavity.
  • the invention relates to an IV-OI chip comprising a laterally epitaxially grown dislocation-free germanium-containing group IV semiconductor layer on an insulator layer.
  • the insulator layer is arranged on a carrier substrate in one embodiment of the IV-OI chip.
  • the invention relates to an III-V-Ol chip comprising a laterally epitaxially grown dislocation-free Group III-V semiconductor layer on an insulator layer.
  • the insulator layer is arranged on a carrier substrate in one embodiment of the IV-OI chip.
  • the IV-OI layer structure as well as the IV-OI chip and the III-V-Ol chip share the advantages of the method according to the first aspect of the invention.
  • FIG. 1 schematically shows a flowchart of an embodiment of a method for producing an IV-OI layer structure according to the first aspect of the invention and schematically the intermediates of the individual steps of the method;
  • FIG. 3 is a scanning electron micrograph of an intermediate product of the method described in FIG. 1, 4 schematically shows three IV-OI layer structures according to the second aspect of the invention.
  • FIG. 5 shows two transmission electron microscopic (TEM) images of an IV-OI layer structure according to the second aspect of the invention
  • FIG. 6 shows two transmission electron micrographs of a further embodiment of an IV-OI layer structure according to the second aspect of the invention
  • FIG. 7 shows a scanning force microscope image of a further IV-OI layer structure according to the second aspect of the invention.
  • FIG. 1 schematically shows a flow chart of an embodiment of a method for producing an IV-OI layer structure according to the first aspect of the invention and schematically the intermediates of the individual steps of the method.
  • a substrate 110 having an Si layer 120 arranged on a buried insulator layer 11 and a cover layer 130 on the Si layer is firstly provided.
  • the substrate is a silicon-on-insulator (SOI) substrate.
  • the buried insulator layer 15 is a Si0 2 layer.
  • the cover layer 130 is made of Si0 2 in the present embodiment.
  • a mesa 140 having a mesa cover layer 131 and a mesa-Si layer 121 is formed by exposing the insulator layer 15 locally.
  • the exposure is done, for example, by reactive ion etching (RIE).
  • RIE reactive ion etching
  • side surfaces of the Si layer having a (010) or (1 10) surface are exposed.
  • a so-called pre-epi purification of the resulting intermediate with hydrofluoric acid (HF) take place.
  • oxides on the sidewall of the Si layer may optionally be removed by heating to 850 ° C in a hydrogen atmosphere.
  • a cavity 150 is formed in the mesa 140 under the mesa cover layer 130 by removing the mesa Si layer 120 laterally only limited but vertically but completely.
  • the removal of the mesa-Si layer is done here by means of selective etching, for example with HCl. Thickness losses of the buried layer or the cover layer are negligible in the HCI etching used.
  • a so-called HF dip can be performed.
  • oxides on the sidewall of the mesa-Si layer can also be removed.
  • a germanium-containing group IV semiconductor layer 160 grows laterally epitaxially and selectively, ie, exclusively on the side surface 125 of the mesa Si layer 120.
  • the germanium-containing group IV semiconductor layer fills the cavity.
  • the growth can also be stopped before the complete lateral filling of the cavity.
  • the result is an IV-OI layer structure 100.
  • an H 2 -GeH 4 - HCl gas mixture is used in the present embodiment.
  • dislocation-free regions of the germanium-containing group IV semiconductor layer are formed. The semiconductor product produced so far can be traded as an intermediate.
  • the dislocation-free regions can be cut out together with the underlying regions of the substrate and singulated so that an IV oil chip with a dislocation-free germanium-containing group IV Semiconductor layer is provided on an insulator.
  • the mesa cover layer is removed by means of lithographic processes or etching processes.
  • the surface of the germanium-containing group IV semiconductor layer shows the same smoothness as the interface between the Si layer and the cover layer. A post-treatment for smoothing the surface, as it is mandatory in known methods, is therefore no longer necessary here.
  • the achievable dimensions of the IV-OI chip fabricated by the described method are in the range of several square microns and are therefore large enough for use in semiconductor devices.
  • step S5b a step S5b described below may be performed.
  • step S5b the growth of the germanium-containing group IV semiconductor layer 161 is stopped before the cavity is laterally completely filled by the germanium-containing group IV semiconductor layer.
  • a group III-V semiconductor material grows laterally epitaxially in a subsequent step S6.
  • the resulting Group III-V layer fills the cavity and grows laterally on the surface of the insulator layer.
  • step S7b dislocation-free regions of the group III-V layer can then be separated together with underlying regions of the substrate and the mesa covering layer can be removed.
  • the process thus results in a III-V OI chip in which a Group III-V material is grown directly on an insulator layer without dislocation.
  • Particularly preferred here is GaAs as group III-V material
  • FIG. 2 shows, in subfigures 2a to 2d, scanning electron micrographs of intermediates of an embodiment of the method according to the first aspect of the invention.
  • 2a and 2c show mesas 240 that have been structured in such a way that the side surfaces of the mesa Si layer 220 that are available after the formation of the cavity for the growth of the germanium-containing group IV semiconductor layer, here a pure germanium layer, are available are oriented in the ⁇ 1 10> direction.
  • FIG. 2 a shows the intermediate product after step S 3 of the method described with reference to FIG. 1.
  • Fig. 2c shows these structures after optional step S4, in which oxides grown on the side surface of the mesa Si layer have been removed by HF dip.
  • FIGS. 2b and 2d are also intermediate products after the described steps S3 (FIG. 2b) and S4 (FIG. 2d). shown.
  • the mesas have been shaped by means of masks in such a way that the lateral surfaces of the mesa Si layer which are available after the formation of the cavity for the growth of the germanium layer are oriented in the ⁇ 100> direction ,
  • FIG. 3 shows a scanning electron micrograph of an intermediate product of the method described in FIG. 1 after step S3 in detail.
  • a cavity 350 was formed, here by means of selective etching with HCl. Left is to recognize the remaining mesa Si layer 320 with the side surface 325.
  • the insulator layer 315 was exposed.
  • the lateral extent L of the cavity is significantly greater than the height H of the cavity.
  • FIG. 4 schematically shows three IV-OI layer structures.
  • a germanium-containing group-IV semiconductor layer 460 is grown in the cavity 450 on side surfaces of the mesa-Si layer 420.
  • the germanium-containing group-IV semiconductor layer 460 is still completely covered by the cover layer 430, leaving a residual cavity.
  • Such IV-OI layer structures can be used on the one hand for the formation of an extended germanium-containing group IV semiconductor layer on the insulator layer 415 of the substrate 410.
  • FIG. 4b here the germanium-containing group IV semiconductor layer 460 of the IV-Ol layer structure 400 laterally completely fills the cavity.
  • a further possibility for using the IV-OI layer structure 401 consists in the use of the germanium-containing group IV semiconductor layer 460 again as an anvil surface for the lateral growth of a group III-V layer 480 from a group III-V semiconductor material, such as GaAs. This is shown in Fig. 4c.
  • the group III-V layer 480 is selectively epitaxially grown on a side surface 465 of the germanium-containing group IV semiconductor layer.
  • a further dislocation-free Group III-V layer 480 is formed on a surface of the insulator layer 415 within the cavity.
  • Fig. 5 shows two transmission electron micrographs (TEM) images of an IV-OI layer structure according to the second aspect of the invention.
  • the sample area examined by means of TEM lies approximately in the plane designated AA in FIG. 4b.
  • the side surfaces 525 of the mesa Si layer 520 are oriented in the ⁇ 1 10> direction.
  • the displacements 570 present in the germanium-containing group IV semiconductor layer 560, here again a germanium layer, run in the [1 10] direction, so that dislocation-free regions 566 of the germanium-containing group IV semiconductor layer 560 are formed.
  • Fig. 5b shows an enlarged detail of such a dislocation-free region 566.
  • FIG. 6 shows, like FIG. 5, two TEM images of an IV-OI layer structure in two partial figures 6a and 6b, the plane shown substantially corresponding to the plane A-A marked in FIG.
  • FIG. 6 shows an IV-OI layer structure in which side surfaces 625 of the mesa Si layer 620 are oriented in the ⁇ 100> direction and a germanium layer 660 also has a growth front in the ⁇ 100> direction , Again, dislocations 670 run in the germanium layer 660 in the [1 10] direction.
  • a dislocation-free region 666 of the germanium-containing group-IV semiconductor layer 660 also results in FIG. 6a. This region can be separated together with the underlying substrate to form an IV-OI chip.
  • the dislocation-free region 666 of the germanium layer 660 is shown again in detail.
  • FIG. 7 shows a scanning force micrograph of an IV-OI layer structure corresponding to that shown in FIG.
  • the side surfaces of a germanium layer 760 are oriented here in the [010] direction.
  • the mesa cap layer, here Si0 2 was removed by RF dip after growth of germanium layer 760.
  • the interface 726 between the germanium layer 760 and the mesa Si layer 720 is visible and parallel to the [1 14] direction.
  • the root mean square roughness of the germanium layer is about 0.4 nm. It is determined by the interface roughness between the Si layer and the cap layer.

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Abstract

L'invention concerne un procédé de fabrication d'une couche de semi-conducteur du groupe IV contenant du germanium sur un isolant, comprenant les étapes consistant à : préparer un substrat (110) qui possède une couche de Si (120) sur une couche isolante enterrée (115) et une couche de recouvrement (130) par-dessus la couche de Si (120) du substrat (110) ; former au moins une structure mésa (140) possédant une couche de recouvrement mésa (130) et une couche de Si mésa (120) en dégageant au moyen d'un masque la couche isolante enterrée (115) de la couche de recouvrement ; former une cavité (150) dans la structure mésa (140), sous la couche de recouvrement mésa, en éliminant de manière limitée latéralement mais complète verticalement la couche de Si mésa sous la couche de recouvrement mésa afin de dégager ainsi dans la cavité au moins une face latérale (125) de la couche de Si mésa ; et faire croître par épitaxie latérale une couche de semi-conducteur du groupe IV contenant du germanium (160) à partir de la face latérale ainsi formée de la couche de Si mésa.
PCT/EP2015/056006 2014-03-21 2015-03-20 Production de structures stratifiées de type semi-conducteur sur isolant Ceased WO2015140329A1 (fr)

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DE102014205364.1A DE102014205364A1 (de) 2014-03-21 2014-03-21 Herstellung von Halbleiter-auf-Isolator-Schichtstrukturen
DE102014205364.1 2014-03-21

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FR3071098A1 (fr) * 2017-09-13 2019-03-15 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un element d'un dispositif microelectronique
CN110137244A (zh) * 2019-04-09 2019-08-16 华南师范大学 GaN基自支撑衬底的垂直结构HEMT器件及制备方法

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3071098A1 (fr) * 2017-09-13 2019-03-15 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de realisation d'un element d'un dispositif microelectronique
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CN110137244A (zh) * 2019-04-09 2019-08-16 华南师范大学 GaN基自支撑衬底的垂直结构HEMT器件及制备方法
CN110137244B (zh) * 2019-04-09 2022-07-12 华南师范大学 GaN基自支撑衬底的垂直结构HEMT器件及制备方法

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