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WO2015049772A1 - Dispositif de stockage et procédé de commande du dispositif de stockage - Google Patents

Dispositif de stockage et procédé de commande du dispositif de stockage Download PDF

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Publication number
WO2015049772A1
WO2015049772A1 PCT/JP2013/077001 JP2013077001W WO2015049772A1 WO 2015049772 A1 WO2015049772 A1 WO 2015049772A1 JP 2013077001 W JP2013077001 W JP 2013077001W WO 2015049772 A1 WO2015049772 A1 WO 2015049772A1
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WIPO (PCT)
Prior art keywords
columnar
gate
semiconductor layer
layer
insulating film
Prior art date
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Ceased
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PCT/JP2013/077001
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English (en)
Japanese (ja)
Inventor
富士雄 舛岡
広記 中村
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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Priority to PCT/JP2013/077001 priority Critical patent/WO2015049772A1/fr
Publication of WO2015049772A1 publication Critical patent/WO2015049772A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention relates to a storage device and a method for manufacturing the storage device.
  • phase change memories have been developed (see, for example, Patent Document 1).
  • the phase change memory stores information by recording the change in resistance of the information storage element of the memory cell.
  • chalcogenide glass Ge 2 Sb 2 in contact with the heater.
  • Te 5 chalcogenide glass melts at high temperature (high current) and cools at high speed (stops current), it becomes amorphous (reset operation), while it melts at relatively low temperature (low current) and slows down. And crystallize (set [Set] operation).
  • a reset current flows as much as 200 ⁇ A.
  • a bipolar transistor or a diode selection element can be used (see, for example, Patent Document 1).
  • the diode Since the diode is a two-terminal element, when one source line is selected to select a memory cell, the current of all the memory cells connected to that one source line flows to one source line. become. Therefore, the IR drop that is a voltage drop of the IR (current, resistance) product in the source line becomes large.
  • a bipolar transistor is a three-terminal element, but since a current flows through the gate, it is difficult to connect many transistors to the word line.
  • the reset current and the read current can be reduced.
  • the heater element is formed on the side wall of the gate of the planar transistor, and the GST film is formed on the gate, thereby reducing the cross-sectional area in the direction in which current flows in the GST film and the heater element.
  • This method requires a cell string in which a plurality of cells made of planar transistors are connected in series (see, for example, Patent Document 1).
  • SGT Surrounding Gate Transistor
  • a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a columnar semiconductor layer
  • SGT can flow a larger amount of current than a double gate transistor per unit gate width (see, for example, Patent Document 2).
  • the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate width per unit area can be increased, so that a larger amount of current can flow.
  • the present invention has been made in view of the above-described problems, and provides a memory device capable of reducing the cross-sectional area in the direction in which the current of the film whose resistance changes and the lower electrode flows, and a method for manufacturing the same. For the purpose.
  • the storage device provides: A film with variable resistance formed around the top of the columnar insulator layer; And a lower electrode connected to the film whose resistance changes, which is formed around the lower part of the columnar insulator layer.
  • the columnar insulator layer is made of a nitride film,
  • the lower electrode is formed below the columnar insulator layer, It is preferable.
  • the semiconductor device includes a fin-like semiconductor layer formed on a semiconductor substrate; A first insulating film formed around the fin-like semiconductor layer; The first columnar semiconductor layer formed on the fin-like semiconductor layer; The gate electrode, and the gate insulating film formed around and under the gate electrode and the gate wiring, The gate electrode and the gate wiring are made of metal, The gate wiring extends in a direction orthogonal to the fin-like semiconductor layer, The second diffusion layer is formed in the fin-like semiconductor layer. It is preferable.
  • the second diffusion layer is formed on the semiconductor substrate.
  • the semiconductor device includes the fin-like semiconductor layer formed on the semiconductor substrate; The first insulating film formed around the fin-like semiconductor layer; A second columnar semiconductor layer formed on the fin-like semiconductor layer; A contact electrode made of metal and formed around the second columnar semiconductor layer; The contact wiring made of metal, extending in a direction perpendicular to the fin-like semiconductor layer connected to the contact electrode; The fin-like semiconductor layer and the second diffusion layer formed below the second columnar semiconductor layer; The contact electrode is connected to the second diffusion layer; It is preferable.
  • the line width outside the gate electrode is equal to the line width of the gate wiring
  • the line width of the first columnar semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is equal to the line width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer. It is preferable.
  • the semiconductor device preferably includes the gate insulating film formed between the second columnar semiconductor layer and the contact electrode.
  • the line width of the second columnar semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer is preferably equal to the line width of the fin-shaped semiconductor layer in the direction orthogonal to the fin-shaped semiconductor layer.
  • the semiconductor device includes the gate insulating film formed around the contact electrode and the contact wiring.
  • the line width outside the contact electrode is equal to the line width of the contact wiring.
  • the semiconductor device has the first columnar semiconductor layer formed on a semiconductor substrate, The gate insulating film formed around and under the bottom of the gate electrode and the gate wiring, and The gate electrode and the gate wiring are made of metal, The second diffusion layer is formed on the semiconductor substrate; It is preferable.
  • the semiconductor device has a contact wiring extending in parallel with the gate wiring connected to the second diffusion layer.
  • the semiconductor device includes a second columnar semiconductor layer formed on the semiconductor substrate; A contact electrode made of metal and formed around the second columnar semiconductor layer; Contact wiring connected to the contact electrode; The second diffusion layer formed under the second columnar semiconductor layer, and The contact electrode is connected to the second diffusion layer; It is preferable.
  • the line width outside the gate electrode is preferably equal to the line width of the gate wiring.
  • the semiconductor device includes the gate insulating film formed between the second columnar semiconductor layer and the contact electrode. It is preferable.
  • the semiconductor device includes the gate insulating film formed around the contact electrode and the contact wiring.
  • the line width outside the contact electrode is equal to the line width of the contact wiring.
  • a method for manufacturing a storage device includes: A second interlayer insulating film is deposited on the semiconductor substrate to form a contact hole, and a second metal layer and a nitride film are deposited, By removing the second metal layer and the nitride film on the second interlayer insulating film, a columnar insulator layer, a bottom portion of the columnar insulator layer, and the columnar insulation are formed inside the contact hole.
  • a fin-like semiconductor layer extending in one direction on a semiconductor substrate, and forming a first insulating film around the fin-like semiconductor layer; After the first step, a second insulating film is formed around the fin-like semiconductor layer, Depositing and planarizing a first polysilicon on the second insulating film; A second resist for forming the gate wiring, the first columnar semiconductor layer, the second columnar semiconductor layer, and the contact wiring is formed so as to extend in a direction orthogonal to the direction in which the fin-shaped semiconductor layer extends. And The first dummy derived from the first columnar semiconductor layer and the first polysilicon by etching the first polysilicon, the second insulating film, and the fin-like semiconductor layer.
  • a second step of forming a gate, the second columnar semiconductor layer, and a second dummy gate derived from the first polysilicon After the second step, a fourth insulating film is formed around the first columnar semiconductor layer, the second columnar semiconductor layer, the first dummy gate, and the second dummy gate, Second polysilicon is deposited and etched around the fourth insulating film, and the first dummy gate, the first columnar semiconductor layer, the second dummy gate, and the second columnar shape are etched.
  • a second diffusion layer is formed in an upper portion of the fin-shaped semiconductor layer, a lower portion of the first columnar semiconductor layer, and a lower portion of the second columnar semiconductor layer, and the third dummy gate and the fourth
  • a fifth insulating film is formed around the dummy gate and etched to remain in a side wall shape, thereby forming a side wall derived from the fifth insulating film, on the second diffusion layer.
  • a fourth step of forming a compound layer comprising a metal and a semiconductor After the fourth step, a first interlayer insulating film is deposited and planarized, and the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are formed. Each upper part is exposed, the first dummy gate, the second dummy gate, the third dummy gate, and the fourth dummy gate are removed, and the second insulating film and the fourth insulating film are removed. And a gate insulating film is formed around the first columnar semiconductor layer, around the second columnar semiconductor layer, and inside the fifth insulating film, and the second columnar semiconductor is formed.
  • a fifth step of forming a gate electrode and a gate wire around the layers to form the contact electrode and the contact wires around the second columnar semiconductor layer The manufacturing process is included as a sixth process performed after the fifth process. It is preferable.
  • a third insulating film is formed on the first polysilicon.
  • a third resist is formed. It is preferable that an upper portion of the first columnar semiconductor layer is exposed by forming and etching back, and a first diffusion layer is formed on the upper portion of the first columnar semiconductor layer.
  • the present invention it is possible to provide a memory device and a method for manufacturing the same that can reduce the cross-sectional area of the film in which resistance changes and the current flowing through the lower electrode.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention, (b) is a sectional view taken along line XX ′ of (a), and (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention, (b) is a sectional view taken along line XX ′ of (a), and (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a plan view of a semiconductor device according to an embodiment of the present invention
  • (b) is a sectional view taken along line XX ′ of (a)
  • (c) is a YY line of (a). It is sectional drawing in a line.
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention,
  • (b) is sectional drawing in the XX 'line
  • (c) is It is sectional drawing in the YY 'line of (a).
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • (A) is a top view for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention, (b) is sectional drawing in the XX 'line
  • FIG. 1 shows a structure of a semiconductor device according to an embodiment of the present invention.
  • the memory cells of the present embodiment are arranged in one row and one column, one row and three columns, two rows and one column, and two rows and three columns, respectively, in a 3 ⁇ 2 matrix cell array.
  • Contact devices having contact electrodes and contact wirings for connecting source lines to each other are arranged in one row and two columns and two rows and two columns, respectively, in a 3 ⁇ 2 matrix cell array.
  • the memory cells located in two rows and one column include a fin-like silicon layer 104 formed so as to extend in the left-right direction on the semiconductor substrate 101, a first insulating film 106 formed around the fin-like silicon layer 104, The line width of the first columnar silicon layer 129 formed on the fin-like silicon layer 104 and the first columnar silicon layer 129 in the direction perpendicular to the fin-like silicon layer 104 is perpendicular to the fin-like silicon layer 104. Equal to the line width of the fin-like silicon layer 104 in the direction.
  • the memory cells located in two rows and one column are further formed around the first columnar silicon layer 129, the gate insulating film 162 formed around the first columnar silicon layer 129, and the gate insulating film 162.
  • the gate wiring 168 b extends in a direction orthogonal to the fin-like silicon layer 104.
  • the line width outside the gate electrode 168a is equal to the line width of the gate wiring 168b.
  • the memory cells located in two rows and one column are further formed in the first diffusion layer 302 formed above the first columnar silicon layer 129 and in the fin-shaped silicon layer 104 below the first columnar silicon layer 129.
  • the second diffusion layer 143 a formed, the columnar nitride film layer 180 made of a nitride film formed above the first diffusion layer 302, and the resistance formed around the top of the columnar nitride film layer 180 are changed.
  • a lower electrode 184 formed around the lower portion of the columnar nitride film layer 180 and connected to the film 189 having a variable resistance.
  • a lower electrode 184 is formed below the columnar nitride film layer 180.
  • the film 189 whose resistance is changed is preferably made of a phase change film such as chalcogenide glass (GST: Ge 2 Sb 2 Te 5 ).
  • the lower electrode 184 that is a heater element is preferably made of, for example, titanium nitride.
  • the memory cells located in two rows and three columns include a fin-like silicon layer 104 formed so as to extend in the left-right direction on the semiconductor substrate 101, and a first insulating film 106 formed around the fin-like silicon layer 104. And a first columnar silicon layer 131 formed on the fin-like silicon layer 104.
  • the line width of the first columnar silicon layer 131 in the direction perpendicular to the fin-like silicon layer 104 is equal to the line width of the fin-like silicon layer 104 in the direction perpendicular to the fin-like silicon layer 104.
  • the memory cells located in two rows and three columns further include a gate insulating film 163 formed around the first columnar silicon layer 131, and a gate electrode 170a made of metal formed around the gate insulating film 163. And a gate wiring 170b made of metal connected to the gate electrode 170a.
  • the gate insulating film 163 is formed around and under the gate electrode 170a and the gate wiring 170b.
  • the gate wiring 170b extends in a direction orthogonal to the fin-like silicon layer 104, and the line width outside the gate electrode 170a is equal to the line width of the gate wiring 170b.
  • the memory cells located in two rows and three columns are further provided with a first diffusion layer 304 formed above the first columnar silicon layer 131 and a fin-shaped silicon layer 104 below the first columnar silicon layer 131.
  • the formed second diffusion layer 143a, the columnar nitride film layer 181 made of a nitride film formed on the first diffusion layer 304, and the resistance formed on the periphery of the columnar nitride film layer 181 are changed.
  • a lower electrode 185 formed around the lower portion of the columnar nitride film layer 181 and connected to the film 190 having a variable resistance.
  • a lower electrode 185 is further formed below the columnar nitride film layer 181.
  • the film 189 whose resistance changes and the film 190 whose resistance changes are connected by a bit line 201.
  • the memory cells located in one row and one column include a fin-like silicon layer 105 formed on the semiconductor substrate 101 so as to extend in the left-right direction, a first insulating film 106 formed around the fin-like silicon layer 105, and a fin And a first columnar silicon layer 132 formed on the silicon layer 105.
  • the line width of the first columnar silicon layer 132 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the memory cells located in one row and one column further include a gate insulating film 162 formed around the first columnar silicon layer 132, a gate electrode 168a made of metal formed around the gate insulating film 162, and a gate.
  • the gate wiring 168b extends in a direction orthogonal to the fin-like silicon layer 105, and the line width outside the gate electrode 168a is equal to the line width of the gate wiring 168b.
  • the memory cells located in one row and one column are further formed under the first columnar silicon layer 132 in the fin-like silicon layer 105 and the first diffusion layer 305 formed on the first columnar silicon layer 132.
  • a lower electrode 186 is further formed below the columnar nitride film layer 182.
  • the memory cells located in one row and three columns include a fin-like silicon layer 105 formed on the semiconductor substrate 101 so as to extend in the left-right direction, a first insulating film 106 formed around the fin-like silicon layer 105, And a first columnar silicon layer 134 formed on the fin-shaped silicon layer 105.
  • the line width of the first columnar silicon layer 134 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the memory cells located in one row and three columns are further formed around the first columnar silicon layer 134, the gate insulating film 163 formed around the first columnar silicon layer 134, and the gate insulating film 163.
  • the gate wiring 170 b extends in a direction orthogonal to the fin-like silicon layer 105.
  • the line width outside the gate electrode 170a is equal to the line width of the gate wiring 170b.
  • the memory cells located in one row and three columns are further formed on the first columnar silicon layer 134 below the first columnar silicon layer 134 and the first diffusion layer 307 formed on the first columnar silicon layer 134.
  • a film 192 and a lower electrode 187 formed around the lower portion of the columnar nitride film layer 183 and connected to the film 192 having a variable resistance.
  • a lower electrode 187 is further formed below the columnar nitride film layer 183.
  • the film 191 whose resistance is changed and the film 192 whose resistance is changed are connected by a bit line 202.
  • a memory device is composed of lower electrodes 184, 185, 186, and 187 formed around the lower portion and connected to the films 189, 190, 191, and 192 having variable resistance.
  • the semiconductor device of this embodiment includes columnar nitride film layers 180, 181, 182, and 183 and films 189, 190, and 191 that are formed around the columnar nitride film layers 180, 181, 182, and 183 and have variable resistance.
  • the cross-sectional area in the direction in which each current flows between the phase change film made of the films 189, 190, 191 and 192 whose resistance changes and the heater element made of the lower electrodes 184, 185, 186 and 187 is reduced. can do.
  • the columnar nitride film layers 180, 181, 182, and 183 are nitride films, the cooling of the phase change film composed of the films 189, 190, 191, and 192 whose resistance changes can be accelerated.
  • the lower electrodes 184, 185, 186, and 187 are further formed below the columnar nitride film layers 180, 181, 182, and 183, so that the contact resistance between the lower electrodes 184, 185, 186, and 187 and the cell transistors is formed. Can be reduced.
  • SGT can pass a larger amount of current per unit gate width than a double gate transistor. Furthermore, since the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate width per unit area can be increased, so that a larger amount of current can flow. Therefore, since a large reset current can be passed, the phase change film made of the films 189, 190, 191 and 192 whose resistance changes can be melted at a high temperature (high current). Also, since the SGT sub-threshold swing can realize an ideal value, the off-current can be reduced, so that the phase change film composed of the films 189, 190, 191 and 192 whose resistance is changed is cooled at high speed (current). Can stop).
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b are made of metal, so that the cooling when heated can be accelerated.
  • the semiconductor device of this embodiment includes the gate electrodes 168a and 170a, and the gate insulating films 162 and 163 formed around and under the gate electrodes 168a and 170a and the gate wirings 168b and 170b, so that the heat treatment process is performed. Since the gate electrodes 168a and 170a, which are metal gates, are formed by the gate last forming the metal gate at the end of the step, both the metal gate process and the high temperature process can be achieved.
  • the semiconductor device of this embodiment includes gate electrodes 168a and 170a, and gate insulating films 162 and 163 formed around and under the gate electrodes 168a and 170a and the gate wirings 168b and 170b.
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b are made of metal, and the gate wirings 168b and 170b extend in a direction orthogonal to the fin-like silicon layers 104 and 105.
  • the second diffusion layers 143a and 143b are formed in the fin-like silicon layers 104 and 105, and the line width outside the gate electrodes 168a and 170a is equal to the line width of the gate wirings 168b and 170b.
  • the line widths of the first columnar silicon layers 129, 131, 132, and 134 are equal to the line widths of the fin-like silicon layers 104 and 105.
  • the fin-like silicon layers 104 and 105, the first columnar silicon layers 129, 131, 132, and 134, the gate electrodes 168a and 170a, and the gate wirings 168b and 170b are Since it is formed by self-alignment using two masks, the number of steps required for manufacturing a semiconductor device can be reduced.
  • the contact device located in two rows and two columns includes a fin-like silicon layer 104 formed so as to extend in the left-right direction on the semiconductor substrate 101, and a first insulating film 106 formed around the fin-like silicon layer 104. And the second columnar silicon layer 130 formed on the fin-like silicon layer 104.
  • the line width of the second columnar silicon layer 130 in the direction perpendicular to the fin-like silicon layer 104 is equal to the line width of the fin-like silicon layer 104 in the direction perpendicular to the fin-like silicon layer 104.
  • the contact device located in two rows and two columns further includes a metal contact electrode 169a formed around the second columnar silicon layer 130, and between the second columnar silicon layer 130 and the contact electrode 169a.
  • a metal contact electrode 169a formed around the second columnar silicon layer 130, and between the second columnar silicon layer 130 and the contact electrode 169a.
  • the contact wiring 169b made of metal and extending in the direction perpendicular to the fin-like silicon layer 104, connected to the contact electrode 169a, and the contact electrode 169a and the contact wiring 169b
  • the formed gate insulating film 164 and the second diffusion layer 143a formed in the fin-like silicon layer 104 below the second columnar silicon layer 130 are included.
  • the line width outside the contact electrode 169a is equal to the line width of the contact wiring 169b.
  • the contact electrode 169a is connected to the second diffusion layer 143a.
  • a contact device located in one row and two columns includes a fin-like silicon layer 105 formed on the semiconductor substrate 101, a first insulating film 106 formed around the fin-like silicon layer 105, and the fin-like silicon layer 105. And a second columnar silicon layer 133 formed on the substrate.
  • the line width of the second columnar silicon layer 133 in the direction perpendicular to the fin-like silicon layer 105 is equal to the line width of the fin-like silicon layer 105 in the direction perpendicular to the fin-like silicon layer 105.
  • the contact device located in one row and two columns is further formed between the contact electrode 169a made of metal and the second columnar silicon layer 133 and the contact electrode 169a formed around the second columnar silicon layer 133.
  • the contact wiring 169b made of metal and connected to the contact electrode 169a and extending in the direction perpendicular to the fin-like silicon layer 105, and the contact electrode 169a and the contact wiring 169b.
  • the second diffusion layer 143 b formed below the second columnar silicon layer 133 in the fin-like silicon layer 105.
  • the line width outside the contact electrode 169a is equal to the line width of the contact wiring 169b.
  • the contact electrode 169a is connected to the second diffusion layer 143b.
  • the contact wiring 169b extending in parallel with the gate wirings 168b and 170b connected to the second diffusion layers 143a and 143b is provided.
  • the second diffusion layers 143a and 143b are connected to each other, and the resistance of the source line can be lowered.
  • a large reset current can flow through the source line.
  • Such contact wirings 169b extending in parallel with the gate wirings 168b and 170b include, for example, the memory cells 2, 4, 8, 16, 32, and 64 arranged in a line along the direction in which the bit lines 187 and 188 extend. It is preferable to arrange one for each of the numbers.
  • the structure formed by the second columnar silicon layers 130 and 133 and the contact electrode 169a and the contact wiring 169b formed around the second columnar silicon layers 130 and 133 is a contact electrode. Except that 169a is electrically connected to the second diffusion layers 143a and 143b, it has the same structure as the transistor structure of the memory cell located in one row and one column. Further, all source lines including the second diffusion layers 143a and 143b extending in parallel with the gate wirings 168b and 170b are connected to the contact wiring 169b. Thereby, the number of processes required for manufacturing the semiconductor device can be reduced.
  • the second diffusion layer 143 c is formed to a deeper position of the semiconductor substrate 101 and is formed in the fin-like silicon layers 104 and 105 than the second diffusion layers 143 a and 143 b shown in FIG. 1.
  • the structure is similar to that of the second diffusion layers 143a and 143b shown in FIG. With such a structure, the source resistance can be further reduced.
  • the semiconductor device 3 does not include the fin-like silicon layer 105 shown in FIG. 2 and the first insulating film 106 formed around the fin-like silicon layer 105, and the second diffusion layer is directly formed on the semiconductor substrate 101.
  • the semiconductor device having a structure in which 143d is formed is shown. With such a structure, the source resistance can be further reduced.
  • the semiconductor substrate 101 is a silicon substrate, but may be a substrate made of other materials as long as it is a semiconductor.
  • first resists 102 and 103 for forming fin-like silicon layers 104 and 105 extending in the left-right direction are formed on a silicon substrate 101.
  • the silicon substrate 101 is etched to form the fin-like silicon layers 104 and 105.
  • the fin-like silicon layers 104 and 105 are formed using a resist as a mask, but a hard mask such as an oxide film or a nitride film may be used instead of the resist.
  • a first insulating film 106 is deposited around the fin-like silicon layers 104 and 105.
  • an oxide film formed by high-density plasma or an oxide film formed by low-pressure CVD (Chemical Vapor Deposition) can be used.
  • the first insulating film 106 is etched back to expose the upper portions of the fin-like silicon layers 104 and 105.
  • the first step of this embodiment in which the fin-like silicon layers 104 and 105 are formed on the semiconductor substrate 101 and the first insulating film 106 is formed around the fin-like silicon layers 104 and 105 is shown. .
  • the second step of the embodiment of the present invention will be described.
  • the second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105, and the first polysilicon 109 is formed on the second insulating films 107 and 108.
  • second resists 111 and 112 for forming gate wirings 168b and 170b, first columnar silicon layers 129, 131, 132, and 134, second columnar silicon layers 130 and 133, and contact wirings 169b, 113 is formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the first polysilicon 109, the second insulating films 107 and 108, and the fin-like silicon layers 104 and 105 are etched, thereby 1 columnar silicon layers 129, 131, 132, 134, first dummy gates 117, 119 derived from the first polysilicon 109, second columnar silicon layers 130, 133, and the first polysilicon 109 And a second dummy gate 118 derived from the above.
  • second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105 extending in the left-right direction on the semiconductor substrate 101.
  • the second insulating films 107 and 108 are preferably oxide films.
  • a first polysilicon 109 is deposited on the second insulating films 107 and 108 and planarized.
  • a third insulating film 110 is formed on the first polysilicon 109.
  • the third insulating film 110 is preferably a nitride film.
  • the gate wirings 168b, 170b, the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, and the contact wiring 169b for forming the first wirings are formed.
  • Two resists 111, 112, and 113 are formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the third insulating film 110 is separated into a plurality of portions, and third insulating films 114, 115, and 116 are formed on the first dummy gates 117 and 119 and the second dummy gate 118.
  • the second insulating films 107 and 108 are separated into a plurality of portions, and second insulating films 123, 124, 125, 126, 127, and 128 are formed.
  • the third insulating films 114, 115, and 116 function as a hard mask.
  • the second resists 114, 115, and 116 are removed.
  • the second insulating films 107 and 108 are formed around the fin-like silicon layers 104 and 105, and the first polysilicon 109 is deposited on the second insulating films 107 and 108. Flatten with.
  • second resists 111 and 112 for forming gate wirings 168b and 170b, first columnar silicon layers 129, 131, 132, and 134, second columnar silicon layers 130 and 133, and contact wirings 169b, 113 is formed so as to extend in a direction orthogonal to the direction in which the fin-like silicon layers 104 and 105 extend.
  • the first polysilicon 109, the second insulating films 107 and 108, and the fin-like silicon layers 104 and 105 are etched, thereby 1 columnar silicon layers 129, 131, 132, 134, first dummy gates 117, 119 derived from the first polysilicon 109, second columnar silicon layers 130, 133, and the first polysilicon 109
  • the second step of forming the second dummy gate 118 derived from the above is shown.
  • the third step of the embodiment of the present invention will be described.
  • the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, the first dummy gates 117, 119, and the second dummy gate A fourth insulating film 135 is formed around 118.
  • the second polysilicon 136 is deposited and etched around the fourth insulating film 135, and the first dummy gates 117 and 119, the first columnar silicon layers 129, 131, 132 and 134, The third dummy gates 137 and 139 and the fourth dummy gate 138 are formed by remaining on the side walls of the second dummy gate 118 and the second columnar silicon layers 130 and 133.
  • the first columnar silicon layers 129, 131, 132, 134, the second columnar silicon layers 130, 133, the first dummy gates 117, 119, and the second dummy gate 118 are formed.
  • a fourth insulating film 135 is formed around the periphery.
  • the fourth insulating film 135 is preferably an oxide film.
  • a third resist 301 is formed and etched back to expose the upper portions of the first columnar silicon layers 129, 131, 132, and 134. At this time, the upper portions of the second columnar silicon layers 130 and 133 may be exposed.
  • first diffusion layers 302, 304, 305, 307 are introduced to form first diffusion layers 302, 304, 305, 307 on top of the first columnar silicon layers 129, 131, 132, 134.
  • the first diffusion layers 303 and 306 may be formed on the second columnar silicon layers 130 and 133.
  • the introduced impurity is an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus.
  • the impurity to be introduced is a p-type diffusion layer, it is preferable to introduce boron.
  • the third resist 301 is removed.
  • a second polysilicon 136 is deposited around the fourth insulating film 135.
  • the second polysilicon 136 is etched to make the second polysilicon 136 the first dummy gates 117, 119 and the first columnar silicon layers 129, 131, 132. , 134, the second dummy gate 118, and the second columnar silicon layers 130, 133 are left on the sidewalls, thereby forming third dummy gates 137, 139 and a fourth dummy gate 138.
  • the fourth insulating film 135 may be separated into a plurality of portions, and the fourth insulating films 140, 141, 142 may be formed.
  • the first columnar silicon layers 129, 131, 132, and 134, the second columnar silicon layers 130 and 133, the first dummy gates 117 and 119, and the second dummy gate 118 are formed.
  • a fourth insulating film 135 is formed around the periphery.
  • a second polysilicon 136 is deposited and etched around the fourth insulating film 135, and the second polysilicon 136 is removed from the first dummy gates 117 and 119 and the first columnar silicon layer 129.
  • a third step of forming the gate 138 is shown.
  • the fourth step of the embodiment of the present invention will be described.
  • second diffusion layers 143a and 143b are formed.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138 and etched to remain in a sidewall shape, and the fifth insulating film 144 is left.
  • Side walls 145, 146, and 147 derived from the above are formed.
  • compound layers 148, 149, 150, 151, 152, 153, 154, and 155 made of a metal and a semiconductor are formed on the second diffusion layers 143a and 143b.
  • the second diffusion layer 143a is formed below the first columnar silicon layers 129, 131, 132, and 134 and below the second columnar silicon layers 130 and 133. , 143b.
  • the impurity to be introduced forms an n-type diffusion layer, it is preferable to introduce arsenic or phosphorus.
  • the impurity to be introduced forms a p-type diffusion layer, it is preferable to introduce boron.
  • Such a diffusion layer may be formed after forming sidewalls 145, 146, and 147 derived from a fifth insulating film 144 described later.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138.
  • the fifth insulating film 144 is preferably a nitride film.
  • the fifth insulating film 144 is etched to remain in a sidewall shape.
  • sidewalls 145, 146, and 147 are formed from the fifth insulating film 144.
  • compound layers 148, 149, 150, 151, 152, 153, 154, and 155 made of metal and semiconductor are formed on the second diffusion layers 143a and 143b.
  • compound layers 156, 158, and 157 made of metal and semiconductor are also formed on the upper portions of the third dummy gates 137 and 139 and the upper portion of the fourth dummy gate 138, respectively.
  • the second diffusion layer 143a the upper part of the fin-like silicon layers 104 and 105, the lower part of the first columnar silicon layers 129, 131, 132, and 134, and the lower part of the second columnar silicon layers 130 and 133, 143b is formed.
  • a fifth insulating film 144 is formed around the third dummy gates 137 and 139 and the fourth dummy gate 138 and etched to remain in a sidewall shape, so that the fifth insulating film
  • the fourth step is shown in which sidewalls 145, 146, and 147 derived from 144 are formed, and compound layers 156, 158, and 157 made of metal and semiconductor are formed on the second diffusion layers 143a and 143b.
  • the fifth step of the embodiment of the present invention will be described.
  • the first interlayer insulating film 159 is deposited and planarized, and the first dummy gates 117 and 119, the second dummy gate 118, and the third dummy gates 137 and 139 are formed.
  • the fourth dummy gate 138 are exposed, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed. To do.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed, and the gate insulating film 160 is replaced with the first columnar silicon layers 129, 131, It is formed around 132 and 134, around the second columnar silicon layers 130 and 133, and inside the fifth insulating film 144.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is formed, and the gate insulating film around the bottom of the second columnar silicon layers 130 and 133 is formed.
  • gate electrodes 168a and 170a and gate wirings 168b and 170b are formed around the first columnar silicon layers 129, 131, 132, and 134. Thereafter, contact electrodes 169 a and contact wirings 169 b are formed around the second columnar silicon layers 130 and 133.
  • a first interlayer insulating film 159 is deposited.
  • a contact stopper film may be used.
  • the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gates are performed.
  • the upper portions of the dummy gates 138 are exposed.
  • the compound layers 156, 158, and 157 made of metal and semiconductor, which are present above the third dummy gates 137 and 139 and the fourth dummy gate 138, are removed.
  • the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed.
  • the gate insulating film 160 is formed around the first columnar silicon layers 129, 131, 132, and 134, around the second columnar silicon layers 130 and 133, and the fifth insulating film.
  • 144 is formed inside the sidewalls 145, 146, 147 derived from 144.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottoms of the second columnar silicon layers 130 and 133 is formed.
  • the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is removed.
  • the gate insulating film 160 is separated into a plurality of portions, and gate insulating films 162, 163, 164, 165, 166 are formed.
  • the gate insulating films 164, 165, and 166 may be removed by isotropic etching.
  • a metal layer 167 is deposited.
  • the metal layers 167 are etched back to form gate electrodes 168a, 170a and gate wirings 168b, 170b around the first columnar silicon layers 129, 131, 132, 134. Then, the contact electrode 169a and the contact wiring 169b are formed around the second columnar silicon layers 130 and 133.
  • the first interlayer insulating film 159 is deposited and planarized, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and The upper portions of the fourth dummy gates 138 are exposed, and the first dummy gates 117 and 119, the second dummy gate 118, the third dummy gates 137 and 139, and the fourth dummy gate 138 are removed.
  • the second insulating films 123, 124, 125, 126, 127, 128 and the fourth insulating films 140, 141, 142 are removed, and the gate insulating film 160 is replaced with the first columnar silicon layers 129, 131, 132 and 134, around the second columnar silicon layers 130 and 133, and inside the sidewalls 145, 146 and 147 derived from the fifth insulating film 144.
  • a fourth resist 161 for removing the gate insulating film 160 around the bottom of the second columnar silicon layers 130 and 133 is formed, and the gate insulating film around the bottom of the second columnar silicon layers 130 and 133 is formed.
  • a second interlayer insulating film 171 is deposited to form contact holes 174, 175, 176, 177.
  • the second metal layer 178 and the nitride film 179 are deposited, and the second metal layer 178 and the nitride film 179 on the second interlayer insulating film 171 are removed, whereby the contact holes 174 and 175 are obtained.
  • the upper portions of the lower electrodes 184, 185, 186, and 187 surrounding the exposed columnar nitride film layers 180, 181, 182, and 183 are removed.
  • a film 188 having a variable resistance is deposited so as to surround the columnar nitride film layers 180, 181, 182, and 183 and to be connected to the lower electrodes 184, 185, 186, and 187.
  • the film 188 whose resistance is changed is etched, so that the film is left in a sidewall shape above the columnar nitride film layers 180, 181, 182, and 183.
  • a second interlayer insulating film 171 is deposited.
  • a fifth resist 172 for forming contact holes is formed.
  • contact holes 174, 175, 176, 177 are formed.
  • the second metal layer 178 is deposited.
  • the second metal layer 178 is preferably titanium nitride.
  • a nitride film 179 is deposited.
  • the nitride film 179 is etched back, and the nitride film 179 on the second interlayer insulating film 171 is removed. At this time, columnar nitride film layers 180, 181, 182 and 183 are formed.
  • the second metal 178 on the second interlayer insulating film 171 is removed.
  • lower electrodes 184, 185, 186, 187 surrounding the bottoms of the columnar nitride film layers 180, 181, 182, 183 and the periphery of the columnar nitride film layers 180, 181, 182, 183 are formed.
  • the second interlayer insulating film 171 is etched back to expose the upper portions of the lower electrodes 184, 185, 186, 187 surrounding the columnar nitride film layers 180, 181, 182, 183.
  • the second interlayer insulating film 171 is etched back to expose the upper portions of the lower electrodes 184, 185, 186, 187 surrounding the columnar nitride film layers 180, 181, 182, 183. Let If the upper portions of the lower electrodes 184, 185, 186, and 187 are already exposed after the step shown in FIG. 43, the step shown in FIG. 44 is unnecessary.
  • the film 188 whose resistance is changed is preferably made of a phase change film such as chalcogenide glass (GST: Ge 2 Sb 2 Te 5 ).
  • the film 188 with variable resistance is etched to remain in the form of sidewalls on top of the columnar nitride film layers 180, 181, 182, and 183.
  • the film 188 whose resistance is changed is separated into a plurality of portions, and films 189, 190, 191 and 192 whose resistance is changed are formed.
  • the film 188 whose resistance is changed may remain on the upper sidewalls of the lower electrodes 184, 185, 186 and 187 as films 193, 194, 195 and 196 whose resistance is changed.
  • the second interlayer insulating film 171 is deposited, and contact holes 174, 175, 176, 177 are formed.
  • the second metal layer 178 and the nitride film 179 are deposited, and the second metal layer 178 and the nitride film 179 on the second interlayer insulating film 171 are removed, whereby the contact holes 174 and 175 are obtained.
  • Lower electrodes 184, 185, 186, and 187 are formed.
  • the second interlayer insulating film 171 is etched back to expose the upper portions of the lower electrodes 184, 185, 186, 187 surrounding the columnar nitride film layers 180, 181, 182, 183.
  • the upper portions of the lower electrodes 184, 185, 186, and 187 surrounding the exposed columnar nitride film layers 180, 181, 182, and 183 are removed.
  • a film 188 having a variable resistance is deposited so as to surround the columnar nitride film layers 180, 181, 182, and 183 and to be connected to the lower electrodes 184, 185, 186, and 187.
  • a sixth step is shown in which the film 188 with variable resistance is etched to remain in a sidewall shape on the columnar nitride film layers 180, 181, 182, and 183.
  • the above-described structure is formed by one mask for forming the contact holes 174, 175, 176, and 177, so that the number of steps required for manufacturing the semiconductor device can be reduced.
  • a third interlayer insulating film 197 is deposited and planarized to expose the upper portions of the films 189, 190, 191, and 192 whose resistance changes.
  • a metal layer 198 is deposited.
  • sixth resists 199 and 200 for forming bit lines are formed.
  • bit lines 201 and 202 are formed by etching the metal layer 198.
  • the memory device includes films 189, 190, 191, and 192 that change around the first pillar-shaped silicon layers 129, 131, 132, and 134, the columnar nitride film layer 180, The lower electrodes 184, 185, 186, and 187 connected to the films 189, 190, 191, and 192 that change the resistance and are formed around the lower portions of the lower layers 181, 182, and 183 are included.
  • the cross-sectional area in the direction in which each current flows between the phase change film composed of the films 189, 190, 191 and 192 whose resistance changes and the heater element composed of the lower electrodes 184, 185, 186 and 187 is reduced. Can do.
  • the columnar nitride film layers 180, 181, 182, and 183 are made of a nitride film, so that the phase change film made of the films 189, 190, 191, and 192 whose resistance changes Cooling can be accelerated.
  • the lower electrodes 184, 185, 186, and 187 are further provided below the columnar nitride film layers 180, 181, 182, and 183, thereby reducing the contact resistance between the lower electrodes 184, 185, 186, and 187 and the cell transistors. be able to.
  • the SGT can pass a larger amount of current than the double gate transistor per unit gate width. Furthermore, since the SGT has a structure in which the gate electrode surrounds the columnar semiconductor layer, the gate width per unit area can be increased, so that a larger amount of current can flow. Therefore, since a large reset current can be passed, the phase change film made of the films 189, 190, 191 and 192 whose resistance changes can be melted at a high temperature (high current). Also, since the SGT sub-threshold swing can realize an ideal value, the off-current can be reduced, so that the phase change film composed of the films 189, 190, 191 and 192 whose resistance is changed is cooled at high speed (current). Can stop).
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b are metal, cooling when heated can be accelerated.
  • the gate electrodes 168a and 170a and the gate insulating films 162 and 163 formed around and under the gate electrodes 168a and 170a and the gate wirings 168b and 170b, a metal gate is formed at the end of the heat treatment step. Since the gate electrodes 168a and 170a, which are metal gates, are formed by the gate last, both the metal gate process and the high temperature process can be achieved.
  • the semiconductor device includes the fin-like silicon layers 104 and 105 formed on the semiconductor substrate 101, the first insulating film 106 formed around the fin-like silicon layers 104 and 105, and the fins.
  • gate electrodes 168a and 170a and gate insulating films 162 and 163 formed around and under the gate electrodes 168a and 170a and the gate wirings 168b and 170b are provided.
  • the gate electrodes 168a and 170a and the gate wirings 168b and 170b are metal, and the gate wirings 168b and 170b extend in a direction orthogonal to the fin-like silicon layers 104 and 105.
  • the second diffusion layers 143a and 143b are formed in the fin-like silicon layers 104 and 105, and the line width outside the gate electrodes 168a and 170a is equal to the line width of the gate wirings 168b and 170b.
  • the line widths of the first columnar silicon layers 129, 131, 132, and 134 are equal to the line widths of the fin-like silicon layers 104 and 105.
  • the fin-like silicon layers 104 and 105, the first columnar silicon layers 129, 131, 132, and 134, the gate electrodes 168a and 170a, and the gate wirings 168b and 170b are Since it is formed by self-alignment using two masks, the number of steps required for manufacturing a semiconductor device can be reduced.
  • the resistance of the source line is lowered by having the contact wiring 169b extending in parallel with the gate wirings 168b and 170b connected to the second diffusion layers 143a and 143b. Can do. As a result, a large reset current can flow through the source line.
  • Such contact wirings 169b extending in parallel with the gate wirings 168b and 170b include, for example, the memory cells 2, 4, 8, 16, 32, and 64 arranged in a line along the direction in which the bit lines 187 and 188 extend. It is preferable to arrange one for each of the numbers.
  • the second columnar silicon layers 130 and 133, and the contact electrodes 169a and the contact wirings 169b formed around the second columnar silicon layers 130 and 133 are formed.
  • the structure is the same as the transistor structure of the memory cells located in one row and one column except that the contact electrode 169a is electrically connected to the second diffusion layers 143a and 143b. Further, all source lines including the second diffusion layers 143a and 143b extending in parallel with the gate wirings 168b and 170b are connected to the contact wiring 169b. Thereby, the number of processes required for manufacturing the semiconductor device can be reduced.
  • Second columnar silicon layer 131 First columnar silicon layer 132. First columnar silicon layer 133. Second columnar silicon layer 134. First columnar silicon layer 135. Fourth insulating film 136. Second polysilicon 137. Third dummy gate 138. Fourth dummy gate 139. Third dummy gate 140. Fourth insulating film 141. Fourth insulating film 142. Fourth insulating film 143a. Second diffusion layer 143b. Second diffusion layer 143c. Second diffusion layer 143d. Second diffusion layer 144. Fifth insulating film 145. Side wall 146. Sidewall 147. Sidewall 148. Compound made of metal and semiconductor 149. Compound made of metal and semiconductor 150. Compound made of metal and semiconductor 151. Compound made of metal and semiconductor 152.

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Abstract

L'invention concerne un dispositif mémoire comprenant des films (189, 190, 191, 192) qui sont formés autour de sections supérieures de couches isolantes en colonnes (180, 181, 182, 183) et dont la résistance change, et des électrodes de fond (184, 185, 186, 187) qui sont formées autour des sections inférieures desdites couches isolantes en colonnes (180, 181, 182, 183) et qui sont connectées aux films (189, 190, 191, 192) dont la résistance change.
PCT/JP2013/077001 2013-10-03 2013-10-03 Dispositif de stockage et procédé de commande du dispositif de stockage Ceased WO2015049772A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599559A (zh) * 2019-09-17 2021-04-02 铠侠股份有限公司 半导体存储装置
CN112599558A (zh) * 2019-09-17 2021-04-02 铠侠股份有限公司 半导体存储装置

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Publication number Priority date Publication date Assignee Title
JP2010219325A (ja) * 2009-03-17 2010-09-30 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2012186424A (ja) * 2011-03-08 2012-09-27 Elpida Memory Inc 半導体装置の製造方法
JP2013016718A (ja) * 2011-07-06 2013-01-24 Elpida Memory Inc 半導体装置および半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010219325A (ja) * 2009-03-17 2010-09-30 Elpida Memory Inc 半導体記憶装置及びその製造方法
JP2012186424A (ja) * 2011-03-08 2012-09-27 Elpida Memory Inc 半導体装置の製造方法
JP2013016718A (ja) * 2011-07-06 2013-01-24 Elpida Memory Inc 半導体装置および半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112599559A (zh) * 2019-09-17 2021-04-02 铠侠股份有限公司 半导体存储装置
CN112599558A (zh) * 2019-09-17 2021-04-02 铠侠股份有限公司 半导体存储装置
CN112599558B (zh) * 2019-09-17 2024-03-19 铠侠股份有限公司 半导体存储装置

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