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WO2014119537A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2014119537A1
WO2014119537A1 PCT/JP2014/051753 JP2014051753W WO2014119537A1 WO 2014119537 A1 WO2014119537 A1 WO 2014119537A1 JP 2014051753 W JP2014051753 W JP 2014051753W WO 2014119537 A1 WO2014119537 A1 WO 2014119537A1
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WIPO (PCT)
Prior art keywords
insulating film
semiconductor device
semiconductor
wiring
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2014/051753
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English (en)
Japanese (ja)
Inventor
隆郎 安達
健治 前
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PS4 Luxco SARL
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PS4 Luxco SARL
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Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Publication of WO2014119537A1 publication Critical patent/WO2014119537A1/fr
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Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/74—Array wherein each memory cell has more than one access device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present invention is based on the priority claims of Japanese patent applications: Japanese Patent Application No. 2013-014454 (filed on January 29, 2013) and Japanese Patent Application No. 2013-014455 (filed on January 29, 2013), The entire contents of this application are incorporated herein by reference.
  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device as a semiconductor memory such as a resistance change type semiconductor memory (ReRAM), a layer change type semiconductor memory (PRAM), and a magnetic change type semiconductor memory (MRAM).
  • ReRAM resistance change type semiconductor memory
  • PRAM layer change type semiconductor memory
  • MRAM magnetic change type semiconductor memory
  • each memory cell has a word line and a memory cell provided at each intersection of the bit line and the word line, and each memory cell receives information based on a change in electric resistance and one selection transistor connected in series.
  • There are some which have one memory element to memorize for example, refer to patent documents 1).
  • the resistance rapidly increases due to the thinning of the width of the bit line with further miniaturization, the voltage drop in the bit line increases, and the applied voltage to the bit line increases.
  • the location dependence of the memory element electrically connected to the bit line becomes significant (the variation in the voltage drop is significant due to the difference in the distance from the peripheral circuit to the memory element).
  • a semiconductor device includes a common source line, a common bit line, and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which includes first and second controls.
  • a plurality of memory cells in which a selection element and a storage element each having an electrode are connected in series between the common source line and the common bit line; and a plurality of first selection lines, each of the plurality of memory cells
  • a plurality of first selection lines and a plurality of second selection lines commonly connected to the first control electrode of each memory cell belonging to a corresponding row of the rows, each of which is in the plurality of columns
  • a plurality of second selection lines connected in common to the second control electrodes of the memory cells belonging to the corresponding column.
  • a semiconductor device is a plurality of memory blocks, each of which is a common bit line and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, A plurality of memory cells in which a selection element and a storage element having first and second control electrodes are connected in series between the common bit line and a reference potential line, and a plurality of first selection lines, Are a plurality of first selection lines and a plurality of second selection lines commonly connected to the first control electrode of each memory cell belonging to the corresponding row of the plurality of rows, A plurality of memory blocks having a plurality of second selection lines connected in common to the second control electrode of each memory cell belonging to the corresponding column of the plurality of columns, the plurality of memory blocks being Multiple rows and multiple columns The plurality of first selection lines belonging to memory blocks arranged in a matrix and belonging to the same row are connected in common, and the plurality of second selection lines belonging to memory blocks arranged in the same column are respectively Commonly connected.
  • a plurality of semiconductor pillars arranged in a matrix of a plurality of rows and a plurality of columns and having a first region, a channel region, and a second region stacked in this order, A plurality of first wirings covering the channel region belonging to the same row among a plurality of semiconductor pillars via a first gate insulating film; and a plurality of first wirings disposed on different layers with respect to the plurality of first wirings, A plurality of second wirings covering the channel region belonging to the same column of the semiconductor pillars via a second gate insulating film, and disposed on the second region and electrically connected to the second region A plurality of memory elements, and the plurality of memory elements arranged on the plurality of memory elements and electrically in common with the plurality of memory elements in a predetermined range of a plurality of rows and a plurality of columns among the plurality of memory elements. And a conductor layer connected.
  • a semiconductor device is a plurality of semiconductor pillars, each of which includes a first and a second region, and a first and a second region configured in series between the first and second regions.
  • a plurality of semiconductor pillars having a second channel region, and a plurality of first wirings, each extending in a first direction and extending in the first direction of the plurality of semiconductor pillars;
  • a semiconductor device includes a conductor plate and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each having a first region and a second region in series between them.
  • a plurality of memory cells each including a semiconductor pillar having first and second channel regions provided on the semiconductor substrate, an information storage layer interposed between the first region and the conductor plate, and a plurality of first wirings.
  • a plurality of first channel layers formed extending in the row direction and covering the first channel layer belonging to the semiconductor pillars arranged in the row direction among the plurality of semiconductor pillars via the first gate insulating film.
  • a second channel layer that includes one wiring and a plurality of second wirings, each extending in the column direction and belonging to the semiconductor pillars arranged in the column direction among the plurality of semiconductor pillars; Via gate insulating film And a plurality of second wirings which covers Te.
  • the semiconductor substrate is arranged in a second direction extending in a first direction and intersecting the first direction at a predetermined interval.
  • the present invention it is possible to prevent the bit line width from being miniaturized due to the miniaturization of the wiring, and to reduce the resistance of the bit line.
  • FIG. 1 is a circuit diagram schematically showing a configuration of a memory cell in a semiconductor device according to Embodiment 1 of the present invention. It is the block diagram which showed typically the circuit structure of the semiconductor device which concerns on Embodiment 1 of this invention.
  • 1 is a circuit diagram schematically showing a configuration of a memory cell unit in a semiconductor device according to Embodiment 1 of the present invention.
  • 1 is a partial plan view schematically showing the configuration of a memory cell array and peripheral circuits in a semiconductor device according to Embodiment 1 of the present invention.
  • 1 is a perspective view schematically showing a partial configuration of a memory cell unit in a semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 6 is a circuit diagram schematically showing a configuration of a memory cell in a semiconductor device according to Embodiment 2 of the present invention. It is the partial circuit diagram which showed typically the structure of the memory cell unit in the semiconductor device which concerns on Embodiment 2 of this invention.
  • FIG. 6 is a partial cross-sectional view between XX ′ and YY ′ schematically showing the configuration of a memory cell array in a semiconductor device according to Embodiment 3 of the present invention.
  • 10 is a partial cross-sectional view between XX ′ and YY ′ schematically showing a method of manufacturing a memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 10 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 9 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 11 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 10 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 12 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 11 schematically showing the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 11 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 11 schematically showing the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 13 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 12 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 14 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 13 schematically showing the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 15 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 14 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 14 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 14 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 16 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 15 schematically showing the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 17 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 16 schematically illustrating the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 18 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 17 schematically illustrating the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 17 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 17 schematically illustrating the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 19 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 18 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 20 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 19 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • FIG. 6 is a circuit diagram schematically showing a configuration of a memory cell in a semiconductor device according to Embodiment 4 of the present invention. It is the partial circuit diagram which showed typically the structure of the memory cell unit in the semiconductor device which concerns on Embodiment 4 of this invention.
  • FIG. 6 is a circuit diagram schematically showing a configuration of a memory cell in a semiconductor device according to Embodiment 4 of the present invention. It is the partial circuit diagram which showed typically the structure of the memory cell unit in the semiconductor device which concerns on Embodi
  • FIG. 9 is a circuit diagram schematically showing a configuration of a memory cell in a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 10 is a partial circuit diagram schematically showing a configuration of a memory cell unit in a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 10 is a partial cross-sectional view between XX ′ and YY ′ schematically showing the configuration of a memory cell array in a semiconductor device according to Embodiment 6 of the present invention.
  • FIG. 16 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ schematically illustrating the method of manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 10 is a partial circuit diagram schematically showing a configuration of a memory cell unit in a semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 10 is a partial cross-sectional view between XX ′ and YY ′ schematic
  • FIG. 27 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 26 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 28 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 27 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 29 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 28 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 28 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 28 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 30 is a partial cross-sectional view taken along the line XX ′ and the line YY ′ following FIG. 29 schematically illustrating the method for manufacturing the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 33 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 32 schematically showing the configuration of the memory cell array in the semiconductor device according to Embodiment 7 of the present invention. It is the fragmentary top view which showed typically the structure of the memory cell array in the semiconductor device which concerns on Embodiment 7 of this invention.
  • FIG. 35 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 34 schematically showing the configuration of the memory cell array in the semiconductor device according to the comparative example.
  • FIG. 1 is a circuit diagram schematically showing the configuration of a memory cell in a semiconductor device according to Embodiment 1 of the present invention.
  • the semiconductor device is a semiconductor memory device (semiconductor memory) capable of storing information in a circuit configured by semiconductor elements.
  • the semiconductor device has a memory cell 2 as shown in FIG.
  • the memory cell 2 includes a storage element 5 connected in series and a selection element having two control electrodes.
  • the memory cell 2 includes two transistors as the selection element. That is, between the common source line 6 and the common bit line 7 (BL_k), the first selection transistor 3, the second selection transistor 4, and the storage element 5 are connected in series in this order from the common source line 6 side. It has a configuration.
  • the memory cells 2 are arranged in a matrix of a plurality of rows and a plurality of columns in the memory cell array (11 in FIG. 3).
  • the first selection transistor 3 is a transistor for selecting the corresponding storage element 5.
  • the first selection transistor 3 for example, a single gate type field effect transistor that controls the current between the source terminal and the drain terminal by applying a voltage to the gate electrode to generate an electric field in the channel can be used.
  • the first selection transistor 3 is electrically connected to a row word line 8 (RWL_m) as a first selection line at a gate electrode as a control electrode, and is electrically connected to a common source line 6 at a source terminal.
  • the drain terminal is electrically connected to the source terminal of the second selection transistor 4.
  • the first selection transistor 3 may be provided in parallel between the common source line 6 and the second selection transistor 4, and the parallel gate electrodes may be connected to the same row word line 8.
  • the second selection transistor 4 is a transistor for selecting the corresponding storage element 5.
  • the second selection transistor 4 for example, a single gate type field effect transistor can be used.
  • the second selection transistor 4 is electrically connected to the column word line 9 (CWL_n) as the second selection line at the gate electrode as the control electrode, and the drain terminal of the first selection transistor 3 at the source terminal. It is electrically connected and is electrically connected to the input terminal of the memory element 5 at the drain terminal.
  • the second selection transistor 4 may be provided in parallel between the first selection transistor 3 and the storage element 5, and the parallel gate electrodes may be connected to the same column word line 8.
  • the storage element 5 is an information storage body that stores 0 or 1 (High or Low) information.
  • a resistance change element that can change the resistance value of the resistance change film by applying a voltage to the resistance change film provided between the electrodes and flowing a current is provided between the electrodes.
  • a capacitor or the like that can change a charge accumulation amount in the capacitor insulating film by applying a voltage to the capacitor insulating film to flow a current can be used.
  • the storage element 5 is electrically connected to the drain terminal of the second selection transistor 4 at the input terminal, and is electrically connected to the common bit line 7 (BL_k) at the output terminal.
  • the memory element 5 is provided individually for each memory cell 2.
  • the memory element 5 is formed in a line shape in the row direction or the column direction. It is good also as a structure connected, and it is good also as a structure connected in plate shape in the row direction and the column direction.
  • the common source line 6 is a wiring for supplying a common reference potential to the memory cells 2.
  • the common source line 6 is electrically connected to a power supply circuit (not shown) that outputs a reference potential.
  • the common bit line 7 (BL_k) is a bit line that is electrically connected in common to the memory cells 2 (or all the memory cells 2 are possible) arranged in a matrix of at least a plurality of rows and a plurality of columns.
  • the common bit line 7 has a portion configured in a plate shape so as to collectively cover a plurality of memory cells 2 arranged in a matrix of at least a plurality of rows and a plurality of columns.
  • the common bit line 7 is electrically connected to a sense amplifier (18 in FIG. 2) and a write amplifier (17 in FIG. 2) via a multiplexer (19 in FIG. 2) (or directly).
  • the row word line 8 (RWL_m, m + 1) is a word line (selection line) for selecting each memory cell 2 belonging to the same row (row).
  • the row word line 8 is electrically connected in common with the gate electrode of the first selection transistor 3 of each memory cell 2 belonging to the same row.
  • the row word line 8 is electrically connected to a row selector (13 in FIG. 2), and one of RWL_m and m + 1 is selected by the row selector.
  • the column word line 9 (CWL_n, n + 1) is a word line (selection line) for selecting each memory cell 2 belonging to the same column (column).
  • the column word line 9 is electrically connected in common with the gate electrode of the second selection transistor 4 of each memory cell 2 belonging to the same column.
  • the column word line 9 is electrically connected to a column selector (20 in FIG. 2), and either CWL_n or n + 1 is selected by the column selector.
  • FIG. 2 is a block diagram schematically showing a circuit configuration of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a partial circuit diagram schematically showing the configuration of the memory cell array in the semiconductor device according to Embodiment 1 of the present invention.
  • the memory cell 2 as shown in FIG. 1 can be used in the circuit configuration of the semiconductor device 1 as shown in FIG.
  • the semiconductor device 1 includes a memory circuit and a peripheral circuit provided around the memory circuit.
  • the semiconductor device 1 includes, as a memory circuit, a memory cell array 11 divided into a plurality of Banks 0 to 1, a row decoder 12, a row selector 13, a column decoder 14, a data register 15, a determination circuit 16, a write circuit associated with each Bank 0 to 1.
  • An amplifier 17, a sense amplifier 18, a multiplexer 19, and a column selector 20 are included.
  • the semiconductor device 1 includes a row address buffer 21, an array control circuit 22, a phase counter 23, a control logic circuit 24, a command register 25, a status register 26, and a control signal input circuit 27 as peripheral circuits. , An input / output control circuit 28, an address register 29, a column address buffer 30, and a transistor 31.
  • two Banks 0 to 1 are provided, but the number of Banks is not particularly limited.
  • external power supply voltages VDD and VSS are externally supplied to the semiconductor device.
  • the memory cell array 11 is a circuit in which a plurality of memory cells 2 (MC) are arranged in a matrix of a plurality of rows and a plurality of columns (see FIG. 2).
  • the memory cell array 11 includes a column word line 9 (CWL_n), a row word line 8 (RWL_m), a memory cell 2 (MC), a common bit line 7 (BL_k), and a common source line 6.
  • the column word line 9 (CWL_n) extends in one direction and is arranged side by side in the other direction (a direction perpendicular to the one direction). Each column word line 9 (CWL_n) is electrically connected to the column selector 20.
  • the row word line 8 (RWL_m) extends in the other direction and is arranged in one direction.
  • Each row word line 8 (RWL_m) is electrically connected to the row selector 13.
  • the memory cell 2 (MC) is provided near each intersection of the column word line 9 (CWL_n) and the row word line 8 (RWL_m).
  • the memory cell 2 (MC) is electrically connected to the corresponding column word line 9 (CWL_n), row word line 8 (RWL_m), common bit line 7 (BL_k), and common source line 6.
  • the common bit line 7 (BL_k) is electrically connected in common to the memory cells 2 (MC) in a predetermined range of a plurality of rows and a plurality of columns.
  • Each common bit line 7 (BL_k) is electrically connected to the multiplexer 19.
  • the common source line 6 supplies a common reference potential to each memory cell 2 (MC). Details of the memory cell array 11 will be described later.
  • the row decoder 12 is a circuit for decoding signals from the array control circuit 22 and the row address buffer 21 (encoded row word line selection signal, row address).
  • the row decoder 12 outputs the decoded signal (row address) to the row selector 13.
  • the row selector 13 Based on the row address (corresponding to XA (m) and XA (m + 1) in FIG. 4) from the row decoder 12, the row selector 13 activates the row word line 8 (RWL_m) corresponding to the address, and the row word line 8 is a circuit for selecting a row address in the memory cell array 11 via 8 (RWL_m).
  • the column decoder 14 is a circuit that decodes signals from the array control circuit 22 and the column address buffer 30 (encoded column word line selection signal, column address). The column decoder 14 outputs the decoded signal (column address) to the column selector 20. The column decoder 14 outputs a signal (area address) for selecting the common bit line 7 corresponding to the column address to the multiplexer 19.
  • the data register 15 is a register that holds data.
  • the data register 15 exchanges data with the input / output control circuit 28.
  • the data register 15 holds data from the input / output control circuit 28 or the sense amplifier 18.
  • the data register 15 outputs the held data to the write amplifier 17 based on a signal from the array control circuit 22 at the time of writing.
  • the data register 15 outputs the held data to the input / output control circuit 28 based on a signal from the array control circuit 22 at the time of reading.
  • the determination circuit 16 is a circuit that determines whether a pass or a fail (verify operation) by comparing write data in the write amplifier 17 and read data in the sense amplifier 18 based on a signal from the array control circuit 22. is there. When the determination circuit 16 detects a failure, the determination circuit 16 performs rewriting to the memory cell array 11 and repeats the rewriting and reading loop until all the memory cells 2 (MC) pass.
  • the write amplifier 17 is a circuit that amplifies the potential of data from the data register 15 based on a signal from the array control circuit 22.
  • the write amplifier 17 outputs the potential amplified data to the memory cell array 11 via the multiplexer 19 and the selected common bit line 7 (BL_k).
  • the sense amplifier 18 amplifies the potential of data read from the memory cell array 11 via the selected common bit line 7 (BL_k) and the multiplexer 19 based on the signal from the array control circuit 22. It is. The sense amplifier 18 outputs the potential-amplified data to the data register 15 and the determination circuit 16.
  • the multiplexer 19 uses the area address (corresponding to YA2 (k), YA2 (k + 1) in FIG. 4) from the column decoder 14 and the area (block) address in the memory cell array 11 via the common bit line 7 (BL_k). Is a circuit for selecting. Each multiplexer 19 is electrically connected to the write amplifier 17 and the sense amplifier 18.
  • the column selector 20 activates the corresponding column word line 9 (CWL_n) based on the column address (corresponding to YA1 (n), YA1 (n + 1) in FIG. 4) from the column decoder 14, and the column word line 9
  • the row address buffer 21 is a buffer that holds a row address among the addresses from the address register 29.
  • the row address buffer 21 outputs the held row address to the row decoder 12.
  • the array control circuit 22 Based on signals from the control logic circuit 24 and the phase counter 23, the array control circuit 22 operates the row decoder 12, the column decoder 14, the data register 15, the determination circuit 16, the write amplifier 17, and the sense amplifier 18, respectively. Is a circuit for controlling The array control circuit 22 supplies a row word line selection signal to the row decoder 12, supplies a column word line selection signal to the column decoder 14, and supplies the data register 15, sense amplifier 18, write amplifier 17, and determination circuit 16. Various control signals are supplied.
  • the phase counter 23 is a counter for controlling the phase to be accessed.
  • the control logic circuit 24 is a logic circuit that outputs various control signals to peripheral circuits.
  • the control logic circuit 24 outputs various control signals to the array control circuit 22, the status register 26, and the transistor 31 based on signals from the control signal input circuit 27 and the command register 25.
  • the control logic circuit 24 exchanges signals with the array control circuit 22.
  • the command register 25 is a register that holds a command from the input / output control circuit 28.
  • the command register 25 outputs the held command toward the control logic circuit 24.
  • the status register 26 is a register that holds a status (signal) from the control logic circuit 24.
  • the status register 26 outputs the held status signal to the input / output control circuit 28.
  • the status is information indicating a state such as a write pass or a failure.
  • the control signal input circuit 27 is a circuit to which commands (chip enable / CE, command latch enable CLE, address latch enable ALE, write enable / WE, read enable / RE, / WP) are input.
  • / CE is a device selection signal. For example, when it is set to High in the read state, the standby mode is set.
  • CLE is a signal for controlling the command to be taken into the command register 25 inside the device.
  • CLE is a signal for controlling the command to be taken into the command register 25 inside the device.
  • ALE is a signal for controlling the address and data taken into the address register 29 and data register 15 inside the device.
  • ALE is a signal for controlling the address and data taken into the address register 29 and data register 15 inside the device.
  • data on the I / O terminals (I / O_0 to 7) is taken into the address register 29 as address data.
  • data on the I / O terminals (I / O_0 to 7) is taken into the data register 15 as input data.
  • / WE is a write signal for taking data from the IO terminals (I / O_0 to 7) into the device.
  • / RE is a signal for outputting data (serial output).
  • the input / output control circuit 28 is a circuit that controls input / output of commands, addresses, and data.
  • the input / output control circuit 28 exchanges commands, addresses, and data to the outside via the I / O terminals (I / O_0 to 7).
  • the input / output control circuit 28 outputs the input command to the command register 25.
  • the input / output control circuit 28 outputs the input address to the address register 29.
  • the input / output control circuit 28 exchanges data with the data register 15.
  • the input / output control circuit 28 controls input / output of commands, addresses, and data based on signals from the control signal input circuit 27 and the status register 26.
  • I / O_0 to 7 are terminals (ports) for inputting / outputting addresses, commands, and data.
  • the address register 29 is a register that holds an address from the input / output control circuit 28.
  • the address register 29 outputs the row address among the held addresses to the row address buffer 21.
  • the address register 29 outputs the column address among the held addresses to the column address buffer 30.
  • the column address buffer 30 is a buffer that holds a column address among the addresses from the address register 29.
  • the column address buffer 30 outputs the stored column address to the column decoder 14.
  • the transistor 31 is an nMOS transistor having an open drain configuration.
  • the gate electrode of the transistor 31 is electrically connected to the control logic circuit 24.
  • the source terminal of the transistor 31 is electrically connected to the ground.
  • the drain terminal of the transistor 31 is electrically connected to the output terminal of the internal state notification signal RY / BY.
  • the gate electrode of the transistor 31 is set to a high potential during an operation such as a program / erase / read operation.
  • RY / BY is a signal for notifying the outside of the internal state of the device.
  • FIG. 3 is a circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 4 is a partial plan view schematically showing the configuration of the memory cell array and peripheral circuits in the semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 5 is a perspective view schematically showing a partial configuration of the memory cell unit in the semiconductor device according to the first embodiment of the present invention.
  • the memory cell unit 11a shown in FIG. 3 is a part of the memory cell array (11 in FIG. 2), and 16 memory cells 2 (2 in FIG. 1) connected to one common bit line BL_0 (4 bits ⁇
  • BL_0 4 bits ⁇
  • the memory cell unit 11a has a plurality of row word lines 8 (RWL_0 to 3) extending in one direction and aligned in the other direction (perpendicular to one direction) and extending in the other direction and aligned in one direction.
  • a plurality of column word lines 9 (CWL_0 to 3), a plurality of memory cells 2 provided at intersections (or the vicinity thereof) of the row word lines 8 (RWL_0 to 3) and the column word lines 9 (CWL_0 to 3);
  • Common bit line 7 (BL_0) electrically connected in common to memory cell 2 (MC) in the range of 4 rows and 4 columns, and a common source for supplying a common reference potential to each memory cell 2 (MC) Line 6.
  • a memory cell array 11 having a planar configuration (16 bits ⁇ 16 bits configuration) as shown in FIG. 4 can be obtained.
  • the plurality of row word lines 8 belonging to the memory units 11a arranged in the same column are connected in common.
  • a plurality of column word lines 9 belonging to the memory units 11a arranged in the same row are connected in common.
  • a row selector 13a (RWL_m) for selecting an even number of row addresses is arranged on the right side
  • a row selector 13b (RWL_m + 1) for selecting an odd number of row addresses is arranged on the left side in FIG.
  • a column selector 20a (CWL_n) and a multiplexer 19a (BL_k) for selecting even numbers of column addresses and area addresses are arranged on the upper side, and a column selector 20b (CWL_n + 1) for selecting odd numbers of column addresses and area addresses is arranged on the lower side.
  • the row selector 13a (RWL_m) and the row selector 13b (RWL_m + 1) correspond to the row selector 13 in FIG.
  • the row selector 13a (RWL_m) is electrically connected to even-numbered RWL_0, 2, 4, 6, 8, 10, 12, and 14 among the plurality of row word lines 8 arranged in the other direction.
  • the row selector 13a (RWL_m) selects the corresponding row word line 8 when the even-numbered signal (XA (m)) of the row address from the row decoder 12 of FIG. 2 is input.
  • the row selector 13b (RWL_m + 1) is electrically connected to odd-numbered RWL_1, 3, 5, 7, 9, 11, 13, and 15 among the plurality of row word lines 8 arranged in the other direction.
  • the row selector 13b (RWL_m + 1) selects the corresponding row word line 8 when the odd-numbered signal (XA (m + 1)) of the row address from the row decoder 12 of FIG. 2 is input.
  • the column selector 20a (CWL_n) and the column selector 20b (CWL_n + 1) correspond to the column selector 20 in FIG.
  • the column selector 20a (CWL_n) is electrically connected to even-numbered CWL_0, 2, 4, 6, 8, 10, 12, and 14 among the plurality of column word lines 9 arranged in one direction.
  • the column selector 20a (CWL_n) selects the corresponding column word line 9 by receiving the even-numbered signal (YA1 (n)) of the column address from the column decoder 14 of FIG.
  • the column selector 20b (RWL_m + 1) is electrically connected to odd-numbered CWL_1, 3, 5, 7, 9, 11, 13, and 15 among the plurality of column word lines 9 arranged in one direction.
  • the column selector 20b (CWL_n + 1) selects the corresponding column word line 9 by receiving the odd-numbered signal (YA1 (n + 1)) of the column address from the column decoder 14 of FIG.
  • the multiplexer 19a (BL_k) and the multiplexer 19b (BL_k + 1) correspond to the multiplexer 19 in FIG.
  • the multiplexer 19a (BL_k) includes even-numbered BL_0, 2, 4, 6, 8, 10, 12, 14 in the common bit line plate portion 7a in which the region address is defined as shown in FIG. It is electrically connected via the line wiring part 7b.
  • the multiplexer 19a (BL_k) receives the even-numbered signal (YA2 (k)) of the area address from the column decoder 14 of FIG. 2, and selects the corresponding common bit line plate portion 7a.
  • the multiplexer 19b (BL_k + 1) includes the odd-numbered BL_1, 3, 5, 7, 9, 11, 13, 15 in the common bit line plate portion 7a in which the region address is defined as shown in FIG. It is electrically connected via the line wiring part 7b.
  • the multiplexer 19b (BL_k + 1) receives the odd-numbered signal (YA2 (k + 1)) of the area address from the column decoder 14 in FIG. 2, and selects the corresponding common bit line plate portion 7a.
  • the common bit line plate portion 7a and the common bit line wiring portion 7b correspond to the common bit line 7 in FIG.
  • the common bit line plate portion 7a is a plate-like portion that collectively covers the plurality of memory cells 2 in the memory cell unit 11a.
  • the common bit line wiring part 7b electrically connects the corresponding common bit line plate part 7a and the multiplexer 19a or 19b.
  • the common bit line plate portion 7a and the common bit line wiring portion 7b are connected to the write amplifier 17 and the sense amplifier 18 of FIG. 2 via the global bit line GBL.
  • the common bit line plate portions 7a belonging to the plurality of memory units 11a are independent from each other in FIG. 4, but may have a common configuration without using the multiplexers 19a and 19b.
  • a part of the memory cell unit 11a in FIG. 4 is shown three-dimensionally, it can be configured as shown in FIG.
  • a common bit line plate portion 7a is disposed on the common source line 6 with an interval therebetween, and the common source line is interposed between the common source line 6 and the common bit line plate portion 7a.
  • the first selection transistor 3, the second selection transistor 4, and the resistance change element 5a are connected in series.
  • the first selection transistor 3 and the second selection transistor 4 are arranged in a matrix in the row direction and the column direction.
  • the resistance change element 5a corresponds to the memory element 5 of FIG.
  • the common bit line plate portion 7a is connected to the common bit line wiring portion 7b.
  • the memory cell 2 at the intersection of the selected row address and column address is selected, and the common source line 6 and the common bit line 7 are selected in the selected memory cell 2.
  • Information can be stored depending on whether or not current flows between the two.
  • the common bit line 7 is commonly connected to each of the memory cells 2 in the plurality of memory cell units 11a, thereby preventing the bit line width from being reduced due to the finer wiring.
  • the resistance of the bit line can be reduced.
  • the memory element 5 is connected to the adjacent memory cell 2 such as a resistance change element in a line shape or a plate shape so as not to electrically contact the adjacent memory cell 2, thereby reducing etching damage to the memory element 5. This can lead to an improvement in yield.
  • FIG. 6 is a circuit diagram schematically showing the configuration of the memory cell in the semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to the second embodiment of the present invention.
  • the second embodiment is a modification of the first embodiment.
  • a selection element connected in series to the storage element 5 and having two control electrodes two single-gate first selection transistors 3 and a first selection transistor 3 as shown in FIG. Instead of connecting the two selection transistors 4 in series, one dual gate type selection transistor 33 is used.
  • the dual gate type selection transistor 33 is a field effect transistor having two gate electrodes 33a and 33b as control electrodes on a channel between a source terminal and a drain terminal (see FIG. 6).
  • the dual gate type select transistor 33 is electrically connected to the row word line 8 (RWL_m) at the gate electrode 33a, and electrically connected to the column word line 9 (CWL_n) at the gate electrode 33b.
  • the terminal is electrically connected to the common source line 6 and the drain terminal is electrically connected to the input terminal of the memory element 5.
  • the dual gate type selection transistor 33 is provided in parallel between the common source line 6 and the storage element 5, the parallel gate electrode 33 a is connected to the same row word line 8, and the parallel gate electrode 33 b is the same column word line 9. You may make it connect to.
  • the row word line 8 is electrically connected in common with the gate electrode 33a of the dual gate type selection transistor 33 of each memory cell 2 arranged in the row direction (see FIG. 7).
  • the column word line 9 is electrically connected in common with the gate electrode 33b of the dual gate type select transistor 33 of each memory cell 2 arranged in the column direction (see FIG. 7).
  • the same effect as that of the first embodiment can be obtained, and the structure of the memory cell can be simplified as compared with the first embodiment.
  • FIG. 8 is a partial cross-sectional view between XX ′ and YY ′ schematically showing the configuration of the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • the semiconductor device according to the third embodiment is an example of a structure equivalent to the circuit of the second embodiment.
  • the semiconductor device has an element isolation region 42 (for example, a silicon oxide film) in which an insulator or the like is embedded in a groove formed in a semiconductor substrate 41 (for example, a P-type silicon substrate).
  • a diffusion region 43 (for example, an N-type impurity diffusion region) having a predetermined depth is formed at a predetermined position on the semiconductor substrate 41.
  • the diffusion region 43 becomes a part of the common source line (corresponding to 6 in FIGS. 6 and 7).
  • a mask insulating film 44 (for example, a silicon nitride film) is formed at a predetermined position on the semiconductor substrate 41 including the semiconductor pillar 82 and the diffusion region 43.
  • a groove 45 having a predetermined depth extending in the column direction and arranged in the row direction is formed in the semiconductor substrate 41 including the diffusion region 43 and the mask insulating film 44.
  • a groove 48 having a predetermined depth extending in the row direction and arranged in the column direction is formed on the semiconductor substrate 41 including the diffusion region 43.
  • the groove 45 and the groove 48 intersect each other, and the planar shape in which the grooves 45 and 48 are combined is a net shape.
  • the groove 45 and the groove 48 have the same depth (including the same).
  • the part (mesh part) surrounded by the grooves 45 and 48 has a columnar semiconductor pillar 82 (P-type silicon) derived from the semiconductor substrate 41.
  • the semiconductor pillar 82 has a channel region 82a between the diffusion region 46 and the diffusion region 60 in the dual gate type selection transistor (corresponding to 33 in FIGS. 6 and 7).
  • the semiconductor pillars 82 are arranged in a matrix of a plurality of rows and a plurality of columns.
  • a diffusion region 46 for example, an N + type impurity diffusion region connected in layers is formed near the bottom of the grooves 45 and 48 or near the base of the semiconductor pillar 82.
  • the diffusion region 46 is disposed below the gate electrodes 51a, 51b, 51c.
  • the diffusion region 46 is connected to the diffusion region 43.
  • the diffusion region 46 becomes a source terminal of a dual gate type selection transistor (corresponding to 33 in FIGS. 6 and 7) and a part of a common source line (corresponding to 6 in FIGS. 6 and 7).
  • a diffusion region 60 (for example, an N + type impurity diffusion region) is formed on the semiconductor pillar 82.
  • the diffusion region 60 is disposed above the gate electrodes 56a, 56b, and 56c.
  • the diffusion region 60 is connected to the contact plug 61.
  • the diffusion region 60 serves as a drain terminal of a dual gate type selection transistor (corresponding to 33 in FIGS. 6 and 7).
  • an insulating film 47 for example, a silicon oxide film / silicon nitride film / silicon oxide film laminated film
  • an insulating film 54 for example, a silicon nitride film / silicon oxide film laminated film
  • Gate electrodes 56a, 56b, and 56c for example, titanium nitride
  • an insulating film 58 for example, a silicon nitride film / silicon oxide film stacked film
  • the gate electrodes 56a, 56b, and 56c are formed on the semiconductor pillars 82 on both sides of the wall surface of the groove 45 via the gate insulating film 55 (for example, silicon oxide film).
  • the gate insulating film 55 for example, silicon oxide film.
  • 56b, 56c are formed, and the gate electrodes 56a, 56b, 56c are separated into two, and an insulating film 57 (for example, silicon nitride film / silicon) is interposed between any two gate electrodes 56a, 56b, 56c.
  • a laminated film of oxide films is embedded.
  • the layer in which the gate electrodes 56a, 56b, and 56c are formed is arranged in a layer above the layer in which the gate electrodes 51a, 51b, and 51c are formed.
  • the gate electrodes 56 a and 56 b are gate electrodes arranged in the normal cell region 84 used as the normal memory cell 2.
  • the gate electrodes 56a and 56b serve as the second gate electrode (33b in FIGS. 6 and 7) of the dual gate type selection transistor (corresponding to 33 in FIGS. 6 and 7), and the column word line (9 in FIGS. 6 and 7). ).
  • the pair of gate electrodes 56a on both sides of the semiconductor pillar 82 become a common column word line and operate simultaneously.
  • a pair of gate electrodes 56b on both sides of another semiconductor pillar adjacent to the semiconductor pillar 82 also become a common column word line (different from the common column word line for the gate electrode 56a) and operate simultaneously.
  • the gate electrode 56 c is a gate electrode disposed in the dummy cell region 83 that is not used as the normal memory cell 2.
  • the gate electrodes 51a, 51b, 51c are formed, and the gate electrodes 51a, 51b, 51c are separated into two, and the insulating film 52 (for example, silicon nitride film / silicone) is interposed between any two gate electrodes of the gate electrodes 51a, 51b, 51c.
  • a laminated film of oxide films is embedded.
  • the layer in which the gate electrodes 51a, 51b, 51c are formed is arranged in a layer below the layer in which the gate electrodes 56a, 56b, 56c are formed.
  • the gate electrodes 51a, 51b, and 51c intersect with the gate electrodes 56a, 56b, and 56c in three dimensions.
  • the gate electrodes 51 a and 51 b are gate electrodes arranged in the normal cell region 84 used as the normal memory cell 2.
  • a contact plug 61 (for example, DOPOS, doped polysilicon) is embedded in a hole 59 that communicates with a diffusion region 60 in a region surrounded by insulating films 53 and 58.
  • a mask insulating film 62 (for example, a silicon nitride film) is formed in a predetermined region on the mask insulating film 44 including the insulating films 53 and 58.
  • a cover insulating film 63 (for example, a laminated film of silicon oxide film / silicon nitride film) is formed on the semiconductor substrate 41 including the mask insulating film 62, the mask insulating film 44, the diffusion region 43, and the element isolation region.
  • interlayer insulating films 64 and 65 (for example, a silicon oxide film and the interlayer insulating films 64 and 65 may be integrated) are formed.
  • a hole 66a communicating with the diffusion region 43 is formed in the interlayer insulating films 65 and 64 and the cover insulating film 63.
  • a contact plug 67a (for example, a titanium nitride / tungsten laminated film) is embedded in the hole 66a.
  • the contact plug 67a becomes a part of the common source line (corresponding to 6 in FIGS. 6 and 7).
  • the interlayer insulating films 65 and 64, the cover insulating film 63, and the insulating film 58 are formed with holes 66b that respectively communicate with the gate electrodes 56a and 56b.
  • a contact plug 67b (for example, a laminated film of titanium nitride / tungsten) is embedded.
  • a mask insulating film 68 (for example, a silicon nitride film) is formed on the interlayer insulating film 65.
  • a hole 69 that communicates with the contact plug 61 is formed in the mask insulating film 68, the interlayer insulating films 65 and 64, the cover insulating film 63, and the mask insulating film 62.
  • a contact plug 70 (for example, a titanium / titanium nitride multilayer film) is embedded in the hole 69.
  • the contact plug 70 serves as a lower electrode of the resistance change element 5a (memory element).
  • a resistance change film 71 for example, hafnium oxide
  • an upper electrode 72 for example, hafnium
  • a common bit line plate portion 73 for example, tungsten
  • a mask insulating film 74 for example, a silicon nitride film.
  • the common bit line plate portion 73 is a conductor layer formed in a planar shape (plate shape) so as to cover the contact plugs 70 in a predetermined range of a plurality of rows and a plurality of columns.
  • the common bit line plate portion 73 may be formed so as to cover all the contact plugs 70 in the memory cell array (corresponding to 11 in FIG.
  • a wiring 79a (for example, a tungsten nitride / tungsten multilayer film) and a mask insulating film 80 (for example, a silicon nitride film) are stacked in order from the bottom on a predetermined position on the interlayer insulating film 76 including the contact plug 78a.
  • the wiring 79a is a part of a common source line (corresponding to 6 in FIGS. 6 and 7).
  • a wiring 79b (for example, a laminated film of tungsten nitride / tungsten) and a mask insulating film 80 (for example, a silicon nitride film) are stacked in order from the bottom on a predetermined position on the interlayer insulating film 76 including the contact plug 78b. Has been.
  • the wiring 79b becomes a part of the column word line (9 in FIGS. 6 and 7).
  • a wiring 79c (for example, a tungsten nitride / tungsten laminated film) and a mask insulating film 80 (for example, a silicon nitride film) are stacked in order from the bottom on a predetermined position on the interlayer insulating film 76 including the contact plug 78c.
  • the wiring 79c becomes a part of the row word line (8 in FIGS. 6 and 7).
  • a wiring 79d (for example, a tungsten nitride / tungsten laminated film) and a mask insulating film 80 (for example, a silicon nitride film) are stacked in order from the bottom on a predetermined position on the interlayer insulating film 76 including the contact plug 78d.
  • the wiring 79d is a part of the common bit line (7 in FIGS. 6 and 7).
  • An interlayer insulating film 81 (for example, a silicon oxide film) is formed on the interlayer insulating film 76 between the wirings 79a, 79b, 79c, and 79d.
  • the pair of gate electrodes 51a (or 51b) to be the selected row word line and the pair of gate electrodes 56a (or 56b) to be the selected column word line are sandwiched. It is possible to select the memory cell 2 belonging to one semiconductor pillar 82 at the cross point.
  • the semiconductor substrate 41 P-type silicon
  • the inversion layer that can be used as a channel when both the gate electrodes are at the active level (high level) is substantially connected.
  • the gate type selection transistor is turned on.
  • 9 to 20 are partial cross-sectional views taken along the line XX ′ and the line YY ′ schematically illustrating the method of manufacturing the memory cell array in the semiconductor device according to the third embodiment of the present invention.
  • the mask insulating film 44 is patterned using a lithography technique and a dry etching technique, and then the semiconductor substrate 41 (including the diffusion region 43) is patterned using the mask insulating film 44 as a mask, thereby extending in the X direction. Grooves 45 that are present and arranged at a predetermined interval in the Y direction are formed (step A3; see FIG. 11).
  • a diffusion region 46 (for example, phosphorus ion diffusion region) is formed in the semiconductor substrate 41 around the bottom of the groove 45, and then an insulating film 47 (for example, silicon oxide film / silicon nitride film / silicon embedded in the groove 45). (Laminated oxide film) is formed (step A4; see FIG. 12).
  • the diffusion region 46 can be formed by ion implantation (for example, phosphorus ion implantation) into the semiconductor substrate 41 around the bottom of the groove 45 using the mask insulating film 44 as a mask, and then annealing at a predetermined temperature. it can.
  • the diffusion region 46 is formed so as to be connected in layers and to the diffusion region 43.
  • an insulating film 49 is formed below the trench 48, and then a row word line layer (a layer having the gate insulating film 50, gate electrodes 51a, 51b, 51c, and the insulating film 52) on the insulating film 49 in the trench 48. Then, an insulating film 53 is formed on the row word line layer in the trench 48 (step A6; see FIG. 14).
  • the insulating film 49 is formed by depositing an insulating film (for example, a laminated film of silicon nitride film / silicon oxide film) on the entire surface of the substrate (deposited so as not to fill the groove 48), and then the insulating film has a predetermined thickness. It can form in the lower part of the groove
  • an insulating film for example, a laminated film of silicon nitride film / silicon oxide film
  • the row word line layer can be formed as follows. First, a gate insulating film 50 (for example, a silicon oxide film) is formed on the wall surface of each semiconductor pillar 82 exposed from the trench 48 by thermal oxidation, and then a conductive film (for the gate electrodes 51a, 51b, 51c) is formed on the entire surface of the substrate. For example, titanium nitride) is deposited (deposited so as not to fill the groove 48), and then the conductive film is etched back to form sidewall-shaped gate electrodes 51a, 51b, 51c.
  • a gate insulating film 50 for example, a silicon oxide film
  • a conductive film for the gate electrodes 51a, 51b, 51c
  • An insulating film 52 (for example, a stacked film of silicon nitride film / silicon oxide film) is deposited (deposited so as not to fill the trench 48), and then the gate insulating film 50, the gate electrodes 51a, 51b, 51c, and the insulating film 52 are formed.
  • a low word line layer can be formed by dry etching until a predetermined thickness is reached.
  • the insulating film 53 is formed by depositing an insulating film (for example, a laminated film of silicon nitride film / silicon oxide film) on the entire surface of the substrate (depositing so as to fill the groove 48), and thereafter, until the mask insulating film 44 appears by CMP. It can be formed by polishing (planarizing) the insulating film.
  • an insulating film for example, a laminated film of silicon nitride film / silicon oxide film
  • the insulating film 47 (including the insulating film 53) in the trench 45 is removed to a predetermined thickness, thereby extending in the X direction and extending in the Y direction.
  • Grooves 45 having the insulating film 47 as the bottom surface are formed at predetermined intervals (step A7; see FIG. 15). Note that the depth of the groove 45 in step A7 is set not to be lower than the upper surfaces of the gate electrodes 51a, 51b, 51c.
  • an insulating film 54 is formed on the insulating film 47 (including the insulating film 53) in the trench 45, and then a column word line layer (gate insulating film 55, gate electrode 56a, 56b, 56c, a layer having an insulating film 57), and then an insulating film 58 is formed on the column word line layer in the groove 45 (step A8; see FIG. 16).
  • the contact plug 61 deposits a conductive film (for example, a DOPOS film (doped polysilicon film)) on the entire surface of the substrate (deposits so as to fill the hole 59), and thereafter, until the mask insulating film 44 appears by CMP. It can be formed by polishing (planarizing) the conductive film.
  • a conductive film for example, a DOPOS film (doped polysilicon film)
  • the hole 66a that communicates with the diffusion region 43, the hole 66b that communicates with the gate electrodes 56a and 56b, and the hole 66c that communicates with the gate electrodes 51a and 51b are formed using the technique and the dry etching technique, and then the holes 66a, 66b, and 66c are formed.
  • Contact plugs 67a, 67b, and 67c (for example, a titanium nitride / tungsten laminated film) are formed, and then a mask insulating film 68 (for example, a silicon nitride film) is formed on the interlayer insulating film 65 including the contact plugs 67a, 67b, and 67c.
  • the mask insulating film 68 is patterned using a lithography technique and a dry etching technique. Then, using the mask insulating film 68 as a mask, a hole 69 communicating with the contact plug 61 is formed, and then a contact plug 70 (for example, a titanium / titanium nitride laminated film) is formed in the hole 69 (step A10; (See FIG. 18). Note that the step of depositing the interlayer insulating film 65 can be omitted.
  • the hole 66a can be formed by etching the interlayer insulating films 65 and 64 and the cover insulating film 63 using a lithography technique and a dry etching technique.
  • the hole 66b can be formed by etching the interlayer insulating films 65 and 64, the cover insulating film 63, and the insulating film 58 using a lithography technique and a dry etching technique.
  • the hole 66c can be formed by etching the interlayer insulating films 65 and 64, the cover insulating film 63, and the insulating film 53 using a lithography technique and a dry etching technique.
  • the contact plugs 67a, 67b, and 67c are formed by depositing a conductive film (for example, a titanium nitride / tungsten laminated film) on the entire surface of the substrate (depositing so as to fill the holes 66a, 66b, and 66c), and thereafter performing interlayer bonding by CMP. It can be formed by polishing (planarizing) the conductive film until the insulating film 65 appears.
  • a conductive film for example, a titanium nitride / tungsten laminated film
  • the hole 69 can be formed by etching the mask insulating film 68, the interlayer insulating films 65 and 64, and the cover insulating film 63 using a lithography technique and a dry etching technique.
  • a hole 77a that communicates with the contact plug 67a, a hole 77b that communicates with the contact plug 67b, a hole 77c that communicates with the contact plug 67c, and a hole 77d that communicates with the common bit line plate portion 73 are formed.
  • contact plugs 78a, 78b, 78c, and 78d are formed in the holes 77a, 77b, 77c, and 77d, and then wirings 79a, 79b, 79c, and 79d are formed on the interlayer insulating film 76 including the contact plugs 78a, 78b, 78c, and 78d.
  • the conductive film is etched until the interlayer insulating film 76 appears to form wirings 79a, 79b, 79c, 79d, and then the mask insulating film 80, the wiring 79a,
  • An interlayer insulating film 81 (for example, a silicon oxide film) is deposited on the interlayer insulating film 76 including 79b, 79c, and 79d, and then the interlayer insulating film 81 is polished (planarized) by CMP (step A13; see FIG. 8). ).
  • CMP step A13; see FIG. 8
  • the holes 77a, 77b, and 77c can be formed by etching the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 68 using a lithography technique and a dry etching technique.
  • the hole 77d can be formed by etching the interlayer insulating film 76, the cover insulating film 75, and the mask insulating film 74 using a lithography technique and a dry etching technique.
  • the wirings 79a, 79b, 79c, and 79d are formed so as to be connected to the corresponding contact plugs 78a, 78b, 78c, and 78d.
  • the third embodiment it is possible to avoid etching the upper electrode 72 and the resistance change film 71 which are the constituent parts of the memory element, which has been etched at the same time as the bit line, with a minimum pitch. Etching damage to the side walls of the electrode 72 and the resistance change film 71 can be further reduced, leading to an improvement in yield.
  • FIG. 21 is a circuit diagram schematically showing the configuration of the memory cell in the semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 22 is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to Embodiment 4 of the present invention.
  • FIG. 21 as the fourth embodiment is a modification of the first embodiment, in which the first selection transistor 3 includes two transistors 3a and 3b connected in parallel, and the second selection transistor 4 is also connected in parallel. It consists of two transistors 4a and 4b.
  • the configuration of the four transistors is a story on an equivalent circuit.
  • the channel regions of the transistors 3a and 3b are formed in a common semiconductor layer.
  • the channel regions 4b are also formed in a common semiconductor layer. Accordingly, there are four gate electrodes in the selection element.
  • the gate electrodes of the transistors 3a and 3b in the memory cell 2 are connected to different row word lines 8a and 8b, respectively, and the gate electrodes of the transistors 4a and 4b are connected to different column word lines 9a and 9b, respectively.
  • the row word line 8a is electrically connected in common with the gate electrode of the first selection transistor 3a of each memory cell 2 belonging to the same row (see FIG. 22).
  • the row word line 8b is electrically connected in common with the gate electrode of the first selection transistor 3b of each memory cell 2 belonging to the same row (see FIG. 22).
  • the column word line 9a is electrically connected in common with the gate electrode of the second selection transistor 4a of each memory cell 2 belonging to the same column (see FIG. 22).
  • the column word line 9b is electrically connected in common with the gate electrode of the second selection transistor 4b of each memory cell 2 belonging to the same column (see FIG. 22).
  • Other configurations are the same as those of the first embodiment.
  • FIG. 23 is a circuit diagram schematically showing the configuration of the memory cell in the semiconductor device according to Embodiment 5 of the present invention.
  • FIG. 24 is a partial circuit diagram schematically showing the configuration of the memory cell unit in the semiconductor device according to Embodiment 5 of the present invention.
  • Embodiment 5 is a modification of Embodiment 2, in which two dual gate type selection transistors 34 and 35 are arranged in parallel. Even in such a configuration, in terms of the device structure, the channel regions of the dual gate type selection transistors 34 and 35 are formed in a common semiconductor layer.
  • the dual gate type selection transistor 34 is a field effect transistor in which two gate electrodes 34a and 34b are arranged in series on a channel between a source terminal and a drain terminal (see FIG. 23).
  • the dual gate selection transistor 34 is electrically connected to the row word line 8a (RWL_m) at the gate electrode 34a, and electrically connected to the column word line 9a (CWL_n) at the gate electrode 34b.
  • the terminal is electrically connected to the common source line 6 and the drain terminal is electrically connected to the input terminal of the memory element 5.
  • the dual gate type selection transistor 35 is a field effect transistor in which two gate electrodes 35a and 35b are arranged in series on a channel between a source terminal and a drain terminal (see FIG. 23).
  • the dual gate type selection transistor 35 is electrically connected to the row word line 8b (RWL_m + 1) at the gate electrode 35a, and is electrically connected to the column word line 9b (CWL_n + 1) at the gate electrode 35b.
  • the terminal is electrically connected to the common source line 6 and the drain terminal is electrically connected to the input terminal of the memory element 5.
  • the row word line 8a is electrically connected in common with the gate electrode 34a of the dual gate type selection transistor 34 of each memory cell 2 arranged in the row direction (see FIG. 24).
  • the row word line 8b is electrically connected in common with the gate electrode 35a of the dual gate type selection transistor 35 of each memory cell 2 arranged in the row direction (see FIG. 24).
  • the column word line 9a is electrically connected in common with the gate electrode 34b of the dual gate type select transistor 34 of each memory cell 2 arranged in the column direction (see FIG. 24). Further, the column word line 9b is electrically connected in common with the gate electrode 35b of the dual gate type selection transistor 35 of each memory cell 2 arranged in the column direction (see FIG. 24).
  • the same effects as those of the fourth embodiment can be obtained, and the structure of the memory cell can be simplified as compared with the fourth embodiment.
  • FIG. 25 is a partial cross-sectional view between XX ′ and YY ′ schematically showing the configuration of the memory cell array in the semiconductor device according to the sixth embodiment of the present invention.
  • Embodiment 6 is an example of a structure equivalent to the circuit of Embodiment 2.
  • the gate electrodes 51a, 51b, and 51c serving as the row word lines between the adjacent semiconductor pillars 82 are provided in the row word line layer and the column word line layer, as in the third embodiment (see FIG. 8).
  • the gate electrodes 56a, 56b, 56c serving as column word lines are not separated into two, and the gate electrodes 51a, 51b serving as row word lines between the adjacent semiconductor pillars 82 are separated.
  • the gate electrodes 51a and 51b adjacent to each other in the X direction of the semiconductor pillar 82 are not common. By selecting only the gate electrode on one side, the semiconductor pillar 82 to be selected is not selected, and the gate electrodes on both sides are selected. The semiconductor pillar 82 to be selected is selected. The gate electrodes 56a and 56b adjacent to each other in the Y direction of the semiconductor pillar 82 are not common, and the semiconductor pillar 82 to be selected is not selected only by selecting only one of the gate electrodes, but by selecting the gate electrodes on both sides. The semiconductor pillar 82 to be selected is selected. That is, only the memory cell 2 belonging to the semiconductor pillar 82 in the region (cross point) surrounded by the four selected gate electrodes 51a, 51b, 56a, and 56b is selected.
  • the semiconductor substrate 41 P-type silicon
  • the semiconductor substrate 41 P-type silicon
  • the semiconductor substrate 41 P-type silicon
  • the channel is formed when both gate electrodes are at the active level (high level).
  • the inversion layers that can be formed are substantially connected, and the dual gate type selection transistor is turned on.
  • the dual gate type selection transistor 33 is described as an example. However, a diffusion region is formed in the semiconductor pillar 82 between the gate electrodes 51a and 51b and the gate electrodes 56a and 56b (diffusion region). 2), two single-gate selection transistors can be arranged in series (corresponding to the fourth embodiment).
  • a substrate having the same configuration as that of FIG. 13 is manufactured by the same process as Step A1 (see FIG. 9) to Step A5 (see FIG. 13) of Embodiment 3 (Step B1).
  • an insulating film 49 is formed below the trench 48, and then a row word line layer (a layer having the gate insulating film 50, gate electrodes 51a, 51b, 51c, and the insulating film 52) on the insulating film 49 in the trench 48. Then, an insulating film 53 is formed on the row word line layer in the trench 48 (step B2; see FIG. 26).
  • the gate electrodes 51a, 51b, 51c are not separated into two as shown in FIG. 14, but are formed as one gate electrode 51a, 51b, 51c.
  • the insulating film 49 and the insulating film 53 can be formed by the same method as in Step A6 (see FIG. 14) of the third embodiment.
  • the row word line layer can be formed as follows. First, a gate insulating film 50 (for example, a silicon oxide film) is formed on the wall surface of each semiconductor pillar 82 exposed from the trench 48 by thermal oxidation, and then a conductive film (for the gate electrodes 51a, 51b, 51c) is formed on the entire surface of the substrate.
  • a gate insulating film 50 for example, a silicon oxide film
  • a conductive film for the gate electrodes 51a, 51b, 51c
  • titanium nitride is deposited (deposited to the extent that the groove 48 is not filled), and then an insulating film 52 (for example, a silicon nitride film / silicon oxide film laminated film) is deposited over the entire surface of the substrate (to the extent that the groove 48 is not filled). Then, dry etching is performed until the gate insulating film 50, the conductive film, and the insulating film 52 have a predetermined thickness, so that any one of the gate electrodes 51a, 51b, and 51c is formed in each groove 48.
  • the formed row word line layer can be formed.
  • the insulating film 47 (including the insulating film 53) in the trench 45 is removed to a predetermined thickness, thereby extending in the X direction and extending in the Y direction.
  • Grooves 45 with the insulating film 47 serving as the bottom surface are formed at predetermined intervals (step B3; see FIG. 27). Note that the depth of the groove 45 in step B3 is set not to be lower than the upper surfaces of the gate electrodes 51a, 51b, and 51c.
  • an insulating film 54 is formed on the insulating film 47 (including the insulating film 53) in the trench 45, and then a column word line layer (gate insulating film 55, gate electrode 56a, 56b, 56c, a layer having an insulating film 57), and then an insulating film 58 is formed on the column word line layer in the groove 45 (step B4; see FIG. 28).
  • the insulating film 54 and the insulating film 58 can be formed by the same method as in step A6 (see FIG. 14) of the third embodiment.
  • the column word line layer (the layer having the gate insulating film 55, the gate electrodes 56a, 56b and 56c, and the insulating film 57) can be formed as follows. First, a gate insulating film 55 (for example, a silicon oxide film) is formed on the wall surface of each semiconductor pillar 82 exposed from the trench 45 by thermal oxidation, and then a conductive film (for the gate electrodes 56a, 56b, and 56c) is formed on the entire surface of the substrate.
  • a gate insulating film 55 for example, a silicon oxide film
  • the mask insulating film 44 on the semiconductor pillar 82 in the normal cell region 84 is removed to form a hole 59 that communicates with the semiconductor pillar 82.
  • a diffusion region 60 is formed in the upper portion, and then a contact plug 61 embedded in the hole 59 is formed (step B5; see FIG. 29).
  • the diffusion region 60 and the contact plug 61 can be formed by the same method as in Step A9 (see FIG. 17) of the third embodiment.
  • a mask insulating film 62 (for example, a silicon nitride film) is deposited on the mask insulating film 44 including the mask insulating film 44, the insulating film 53, and the contact plug 61, and then a lithography technique and a dry etching technique are used. Then, a part of the mask insulating film 62 is removed until the mask insulating film 44 appears, and then the mask insulating film is used until the semiconductor substrate 41, the element isolation region 42, and the diffusion region 43 appear using the lithography technique and the dry etching technique.
  • a mask insulating film 62 for example, a silicon nitride film
  • the cover insulating film 63 (for example, on the semiconductor substrate 41, the element isolation region 42, the diffusion region 43, the mask insulating film 44, and the mask insulating film 62) is removed.
  • a silicon oxide film / silicon nitride film is deposited, and then an interlayer insulating film 64 (for example, silicon film) is formed on the cover insulating film 63.
  • the interlayer insulating film 64 is polished (planarized) by CMP, and then an interlayer insulating film 65 (for example, a silicon oxide film) is deposited on the interlayer insulating film 64, followed by lithography.
  • the mask insulating film 68 is patterned using a lithography technique and a dry etching technique. Then, using the mask insulating film 68 as a mask, a hole 69 communicating with the contact plug 61 is formed, and then a contact plug 70 (for example, a titanium / titanium nitride laminated film) is formed in the hole 69 (step B6; (See FIG. 30). Note that the step of depositing the interlayer insulating film 65 can be omitted.
  • the holes 66a, 66b, and 66c can be formed by the same method as in Step A10 (see FIG. 18) of the third embodiment.
  • the holes 66b and 66c are respectively per one groove 45 and 48. This is different from the third embodiment in which two holes 66b and 66c are formed per groove 45 and 48 in that one hole 66b and 66c is formed.
  • the same effects as those of the fifth embodiment can be achieved, and the manufacturing method of the third embodiment can be simplified.
  • FIG. 31 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 32 schematically showing the configuration of the memory cell array in the semiconductor device according to the seventh embodiment of the present invention.
  • FIG. 32 is a partial plan view schematically showing the configuration of the memory cell array in the semiconductor device according to Embodiment 7 of the present invention.
  • FIG. 33 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 34 schematically showing the configuration of the memory cell array in the semiconductor device according to the comparative example.
  • FIG. 31 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 32 schematically showing the configuration of the memory cell array in the semiconductor device according to the seventh embodiment of the present invention.
  • FIG. 32 is a partial plan view schematically showing the configuration of the memory cell array in the semiconductor device according to Embodiment 7 of the present invention.
  • FIG. 33 is a partial cross-sectional view taken along the line ZZ ′ of FIG. 34 schematically showing the configuration of the memory cell
  • FIG. 34 is a partial plan view schematically showing the configuration of the memory cell array in the semiconductor device according to the comparative example.
  • FIG. 35 is a diagram comparing the forming voltage at the resistance change film in the semiconductor device according to the seventh embodiment of the present invention with that in the comparative example.
  • the seventh embodiment is a modification of the third embodiment, and the contact plug 78d connected to the common bit line plate portion 73 is positioned at the position of the contact plug 70 connected to the resistance change film 71 (the same position as the semiconductor pillar 82). (See FIGS. 31 and 32). A plurality of contact plugs 78 d may be connected to one common bit line plate portion 73. Other configurations are the same as those of the third embodiment (see FIG. 8). The seventh embodiment may be applied in the sixth embodiment (see FIG. 25).
  • a contact plug 78d connected to the common bit line plate portion 73 is formed immediately above the contact plug 70 connected to the resistance change film 71 (at the same position as the semiconductor pillar 82).
  • the configuration is used (see FIGS. 33 and 34).
  • the contact plug 78d connected to the common bit line plate portion 73 is used.
  • the position of is not directly above the contact plug 70 (the same position as the semiconductor pillar 82), the breakdown voltage (forming voltage) of the memory element (resistance change element; contact plug 70, resistance change film 51, upper electrode 72) is reduced. (See FIG. 35).
  • the storage element resistance change element; contact plug 70
  • the contact plug 78d connected to the common bit line plate portion 73 in the dummy cell region is directly above the contact plug 70 (at the same position as the semiconductor pillar 82). It does not matter if it is formed.
  • a semiconductor device includes a common source line, a common bit line, and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each of which includes first and second controls.
  • the selection element includes first and second transistors connected in series, and the first and second control electrodes are connected to gates of the first and second transistors, respectively. It is preferable that
  • the selection element further includes third and fourth control electrodes, a first parallel connection of the first and second transistors, and a second parallel connection of the third and fourth transistors.
  • the first and second parallel connection bodies are connected in series, the first and third control electrodes are connected to the gates of the first and second transistors, respectively, and the second and fourth control electrodes are Connected to the third and fourth transistors, respectively, the third control electrode is connected to the first electrode of an adjacent memory cell, and the fourth control electrode is connected to the second electrode of the adjacent memory cell.
  • the third control electrode is connected to the first electrode of an adjacent memory cell, and the fourth control electrode is connected to the second electrode of the adjacent memory cell.
  • it is.
  • the memory element includes third and fourth control electrodes, and first and second dual gate transistors connected in parallel, and the first and second control electrodes are the first and second control electrodes. And the third and fourth control electrodes are respectively connected to the two gates of the second dual gate transistor, and the third control electrode is connected to the second gate of the adjacent memory cell.
  • the fourth control electrode is connected to one electrode, and the fourth control electrode is connected to the second electrode of an adjacent memory cell.
  • the plurality of common bit lines in the plurality of memory blocks are independent of each other.
  • the semiconductor device further includes a multiplexer connected to the plurality of common bit lines, and the multiplexer selects one of the plurality of common bit lines.
  • the semiconductor device of the present invention further includes a global bit line, and the multiplexer electrically connects the selected common bit line to the global bit line.
  • a plurality of semiconductor pillars arranged in a matrix of a plurality of rows and a plurality of columns and having a first region, a channel region, and a second region stacked in this order, A plurality of first wirings covering the channel region belonging to the same row among a plurality of semiconductor pillars via a first gate insulating film; and a plurality of first wirings disposed on different layers with respect to the plurality of first wirings, A plurality of second wirings covering the channel region belonging to the same column of the semiconductor pillars via a second gate insulating film, and disposed on the second region and electrically connected to the second region A plurality of memory elements, and the plurality of memory elements arranged on the plurality of memory elements and electrically in common with the plurality of memory elements in a predetermined range of a plurality of rows and a plurality of columns among the plurality of memory elements. And a conductor layer connected.
  • the conductor layer is formed in a plate shape so as to cover the plurality of memory elements in a predetermined range of a plurality of rows and columns among the plurality of memory elements. It is preferable.
  • the memory element is a resistance change element in which a lower electrode, a resistance change film, and an upper electrode are stacked in order from the second region side, and the resistance change element is within the predetermined range.
  • the resistance change film and the upper electrode are preferably connected in common and formed in a plate shape.
  • the lower electrodes of the variable resistance element within the predetermined range are independent from each other.
  • the first wiring is divided into two parts between the adjacent semiconductor pillars, and each of the first wirings is controlled separately, and the second wiring is provided between the adjacent semiconductor pillars. It is divided into two, and it is preferable that each is controlled separately.
  • the pair of first wirings arranged on both sides of the semiconductor pillar are controlled simultaneously, and the pair of second wirings arranged on both sides of the semiconductor pillar are Are preferably controlled simultaneously.
  • a semiconductor device is a plurality of semiconductor pillars, each of which includes a first and a second region, and a first and a second region configured in series between the first and second regions.
  • a plurality of semiconductor pillars having a second channel region, and a plurality of first wirings, each extending in a first direction and extending in the first direction of the plurality of semiconductor pillars;
  • a semiconductor device includes a conductor plate and a plurality of memory cells arranged in a plurality of rows and a plurality of columns, each having a first region and a second region in series between them.
  • a plurality of memory cells each including a semiconductor pillar having first and second channel regions provided on the semiconductor substrate, an information storage layer interposed between the first region and the conductor plate, and a plurality of first wirings.
  • a plurality of first channel layers formed extending in the row direction and covering the first channel layer belonging to the semiconductor pillars arranged in the row direction among the plurality of semiconductor pillars via the first gate insulating film.
  • the semiconductor substrate is arranged in a second direction extending in a first direction and intersecting the first direction at a predetermined interval.
  • the method for manufacturing a semiconductor device includes the step of forming a fourth region having a predetermined depth in a predetermined region of the semiconductor substrate before the step of forming the first groove, In the step of forming the first region, the first region is preferably formed so as to be connected to the second region.
  • a second insulating film is formed below the second groove, and then the second insulating film in the second groove.
  • the first gate insulating film, the first wiring, and the third insulating film are formed on the first gate insulating film, and then the first gate insulating film, the first wiring, and the third insulating film in the second trench are formed on the first insulating film. It is preferable to form four insulating films.
  • the first gate insulating film, the first wiring, and the third insulating film are formed in the second groove.
  • the third insulating film is deposited on the insulating film, and then the first gate insulating film, the first wiring, and the upper portion of the third insulating film in the second trench are removed.
  • a part of the first insulating film in the first trench is removed, and then the first trench in the first trench is formed.
  • a seventh insulating film is formed on the second gate insulating film, the second wiring, and the sixth insulating film in the first trench.
  • an eighth insulating film is formed on the second region, and then the second insulating film is electrically connected to the second region. It is preferable to form a lower electrode connected to the first electrode, and then deposit a resistance change film on the eighth insulating film including the lower electrode, and then deposit an upper electrode on the resistance change film.
  • the conductor layer is deposited on the upper electrode, and then the conductor layer, the upper electrode, and the resistance change film. It is preferable to remove a part of.
  • the step of forming the conductor layer includes a step of forming a contact plug on the conductor layer so as not to overlap the region of the semiconductor pillar.

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Abstract

Selon la présente invention, une diminution de la largeur d'une ligne de bits provoque l'augmentation brusque d'une résistance. Le dispositif à semi-conducteur selon la présente invention est pourvu : d'une ligne de source commune; d'une ligne de bits commune; de cellules de mémoire multiples qui sont agencées en rangées multiples et en colonnes multiples, chacune desdites cellules de mémoire multiples étant conçue par connexion en série d'un composant de sélection comportant des première et seconde électrodes de commande et d'un composant de mémoire entre la ligne de source commune et la ligne de bits commune; de multiples premières lignes de sélection, chacune desdites multiples premières lignes de sélection étant connectée en commun à la première électrode de commande d'une cellule de mémoire respective appartenant à une rangée correspondante parmi les rangées multiples; et de multiples secondes lignes de sélection, chacune desdites multiples secondes lignes de sélection étant connectée en commun à la seconde électrode de commande d'une cellule de mémoire respective appartenant à une colonne correspondante parmi les colonnes multiples.
PCT/JP2014/051753 2013-01-29 2014-01-28 Dispositif à semi-conducteur et son procédé de fabrication Ceased WO2014119537A1 (fr)

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