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WO2014024266A1 - Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur - Google Patents

Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur Download PDF

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Publication number
WO2014024266A1
WO2014024266A1 PCT/JP2012/070145 JP2012070145W WO2014024266A1 WO 2014024266 A1 WO2014024266 A1 WO 2014024266A1 JP 2012070145 W JP2012070145 W JP 2012070145W WO 2014024266 A1 WO2014024266 A1 WO 2014024266A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon layer
fin
resist
forming
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/070145
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English (en)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Priority to JP2014508629A priority Critical patent/JP5595619B2/ja
Priority to PCT/JP2012/070145 priority patent/WO2014024266A1/fr
Priority to TW102128020A priority patent/TW201407788A/zh
Publication of WO2014024266A1 publication Critical patent/WO2014024266A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025—Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • a thick gate material when the distance between the silicon pillars becomes narrow, a thick gate material must be deposited between the silicon pillars, and a hole called a void may be formed between the silicon pillars. Once the void is formed, a hole is made in the gate material after etch back. Thereafter, when an insulating film is deposited to form an insulating film sidewall, the insulating film is deposited in the void. Therefore, it is difficult to process the gate material.
  • a gate oxide film is formed, and after depositing thin polysilicon, a resist for covering the upper part of the silicon pillar and forming a gate wiring is formed, the gate wiring is etched, and then the oxide film is thickened. It has been shown that the upper part of the silicon pillar is deposited, the thin polysilicon on the upper part of the silicon pillar is removed, and the thick oxide film is removed by wet etching (see Non-Patent Document 1, for example).
  • a resist for forming the gate wiring must be formed so as to cover the upper part of the silicon pillar, and therefore, the upper part of the silicon pillar must be covered, which is not a self-alignment process.
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A
  • an object of the present invention is to provide a method for manufacturing SGT that is a self-aligned process using a thin gate material, a metal gate, and a self-aligned process, and a SGT structure obtained as a result, by reducing the parasitic capacitance between the gate wiring and the substrate. .
  • a method for manufacturing a semiconductor device of the present invention includes: Forming a fin-like silicon layer on a silicon substrate, forming a first insulating film around the fin-like silicon layer, and forming a columnar silicon layer on the fin-like silicon layer; and The diameter of the columnar silicon layer is the same as the width of the fin-shaped silicon layer, After the first step, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and a third wiring for forming a gate wiring is formed.
  • the method may further include a fifth step of forming silicide on the first diffusion layer, the second diffusion layer, and the gate wiring.
  • a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer.
  • a second step of forming a third resist for forming a gate wiring and performing the anisotropic etching to form the gate wiring after the second process, Depositing a resist to expose the polysilicon film on the upper side wall of the columnar silicon layer; removing the exposed polysilicon film by etching; stripping the fourth resist; removing the metal film by etching;
  • a self-alignment process is realized by the third step of forming a gate electrode connected to the gate wiring. Since it is a self-alignment process, high integration is possible.
  • the gate wiring has a laminated structure of the metal film and silicide. Since the silicide and the metal film are in direct contact, the resistance can be reduced.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • a fin-like silicon layer 103 is formed on a silicon substrate 101, a first insulating film 104 is formed around the fin-like silicon layer 103, and a columnar silicon layer 106 is formed on the fin-like silicon layer 103. Indicates. As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.
  • the silicon substrate 101 is etched to form a fin-like silicon layer 103.
  • the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.
  • the first resist 102 is removed.
  • the second resist 105 is removed.
  • a fourth resist 112 is deposited, the polysilicon film 109 on the upper side wall of the columnar silicon layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is stripped, and a metal film A manufacturing method in which 108 is removed by etching and a gate electrode 111a connected to the gate wiring 111b is formed will be described.
  • the first diffusion layer 114 is formed on the top of the columnar silicon layer 106 and the second diffusion layer 113 is formed on the bottom of the columnar silicon layer 106 and the top of the fin-like silicon layer 103 will be described.
  • the gate wiring 111b tends to have a laminated structure of the metal film 108 and the silicide 119. Since the silicide 119 and the metal film 108 are in direct contact with each other, the resistance can be reduced.
  • the interlayer insulating film 121 is etched to form contact holes 123 and 124.
  • the fifth resist 122 is removed.
  • the interlayer insulating film 121 is etched to form a contact hole 126.
  • the sixth resist 125 is removed.
  • the contact stopper 140 at the bottom of the contact holes 123, 124, 126 is removed by etching.
  • seventh resists 131, 132, 133 for forming metal wiring are formed.
  • the seventh resists 131, 132, 133 are peeled off.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/JP2012/070145 2012-08-08 2012-08-08 Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur Ceased WO2014024266A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014508629A JP5595619B2 (ja) 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置
PCT/JP2012/070145 WO2014024266A1 (fr) 2012-08-08 2012-08-08 Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur
TW102128020A TW201407788A (zh) 2012-08-08 2013-08-06 半導體裝置的製造方法以及半導體裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/070145 WO2014024266A1 (fr) 2012-08-08 2012-08-08 Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur

Publications (1)

Publication Number Publication Date
WO2014024266A1 true WO2014024266A1 (fr) 2014-02-13

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PCT/JP2012/070145 Ceased WO2014024266A1 (fr) 2012-08-08 2012-08-08 Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur

Country Status (3)

Country Link
JP (1) JP5595619B2 (fr)
TW (1) TW201407788A (fr)
WO (1) WO2014024266A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015125204A1 (fr) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur
WO2015125205A1 (fr) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs
WO2015132913A1 (fr) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur
WO2015132912A1 (fr) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs
JP5798276B1 (ja) * 2014-06-16 2015-10-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015193940A1 (fr) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteur et dispositif à semi-conducteur
JP2016105500A (ja) * 2016-02-01 2016-06-09 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
US9530793B2 (en) 2014-03-03 2016-12-27 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

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JP2009532903A (ja) * 2006-04-04 2009-09-10 マイクロン テクノロジー， インク． 成長型ナノＦｉｎトランジスタ
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2011071235A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体装置及びその製造方法
JP2011077437A (ja) * 2009-10-01 2011-04-14 Unisantis Electronics Japan Ltd 半導体装置
JP2011100826A (ja) * 2009-11-05 2011-05-19 Elpida Memory Inc 半導体装置の製造方法および半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009532903A (ja) * 2006-04-04 2009-09-10 マイクロン テクノロジー， インク． 成長型ナノＦｉｎトランジスタ
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2011071235A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体装置及びその製造方法
JP2011077437A (ja) * 2009-10-01 2011-04-14 Unisantis Electronics Japan Ltd 半導体装置
JP2011100826A (ja) * 2009-11-05 2011-05-19 Elpida Memory Inc 半導体装置の製造方法および半導体装置

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015125205A1 (fr) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs
US10811535B2 (en) 2014-02-18 2020-10-20 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device including surrounding gate transistor having a gate electrode with inclined side surface
US10804397B2 (en) 2014-02-18 2020-10-13 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device with surrounding gate transistor (SGT)
WO2015125204A1 (fr) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur
JP5822326B1 (ja) * 2014-02-18 2015-11-24 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
US9812547B2 (en) 2014-02-18 2017-11-07 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9755053B2 (en) 2014-02-18 2017-09-05 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9640628B2 (en) 2014-02-18 2017-05-02 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9530793B2 (en) 2014-03-03 2016-12-27 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device
US9865741B2 (en) 2014-03-05 2018-01-09 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US9893179B2 (en) 2014-03-05 2018-02-13 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US10923591B2 (en) 2014-03-05 2021-02-16 Unisantis Electronics Singapore Pte. Ltd. Method for producing a semiconductor device
JP5838529B1 (ja) * 2014-03-05 2016-01-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
JP5838530B1 (ja) * 2014-03-05 2016-01-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015132913A1 (fr) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif semi-conducteur et dispositif semi-conducteur
WO2015132912A1 (fr) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs
US10475922B2 (en) 2014-03-05 2019-11-12 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US9960277B2 (en) 2014-03-05 2018-05-01 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device
US9647142B2 (en) 2014-06-16 2017-05-09 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
JP5798276B1 (ja) * 2014-06-16 2015-10-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015193939A1 (fr) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteurs et dispositif à semi-conducteurs
US10026842B2 (en) 2014-06-16 2018-07-17 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device
US9780215B2 (en) 2014-06-16 2017-10-03 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
WO2015193940A1 (fr) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Procédé de fabrication de dispositif à semi-conducteur et dispositif à semi-conducteur
JP5902868B1 (ja) * 2014-06-16 2016-04-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
JP2016105500A (ja) * 2016-02-01 2016-06-09 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置

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Publication number Publication date
TW201407788A (zh) 2014-02-16
JPWO2014024266A1 (ja) 2016-07-21
JP5595619B2 (ja) 2014-09-24

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