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WO2014087479A1 - High-frequency power amplifier - Google Patents

High-frequency power amplifier Download PDF

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Publication number
WO2014087479A1
WO2014087479A1 PCT/JP2012/081355 JP2012081355W WO2014087479A1 WO 2014087479 A1 WO2014087479 A1 WO 2014087479A1 JP 2012081355 W JP2012081355 W JP 2012081355W WO 2014087479 A1 WO2014087479 A1 WO 2014087479A1
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WO
WIPO (PCT)
Prior art keywords
power amplifier
frequency power
frequency
frequency signal
high frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/081355
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French (fr)
Japanese (ja)
Inventor
正和 廣部
和宏 弥政
森 一富
檜枝 護重
堀口 健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to PCT/JP2012/081355 priority Critical patent/WO2014087479A1/en
Priority to TW102103255A priority patent/TW201424256A/en
Publication of WO2014087479A1 publication Critical patent/WO2014087479A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/246A series resonance being added in shunt in the input circuit, e.g. base, gate, of an amplifier stage, e.g. as a trap

Definitions

  • the present invention relates to a high frequency power amplifier applied to, for example, a broadband multiband power amplifier.
  • a transistor for high frequency signal amplification using a FET (Field Effect Transistor) or an HBT (Heterojunction Bipolar Transistor), a bias circuit, And a matching circuit As for a high frequency power amplifier for a portable terminal, like a high frequency power amplifier described in Patent Document 1 below, a transistor for high frequency signal amplification using a FET (Field Effect Transistor) or an HBT (Heterojunction Bipolar Transistor), a bias circuit, And a matching circuit.
  • FET Field Effect Transistor
  • HBT Heterojunction Bipolar Transistor
  • a reception band noise level at the time of transmission.
  • mobile terminals As mobile terminals become more multifunctional, they are required to have low noise levels in multiple frequency bands such as DTV (Digital Television) band, GPS (Global Positioning System) band, and ISM (Industrial Scientific Medical) band in addition to the reception band. It has been.
  • the out-of-band noise level output from the high-frequency power amplifier is represented by input noise level ⁇ out-of-band gain + nonlinear noise level.
  • the transmission band, reception band, and other frequency bands are far enough to change the gain in each band independently, it is possible to reduce the out-of-band noise level by reducing the out-of-band gain.
  • multiple frequency bands can be amplified by a common high-frequency signal amplification transistor.
  • the out-of-band noise level is lowered by reducing only the out-of-band gain without reducing the transmission band gain. It is difficult to do.
  • the bias circuit which is one of the noise generation sources, the bias circuit generates noise having frequency components in the reception band and other bands, as well as in the transmission band, reception band, and other areas. Noise having a difference frequency (difference frequency) from the frequency band is generated.
  • noise having a difference frequency is input from the bias circuit to the high frequency signal amplification transistor, the transmission wave signal and the noise having the difference frequency are mixed in the high frequency signal amplification transistor, and are out of band in the reception band and other frequency bands. There were problems such as noise.
  • the present invention has been made in order to solve the above-described problems. By suppressing the noise having the difference frequency generated in the bias circuit from being input to the high frequency signal amplifying transistor, the transmission band gain is increased.
  • An object of the present invention is to obtain a high-frequency power amplifier that suppresses out-of-band noise without reducing it.
  • a high-frequency power amplifier includes a high-frequency signal amplification transistor that amplifies a high-frequency signal, a bias circuit that supplies a bias to a high-frequency signal input side of the high-frequency signal amplification transistor, a high-frequency signal amplification transistor, and a bias circuit.
  • One end is connected between the other end, the other end is grounded, and a series resonant circuit including an inductor and a capacitor is provided.
  • the series resonance circuit including the inductor and the capacitor is provided, with one end connected between the high frequency signal amplifying transistor and the bias circuit and the other end grounded. Therefore, by suppressing the noise having the difference frequency generated in the bias circuit from being input to the high frequency signal amplifying transistor, it is possible to suppress the out-of-band noise without reducing the transmission band gain. .
  • FIG. 1 is a configuration diagram illustrating a high frequency power amplifier according to a first embodiment of the present invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 2 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 3 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 4 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 5 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 6 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 7 of this invention. It is a block diagram which shows the high frequency power amplifier by Embodiment 8 of this invention.
  • FIG. FIG. 1 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 1 of the present invention.
  • the input matching circuit 2 connected to the input terminal 1 and one or more stages connected to the subsequent stage of the input matching circuit 2 for amplifying a high frequency signal from the input terminal 1 via the input matching circuit 2
  • a high frequency signal amplifying transistor 3 and an output matching circuit 4 connected to the subsequent stage of the high frequency signal amplifying transistor 3 and outputting the amplified high frequency signal to the output terminal 5 are provided.
  • a bias circuit 6 that supplies a bias to the high-frequency signal input side of the high-frequency signal amplifying transistor 3 and one end connected between the high-frequency signal amplifying transistor 3 and the bias circuit 6 and the other end connected to the ground.
  • a series resonance circuit 7 including a series connection of an inductor 8 and a capacitor 9.
  • the high frequency signal amplifying transistor 3 When the high frequency signal amplifying transistor 3 is composed of an FET, a bias voltage is applied from the bias circuit 6 to the gate of the FET.
  • the bias circuit 6 A bias current is supplied to the base of the HBT.
  • the inductor 8 constituting the series resonance circuit 7 is formed by a spiral inductor or a chip inductor, and the capacitor 9 is formed by an MIM (Metal Insulator Metal) capacitor or a chip capacitor.
  • the values of the inductor 8 and the capacitor 9 are set so that the resonance frequency of the series resonance circuit 7 is in the vicinity of the difference frequency, thereby reducing the impedance of the series resonance circuit 7 at the difference frequency.
  • the noise having the difference frequency is caused to flow to the ground via the series resonance circuit 7, thereby suppressing the noise having the difference frequency from being input to the high frequency signal amplifying transistor 3.
  • the inductance of the inductor 8 is L [H]
  • the input impedance of the high frequency signal amplification transistor 3 is Rintr [ ⁇ ]
  • the frequency of the transmission band is fRF [Hz]
  • L is set so that the following relationship holds
  • the impedance of the series resonant circuit 7 is set sufficiently high with respect to the input impedance of the high-frequency signal amplifying transistor 3, so that the signal in the transmission band is grounded via the series resonant circuit 7. Suppresses the flow to
  • the out-of-band noise level can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain.
  • any one or all of the amplifying stage bias circuits 6 are connected in series between the high-frequency signal amplifying transistors 3.
  • a resonance circuit 7 may be connected.
  • the noise generated in the first-stage high-frequency signal amplifying transistor 3 is amplified in the subsequent stage, and thus has a great influence on the output out-of-band noise. Therefore, the effect of reducing the out-of-band noise level obtained when the series resonance circuit 7 is connected to the first stage is great, and the number of series resonance circuits 7 to be connected can be reduced, so that the size can be reduced.
  • the inductor 8 by using a spiral inductor for the inductor 8, it is possible to reduce the size.
  • the use of a chip inductor results in a low loss, so that an effect of suppressing a decrease in transmission band gain can be obtained.
  • the capacitor 9 can be miniaturized by using an MIM capacitor when the required capacitance value is small.
  • a large capacitance can be realized by using a chip capacitor, it is possible to cope with a case where the difference frequency is low.
  • one end is connected between the high-frequency signal amplifying transistor 3 and the bias circuit 6 and the other end is connected to the ground, and includes the inductor 8 and the capacitor 9 in series.
  • a resonance circuit 7 was provided. Therefore, by suppressing the noise having the difference frequency generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3, the out-of-band noise can be suppressed without reducing the transmission band gain.
  • the inductance of the inductor 8 is L [H]
  • the frequency of the high-frequency signal amplified by the high-frequency signal amplification transistor 3 is fRF [Hz]
  • the input impedance of the high-frequency signal amplification transistor 3 Is set to Rintr [ ⁇ ] so that the relationship of L> 5 ⁇ Rintr / 2 ⁇ ⁇ fRF is established. Therefore, by setting the impedance of the series resonance circuit 7 sufficiently high with respect to the input impedance of the high frequency signal amplification transistor 3, it is possible to suppress the transmission band signal from flowing to the ground via the series resonance circuit 7. .
  • the high-frequency signal amplification transistor 3 is a multistage amplifier having two or more stages
  • the series resonance circuit 7 includes the first-stage high-frequency signal amplification transistor 3 and the bias circuit 6. One end was connected between. Therefore, the effect of reducing the out-of-band noise level obtained when the series resonance circuit 7 is connected to the first stage is great, and the number of series resonance circuits 7 to be connected can be reduced, so that the size can be reduced. it can.
  • the inductor 8 of the series resonant circuit 7 is provided with a spiral inductor. Therefore, it is possible to reduce the size.
  • the inductor 8 of the series resonant circuit 7 is provided as a chip inductor. Therefore, since the loss is low, it is possible to suppress a decrease in transmission band gain.
  • the capacitor 9 of the series resonant circuit 7 is provided as a MIM capacitor. Therefore, it is possible to reduce the size.
  • the capacitor 9 of the series resonance circuit 7 is provided as a chip capacitor. Therefore, since a large capacitance can be realized, it is possible to cope with a case where the difference frequency is low.
  • FIG. FIG. 2 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 2 of the present invention.
  • the series resonant circuit 10 of the second embodiment a plurality of series resonant circuits 7 of the high-frequency power amplifier according to the first embodiment are connected in parallel, and the inductor 8 and the capacitor 9 constituting each series resonant circuit 7 have different values. Is set to have a plurality of different resonance frequencies.
  • the second embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.
  • the second embodiment is different from the first embodiment only in the series resonance circuit 10 connected.
  • the series resonance circuit 10 connected in parallel further transmits.
  • noise having a plurality of difference frequencies generated by the bias circuit 6 is grounded via a plurality of series resonance circuits 10.
  • the input to the high frequency signal amplification transistor 3 is suppressed.
  • each inductor 8 is set so that the impedance of the series resonant circuit 10 is sufficiently higher than the input impedance of the high-frequency amplification transistor 3. The signal is prevented from flowing to the ground via the series resonant circuit 10.
  • the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.
  • the series resonance circuit 10 connected in parallel has a plurality of difference frequencies generated by the bias circuit 6 by having resonance frequencies at a plurality of difference frequencies between the transmission band frequency and the plurality of out-of-band frequencies. Noise can be caused to flow through the plurality of series resonance circuits 10 to the ground, and input to the high frequency signal amplifying transistor 3 can be suppressed.
  • FIG. 3 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 3 of the present invention.
  • the series resonant circuit 11 of the third embodiment includes a plurality of capacitors 9 connected in parallel via switches 12 instead of the capacitors 9 constituting the series resonant circuit 7 of the high frequency power amplifier according to the first embodiment.
  • the resonance frequency is made variable by switching the number or size of the capacitors 9 by turning on / off the switch 12.
  • the third embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.
  • the third embodiment is different from the first embodiment only in the series resonant circuit 11 that is connected.
  • the inductance of the inductor 8 is set so that the impedance of the series resonant circuit 11 is sufficiently higher than the input impedance of the high-frequency signal amplification transistor 3, so that the signal in the transmission band is set. Is prevented from flowing to the ground via the series resonant circuit 11.
  • the third embodiment can be downsized because the inductor 8 having a large size is shared with the second embodiment and can be realized by the small switch 12.
  • a plurality of capacitors 9 of the series resonant circuit 11 are connected in parallel via the switch 12, and the capacitor 9 is switched by turning on / off the switch 12.
  • a circuit in which the resonance frequency of the series resonance circuit 11 is changed is provided. Therefore, by switching the value of the capacitor 9 of the series resonance circuit 11 according to the frequency band outside the band where the noise level is desired to be reduced, the noise having a plurality of difference frequencies generated in the bias circuit 6 is passed through the series resonance circuit 11. It is possible to suppress the input to the high-frequency signal amplification transistor 3 by flowing to the ground.
  • FIG. 4 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 4 of the present invention.
  • the high frequency signal amplifying transistor 3 and the bias circuit 6 are connected in series, and the inductor 14 and the capacitor 15 are connected in parallel.
  • a parallel resonant circuit 13 is provided.
  • the inductor 14 constituting the parallel resonance circuit 13 is formed by a spiral inductor or a chip inductor, and the capacitor 15 is formed by an MIM capacitor or a chip capacitor.
  • the values of the inductor 14 and the capacitor 15 are set so that the resonance frequency of the parallel resonance circuit 13 is in the vicinity of the difference frequency, thereby increasing the impedance of the parallel resonance circuit 13 at the difference frequency. As a result, noise having a difference frequency is prevented from being input to the high frequency signal amplification transistor 3.
  • the out-of-band noise level can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain.
  • a parallel connection between the bias circuit 6 of any amplification stage or all amplification stages and the high-frequency signal amplification transistors 3 is performed.
  • a resonance circuit 13 may be connected.
  • the noise generated in the first-stage high-frequency signal amplifying transistor 3 is amplified in the subsequent stage, and thus has a great influence on the output out-of-band noise. Therefore, the effect of reducing the out-of-band noise level obtained when the parallel resonance circuit 13 is connected to the first stage is great, and the number of parallel resonance circuits 13 to be connected can be reduced, and the size can be reduced.
  • the use of a spiral inductor for the inductor 14 enables miniaturization.
  • the loss is reduced by using the chip inductor, an effect of suppressing the decrease in the transmission band gain can be obtained.
  • the capacitor 15 can be miniaturized by using an MIM capacitor when the required capacitance value is small.
  • a large capacitance can be realized by using a chip capacitor, it is possible to cope with a case where the difference frequency is low.
  • the parallel resonant circuit 13 including the inductor 14 and the capacitor 15 is provided in series between the high-frequency signal amplification transistor 3 and the bias circuit 6. Therefore, by suppressing the noise having the difference frequency generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3, the out-of-band noise can be suppressed without reducing the transmission band gain.
  • the high-frequency signal amplification transistor 3 is a multistage amplifier having two or more stages, and the parallel resonance circuit 13 includes the first-stage high-frequency signal amplification transistor 3 and the bias circuit 6.
  • the one connected in series was provided. Therefore, the effect of reducing the out-of-band noise level obtained when the parallel resonant circuit 13 is connected to the first stage is great, and the number of parallel resonant circuits 13 to be connected can be reduced, thereby enabling downsizing. it can.
  • FIG. 5 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 5 of the present invention.
  • a plurality of parallel resonant circuits 13 of the high-frequency power amplifier according to the fourth embodiment are connected in series, and different values are set for the inductor 14 and the capacitor 15 constituting each parallel resonant circuit.
  • Each has a plurality of different resonance frequencies.
  • the fifth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.
  • the fifth embodiment is different from the fourth embodiment only in the parallel resonance circuit 16 connected.
  • the parallel resonance circuit 16 connected in series further transmits.
  • the impedance of the parallel resonant circuit 16 at a plurality of difference frequencies is increased by having resonance frequencies at a plurality of difference frequencies between the band frequency and the plurality of out-of-band frequencies.
  • the noise having a plurality of difference frequencies generated in the bias circuit 6 is suppressed from being input to the high frequency signal amplification transistor 3.
  • the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.
  • a plurality of parallel resonant circuits 16 are connected in series, each having a different resonant frequency. Therefore, the parallel resonance circuit 16 connected in series has resonance frequencies at a plurality of difference frequencies between the transmission band frequency and the plurality of out-of-band frequencies, thereby reducing the impedance of the parallel resonance circuit 16 at the plurality of difference frequencies. Make it high. Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3.
  • FIG. 6 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 6 of the present invention.
  • a plurality of capacitors 15 each connected in parallel via a switch 18 are provided.
  • the resonance frequency is made variable by switching the number or size of the capacitors 15 by turning on / off.
  • the sixth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.
  • the sixth embodiment is different from the fourth embodiment only in the parallel resonant circuit 17 connected.
  • the out-of-band noise level can be set for each frequency band in which noise is desired to be reduced. It becomes possible to reduce. Further, the sixth embodiment can be miniaturized because the inductor 14 having a large size is shared with the fifth embodiment and can be realized by the small switch 18.
  • a plurality of capacitors 15 of the parallel resonant circuit 17 are connected in parallel via the switch 18, and the capacitor 15 is switched by turning on / off the switch 18.
  • the parallel resonance circuit 17 is provided with a variable resonance frequency. Therefore, by switching the value of the capacitor of the parallel resonant circuit 17 according to the frequency band outside the band where the noise level is desired to be reduced, noise having a plurality of difference frequencies generated in the bias circuit 6 is input to the high frequency signal amplifying transistor 3. Can be suppressed.
  • FIG. 7 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 7 of the present invention.
  • the series resonant circuit 19 of the seventh embodiment is obtained by connecting a resistor 20 in series to the series resonant circuit 7 of the high-frequency power amplifier according to the first embodiment.
  • the impedance of the series resonant circuit 19 is set to a wider frequency band. It is a low one.
  • the seventh embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands in a plurality of transmission band frequencies.
  • the seventh embodiment is different from the first embodiment only in the series resonance circuit 19 that is connected.
  • the resonance of the series resonance circuit 19 including the resistor 20 is further obtained.
  • the impedance of the series resonance circuit 19 at the plurality of difference frequencies is lowered.
  • noise having a plurality of difference frequencies is caused to flow to the ground via the series resonance circuit 19, thereby suppressing the noise having the plurality of difference frequencies from being input to the high frequency signal amplification transistor 3.
  • the signal in the transmission band can be obtained.
  • the flow to the ground via the series resonance circuit 19 is suppressed.
  • the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain.
  • the seventh embodiment can be downsized because a plurality of inductors 8 and capacitors 9 can be used in common with the second and third embodiments.
  • the series resonance circuit 19 includes the inductor 8 and the capacitor 9 including the resistor 20 connected in series. Therefore, by setting the values of the inductor 8 and the capacitor 9 so that the resonance frequency of the series resonance circuit 19 including the resistor 20 becomes an intermediate frequency between the plurality of difference frequencies close to each other, the series resonance circuit at the plurality of difference frequencies. 19 Impedance is lowered. Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high-frequency signal amplification transistor 3 by flowing to the ground via the series resonance circuit 19.
  • FIG. 8 shows a configuration diagram of a high-frequency power amplifier according to an eighth embodiment of the present invention.
  • a resistor 22 is connected in series to the parallel resonant circuit 13 of the high-frequency power amplifier according to the fourth embodiment, and the impedance of the parallel resonant circuit 21 is increased over a wider frequency band. .
  • the eighth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands in a plurality of transmission band frequencies.
  • the eighth embodiment is different from the fourth embodiment only in the connected parallel resonance circuit 21.
  • the resonance of the parallel resonance circuit 21 including the resistor 22 is further obtained.
  • the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible. Further, in the eighth embodiment, since the plurality of inductors 14 and the capacitors 15 can be made common to the fifth and sixth embodiments, the size can be reduced.
  • the parallel resonant circuit 21 includes the inductor 14 and the capacitor 15 including the resistor 22 connected in series. Therefore, by setting the values of the inductor 14 and the capacitor 15 so that the resonance frequency of the parallel resonance circuit 21 including the resistor 22 becomes an intermediate frequency of the plurality of difference frequencies close to each other, the parallel resonance circuit at the plurality of difference frequencies Increase the impedance of 21. Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3.
  • the high-frequency power amplifiers shown in the first to eighth embodiments can be applied to a wideband multiband power amplifier that includes a reception band between a plurality of transmission bands for power amplification.
  • one end is connected between the high frequency signal amplifying transistor 3 and the bias circuit 6 and the other end is connected to the ground, and the series resonance including the inductor 8 and the capacitor 9 is performed. Since the circuit 7 is provided, it is suitable for use in a wideband multiband power amplifier.

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Abstract

The present invention is provided with a series resonant circuit (7), one end of which is connected between a high-frequency signal amplification transistor (3) and a bias circuit (6), and the other end of which is connected to ground, the series resonant circuit (7) including an inductor (8) and a capacitor (9). By this configuration, noise having a differential frequency that occurs in the bias circuit (6) is suppressed from being input to the high-frequency signal amplification transistor (3), the transmission band gain is thereby prevented from decreasing, and out-of-band noise can be suppressed.

Description

高周波電力増幅器High frequency power amplifier

 この発明は、例えば、広帯域マルチバンド電力増幅器に適用される高周波電力増幅器に関する。 The present invention relates to a high frequency power amplifier applied to, for example, a broadband multiband power amplifier.

 近年、携帯端末では複数の周波数バンドへの対応が求められている。
 これに伴い、搭載される送信用高周波電力増幅器も周波数バンドの数に応じて増加しており、携帯端末における高周波電力増幅器の占有面積が増加傾向にある。
 一方で携帯端末の多機能化や高機能化に伴う部品点数の増加や、消費電力の増加によるバッテリーの大型化といった背景から、高周波増幅器に対して小型化や、一つの増幅器で複数の周波数バンドに対応するマルチバンド化が求められている。
In recent years, mobile terminals are required to support a plurality of frequency bands.
Along with this, the number of high-frequency power amplifiers for transmission mounted is also increasing according to the number of frequency bands, and the occupation area of the high-frequency power amplifier in the mobile terminal tends to increase.
On the other hand, because of the increase in the number of parts associated with the increase in functionality and functionality of mobile terminals and the increase in battery size due to the increase in power consumption, downsizing of high-frequency amplifiers and multiple frequency bands with a single amplifier There is a need for multi-band processing.

 携帯端末用高周波電力増幅器については、下記特許文献1に記載されている高周波電力増幅器のように、FET(Field Effect Transistor)またはHBT(Heterojunction Bipolar Transistor)を用いた高周波信号増幅用トランジスタ、バイアス回路、および整合回路などにより構成される。 As for a high frequency power amplifier for a portable terminal, like a high frequency power amplifier described in Patent Document 1 below, a transistor for high frequency signal amplification using a FET (Field Effect Transistor) or an HBT (Heterojunction Bipolar Transistor), a bias circuit, And a matching circuit.

特開平11-195932号公報JP-A-11-195932

 携帯端末用高周波電力増幅器においては、送信時における受信帯雑音レベルに対する規定がある。
 また、携帯端末の多機能化に伴い、受信帯以外にもDTV(Digital Television)帯やGPS(Global Positioning System)帯、ISM(Industrial Scientific Medical)帯など、複数の周波数バンドにおける低い雑音レベルに求められている。
In a high frequency power amplifier for a portable terminal, there is a regulation for a reception band noise level at the time of transmission.
As mobile terminals become more multifunctional, they are required to have low noise levels in multiple frequency bands such as DTV (Digital Television) band, GPS (Global Positioning System) band, and ISM (Industrial Scientific Medical) band in addition to the reception band. It has been.

 一般的に、高周波電力増幅器から出力される帯域外雑音レベルは、入力雑音レベル×帯域外利得+非線形雑音レベルによって表される。 Generally, the out-of-band noise level output from the high-frequency power amplifier is represented by input noise level × out-of-band gain + nonlinear noise level.

 送信帯と受信帯やその他の周波数バンドが、それぞれの帯域における利得を独立に変えられる程度に離れている場合は、帯域外利得を低減することにより帯域外雑音レベルを低減することが可能である。
 しかし、送信帯に受信帯が近い場合や、送信帯に他の周波数バンドが近い場合や、広帯域な周波数特性を実現することにより、複数の周波数バンドを共通の高周波信号増幅用トランジスタで増幅するマルチバンド電力増幅器において、複数の送信帯の間に受信帯やその他の周波数バンドが存在する場合には、送信帯利得を低下させずに帯域外利得のみを低下させることで、帯域外雑音レベルを低下させるのは困難である。
If the transmission band, reception band, and other frequency bands are far enough to change the gain in each band independently, it is possible to reduce the out-of-band noise level by reducing the out-of-band gain. .
However, when the reception band is close to the transmission band, when other frequency bands are close to the transmission band, or by realizing wideband frequency characteristics, multiple frequency bands can be amplified by a common high-frequency signal amplification transistor. In a band power amplifier, when there are reception bands or other frequency bands between multiple transmission bands, the out-of-band noise level is lowered by reducing only the out-of-band gain without reducing the transmission band gain. It is difficult to do.

 一方、非線形雑音レベルについては、雑音発生源の一つであるバイアス回路に着目すると、バイアス回路では受信帯およびその他の帯域の周波数成分をもつ雑音が発生する他、送信帯と受信帯およびその他の周波数バンドとの差分の周波数(差周波)をもつ雑音が発生する。
 バイアス回路から高周波信号増幅用トランジスタへ差周波をもつ雑音が入力された場合、高周波信号増幅用トランジスタにおいて送信波信号と差周波をもつ雑音とがミキシングされ、受信帯およびその他の周波数バンドに帯域外雑音が発生するなどの課題があった。
On the other hand, regarding the non-linear noise level, focusing on the bias circuit, which is one of the noise generation sources, the bias circuit generates noise having frequency components in the reception band and other bands, as well as in the transmission band, reception band, and other areas. Noise having a difference frequency (difference frequency) from the frequency band is generated.
When noise having a difference frequency is input from the bias circuit to the high frequency signal amplification transistor, the transmission wave signal and the noise having the difference frequency are mixed in the high frequency signal amplification transistor, and are out of band in the reception band and other frequency bands. There were problems such as noise.

 この発明は、前記のような課題を解決するためになされたもので、バイアス回路において発生する差周波をもつ雑音が高周波信号増幅用トランジスタへ入力されるのを抑制することで、送信帯利得を低下させることなく帯域外雑音を抑制する高周波電力増幅器を得ることを目的とする。 The present invention has been made in order to solve the above-described problems. By suppressing the noise having the difference frequency generated in the bias circuit from being input to the high frequency signal amplifying transistor, the transmission band gain is increased. An object of the present invention is to obtain a high-frequency power amplifier that suppresses out-of-band noise without reducing it.

 この発明に係る高周波電力増幅器は、高周波信号を増幅する高周波信号増幅用トランジスタと、高周波信号増幅用トランジスタの高周波信号入力側にバイアスを供給するバイアス回路と、高周波信号増幅用トランジスタとバイアス回路との間に一端が接続されると共に他端が接地され、インダクタおよびキャパシタを含む直列共振回路とを備える。 A high-frequency power amplifier according to the present invention includes a high-frequency signal amplification transistor that amplifies a high-frequency signal, a bias circuit that supplies a bias to a high-frequency signal input side of the high-frequency signal amplification transistor, a high-frequency signal amplification transistor, and a bias circuit. One end is connected between the other end, the other end is grounded, and a series resonant circuit including an inductor and a capacitor is provided.

 この発明によれば、高周波信号増幅用トランジスタとバイアス回路との間に一端が接続されると共に他端が接地され、インダクタおよびキャパシタを含む直列共振回路を備えた。
 よって、バイアス回路において発生する差周波をもつ雑音が高周波信号増幅用トランジスタへ入力されるのを抑制することで、送信帯利得を低下させることなく、帯域外雑音を抑制することができる効果がある。
According to the present invention, the series resonance circuit including the inductor and the capacitor is provided, with one end connected between the high frequency signal amplifying transistor and the bias circuit and the other end grounded.
Therefore, by suppressing the noise having the difference frequency generated in the bias circuit from being input to the high frequency signal amplifying transistor, it is possible to suppress the out-of-band noise without reducing the transmission band gain. .

この発明の実施の形態1による高周波電力増幅器を示す構成図である。1 is a configuration diagram illustrating a high frequency power amplifier according to a first embodiment of the present invention. この発明の実施の形態2による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 2 of this invention. この発明の実施の形態3による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 3 of this invention. この発明の実施の形態4による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 4 of this invention. この発明の実施の形態5による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 5 of this invention. この発明の実施の形態6による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 6 of this invention. この発明の実施の形態7による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 7 of this invention. この発明の実施の形態8による高周波電力増幅器を示す構成図である。It is a block diagram which shows the high frequency power amplifier by Embodiment 8 of this invention.

 以下、この発明をより詳細に説明するために、この発明を実施するための形態について、添付の図面に従って説明する。
実施の形態1.
 図1にこの発明による実施の形態1の高周波電力増幅器の構成図を示す。
 この実施の形態1では、入力端子1に接続された入力整合回路2と、入力整合回路2の後段に接続され、入力端子1から入力整合回路2を介した高周波信号を増幅する1段以上の高周波信号増幅用トランジスタ3と、高周波信号増幅用トランジスタ3の後段に接続され、増幅された高周波信号を出力端子5に出力する出力整合回路4を備える。
Hereinafter, in order to explain the present invention in more detail, modes for carrying out the present invention will be described with reference to the accompanying drawings.
Embodiment 1 FIG.
FIG. 1 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 1 of the present invention.
In the first embodiment, the input matching circuit 2 connected to the input terminal 1 and one or more stages connected to the subsequent stage of the input matching circuit 2 for amplifying a high frequency signal from the input terminal 1 via the input matching circuit 2 A high frequency signal amplifying transistor 3 and an output matching circuit 4 connected to the subsequent stage of the high frequency signal amplifying transistor 3 and outputting the amplified high frequency signal to the output terminal 5 are provided.

 また、高周波信号増幅用トランジスタ3の高周波信号入力側にバイアスを供給するバイアス回路6と、高周波信号増幅用トランジスタ3とバイアス回路6との間に一端が接続されると共に他端がグランドに接続され、インダクタ8およびキャパシタ9の直列接続からなる直列共振回路7を備える。 A bias circuit 6 that supplies a bias to the high-frequency signal input side of the high-frequency signal amplifying transistor 3 and one end connected between the high-frequency signal amplifying transistor 3 and the bias circuit 6 and the other end connected to the ground. And a series resonance circuit 7 including a series connection of an inductor 8 and a capacitor 9.

 なお、高周波信号増幅用トランジスタ3がFETにより構成される場合は、バイアス回路6からFETのゲートにバイアス電圧を印加し、高周波信号増幅用トランジスタ3がHBTにより構成される場合は、バイアス回路6からHBTのベースにバイアス電流を供給する。
 直列共振回路7を構成するインダクタ8は、スパイラルインダクタもしくはチップインダクタにより形成され、キャパシタ9は、MIM(Metal Insulator Metal)キャパシタもしくはチップコンデンサにより形成される。
When the high frequency signal amplifying transistor 3 is composed of an FET, a bias voltage is applied from the bias circuit 6 to the gate of the FET. When the high frequency signal amplifying transistor 3 is composed of an HBT, the bias circuit 6 A bias current is supplied to the base of the HBT.
The inductor 8 constituting the series resonance circuit 7 is formed by a spiral inductor or a chip inductor, and the capacitor 9 is formed by an MIM (Metal Insulator Metal) capacitor or a chip capacitor.

 この実施の形態1では、直列共振回路7の共振周波数が差周波付近となるようにインダクタ8およびキャパシタ9の値を設定することで、差周波における直列共振回路7のインピーダンスを低くする。
 これにより、差周波をもつ雑音を直列共振回路7を介してグランドへ流すことで、差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
In the first embodiment, the values of the inductor 8 and the capacitor 9 are set so that the resonance frequency of the series resonance circuit 7 is in the vicinity of the difference frequency, thereby reducing the impedance of the series resonance circuit 7 at the difference frequency.
As a result, the noise having the difference frequency is caused to flow to the ground via the series resonance circuit 7, thereby suppressing the noise having the difference frequency from being input to the high frequency signal amplifying transistor 3.

 また、インダクタ8のインダクタンスをL[H]、高周波信号増幅用トランジスタ3の入力インピーダンスをRintr[Ω]、送信帯の周波数をfRF[Hz]とした場合に、L>5×Rintr/2π・fRFの関係が成り立つようにLを設定し、高周波信号増幅用トランジスタ3の入力インピーダンスに対して直列共振回路7のインピーダンスを十分高く設定することで、送信帯の信号が直列共振回路7を介してグランドへ流れるのを抑制する。 Further, when the inductance of the inductor 8 is L [H], the input impedance of the high frequency signal amplification transistor 3 is Rintr [Ω], and the frequency of the transmission band is fRF [Hz], L> 5 × Rintr / 2π · fRF. L is set so that the following relationship holds, and the impedance of the series resonant circuit 7 is set sufficiently high with respect to the input impedance of the high-frequency signal amplifying transistor 3, so that the signal in the transmission band is grounded via the series resonant circuit 7. Suppresses the flow to

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、帯域外雑音レベルの低減が可能となる。 As described above, the out-of-band noise level can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain.

 なお、2段以上の高周波信号増幅用トランジスタ3で構成される多段増幅器の場合には、いずれかの増幅段、もしくは全ての増幅段のバイアス回路6と高周波信号増幅用トランジスタ3との間に直列共振回路7を接続してもよい。
 特に1段目の高周波信号増幅用トランジスタ3おいて生じる雑音については、後段で増幅されるため、出力される帯域外雑音に対する影響が大きい。
 よって、1段目に直列共振回路7を接続した場合に得られる帯域外雑音レベルの低減効果は大きく、また、接続する直列共振回路7の数を削減できるため、小型化が可能である。
 一方、最終段においては、高効率を実現するためにバックオフの小さな出力で使用されるため、歪みが大きくなりミキシングによる帯域外雑音が発生しやすい。
 よって、最終段に直列共振回路7を接続した場合に得られる帯域外雑音レベルの低減効果も大きく、また、接続する直列共振回路7の数を削減できるため、小型化が可能である。
In the case of a multistage amplifier including two or more stages of high-frequency signal amplifying transistors 3, any one or all of the amplifying stage bias circuits 6 are connected in series between the high-frequency signal amplifying transistors 3. A resonance circuit 7 may be connected.
In particular, the noise generated in the first-stage high-frequency signal amplifying transistor 3 is amplified in the subsequent stage, and thus has a great influence on the output out-of-band noise.
Therefore, the effect of reducing the out-of-band noise level obtained when the series resonance circuit 7 is connected to the first stage is great, and the number of series resonance circuits 7 to be connected can be reduced, so that the size can be reduced.
On the other hand, in the final stage, since it is used with an output with a small back-off in order to achieve high efficiency, distortion becomes large and out-of-band noise due to mixing tends to occur.
Therefore, the effect of reducing the out-of-band noise level obtained when the series resonance circuit 7 is connected to the final stage is great, and the number of series resonance circuits 7 to be connected can be reduced, so that the size can be reduced.

 また、インダクタ8にスパイラルインダクタを用いることで、小型化が可能となる。
 一方、チップインダクタを用いることで、低損失となるため、送信帯利得の低下を抑制する効果が得られる。
 キャパシタ9については、必要な容量値が小さい場合には、MIMキャパシタを用いることで小型化が可能となる。
 一方、チップコンデンサを用いることで、大きなキャパシタンスを実現できるため、差周波が低い場合にも対応が可能となる。
Further, by using a spiral inductor for the inductor 8, it is possible to reduce the size.
On the other hand, the use of a chip inductor results in a low loss, so that an effect of suppressing a decrease in transmission band gain can be obtained.
The capacitor 9 can be miniaturized by using an MIM capacitor when the required capacitance value is small.
On the other hand, since a large capacitance can be realized by using a chip capacitor, it is possible to cope with a case where the difference frequency is low.

 以上のように、この実施の形態1によれば、高周波信号増幅用トランジスタ3とバイアス回路6との間に一端が接続されると共に他端がグランドに接続され、インダクタ8およびキャパシタ9を含む直列共振回路7を備えた。
 よって、バイアス回路6において発生する差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制することで、送信帯利得を低下させることなく、帯域外雑音を抑制することができる。
As described above, according to the first embodiment, one end is connected between the high-frequency signal amplifying transistor 3 and the bias circuit 6 and the other end is connected to the ground, and includes the inductor 8 and the capacitor 9 in series. A resonance circuit 7 was provided.
Therefore, by suppressing the noise having the difference frequency generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3, the out-of-band noise can be suppressed without reducing the transmission band gain.

 また、この実施の形態1によれば、インダクタ8のインダクタンスをL[H]、高周波信号増幅用トランジスタ3により増幅される高周波信号の周波数をfRF[Hz]、高周波信号増幅用トランジスタ3の入力インピーダンスをRintr[Ω]とした場合に、L>5×Rintr/2π・fRFの関係が成り立つようにLを設定した。
 よって、高周波信号増幅用トランジスタ3の入力インピーダンスに対して直列共振回路7のインピーダンスを十分高く設定することで、送信帯の信号が直列共振回路7を介してグランドへ流れるのを抑制することができる。
Further, according to the first embodiment, the inductance of the inductor 8 is L [H], the frequency of the high-frequency signal amplified by the high-frequency signal amplification transistor 3 is fRF [Hz], and the input impedance of the high-frequency signal amplification transistor 3 Is set to Rintr [Ω] so that the relationship of L> 5 × Rintr / 2π · fRF is established.
Therefore, by setting the impedance of the series resonance circuit 7 sufficiently high with respect to the input impedance of the high frequency signal amplification transistor 3, it is possible to suppress the transmission band signal from flowing to the ground via the series resonance circuit 7. .

 さらに、この実施の形態1によれば、高周波信号増幅用トランジスタ3は、2段以上からなる多段増幅器であり、直列共振回路7は、1段目の高周波信号増幅用トランジスタ3とバイアス回路6との間に一端が接続されるものを備えた。
 よって、1段目に直列共振回路7を接続した場合に得られる帯域外雑音レベルの低減効果は大きく、また、接続する直列共振回路7の数を削減できるため、小型化を可能とすることができる。
Furthermore, according to the first embodiment, the high-frequency signal amplification transistor 3 is a multistage amplifier having two or more stages, and the series resonance circuit 7 includes the first-stage high-frequency signal amplification transistor 3 and the bias circuit 6. One end was connected between.
Therefore, the effect of reducing the out-of-band noise level obtained when the series resonance circuit 7 is connected to the first stage is great, and the number of series resonance circuits 7 to be connected can be reduced, so that the size can be reduced. it can.

 さらに、この実施の形態1によれば、直列共振回路7のインダクタ8は、スパイラルインダクタであるものを備えた。
 よって、小型化を可能とすることができる。
Further, according to the first embodiment, the inductor 8 of the series resonant circuit 7 is provided with a spiral inductor.
Therefore, it is possible to reduce the size.

 さらに、この実施の形態1によれば、直列共振回路7のインダクタ8は、チップインダクタであるものを備えた。
 よって、低損失となるため、送信帯利得の低下を抑制することができる。
Furthermore, according to the first embodiment, the inductor 8 of the series resonant circuit 7 is provided as a chip inductor.
Therefore, since the loss is low, it is possible to suppress a decrease in transmission band gain.

 さらに、この実施の形態1によれば、直列共振回路7のキャパシタ9は、MIMキャパシタであるものを備えた。
 よって、小型化を可能とすることができる。
Furthermore, according to the first embodiment, the capacitor 9 of the series resonant circuit 7 is provided as a MIM capacitor.
Therefore, it is possible to reduce the size.

 さらに、この実施の形態1によれば、直列共振回路7のキャパシタ9は、チップコンデンサであるものを備えた。
 よって、大きなキャパシタンスを実現できるため、差周波が低い場合にも対応を可能とすることができる。
Furthermore, according to the first embodiment, the capacitor 9 of the series resonance circuit 7 is provided as a chip capacitor.
Therefore, since a large capacitance can be realized, it is possible to cope with a case where the difference frequency is low.

実施の形態2.
 図2にこの発明による実施の形態2の高周波電力増幅器の構成図を示す。
 この実施の形態2の直列共振回路10は、前記実施の形態1による高周波電力増幅器の直列共振回路7を複数個並列接続し、それぞれの直列共振回路7を構成するインダクタ8およびキャパシタ9に異なる値を設定することで、それぞれ異なる複数の共振周波数を持たせたものである。
Embodiment 2. FIG.
FIG. 2 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 2 of the present invention.
In the series resonant circuit 10 of the second embodiment, a plurality of series resonant circuits 7 of the high-frequency power amplifier according to the first embodiment are connected in parallel, and the inductor 8 and the capacitor 9 constituting each series resonant circuit 7 have different values. Is set to have a plurality of different resonance frequencies.

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態2は、このような場合に、複数の送信帯周波数に対して複数の受信帯およびその他の周波数バンドにおける帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In this case, the second embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.

 この実施の形態2は、前記実施の形態1とは接続される直列共振回路10のみが異なり、前記実施の形態1で得られる効果に加えて、さらに、並列接続された直列共振回路10が送信帯周波数と複数の帯域外周波数との複数の差周波で共振周波数を持つようにすることで、バイアス回路6で発生した複数の差周波をもつ雑音を複数の直列共振回路10を介してグランドに流し、高周波信号増幅用トランジスタ3への入力を抑制する。 The second embodiment is different from the first embodiment only in the series resonance circuit 10 connected. In addition to the effects obtained in the first embodiment, the series resonance circuit 10 connected in parallel further transmits. By having resonance frequencies at a plurality of difference frequencies between a band frequency and a plurality of out-of-band frequencies, noise having a plurality of difference frequencies generated by the bias circuit 6 is grounded via a plurality of series resonance circuits 10. The input to the high frequency signal amplification transistor 3 is suppressed.

 また、前記実施の形態1と同様に、それぞれのインダクタ8のインダクタンスを、高周波増幅用トランジスタ3の入力インピーダンスに対して直列共振回路10のインピーダンスを十分高くなるように設定することで、送信帯の信号が直列共振回路10を介してグランドへ流れるのを抑制する。 Similarly to the first embodiment, the inductance of each inductor 8 is set so that the impedance of the series resonant circuit 10 is sufficiently higher than the input impedance of the high-frequency amplification transistor 3. The signal is prevented from flowing to the ground via the series resonant circuit 10.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、複数の周波数バンドにおける帯域外雑音レベルを低減することが可能となる。 As described above, the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.

 以上のように、この実施の形態2によれば、直列共振回路10は、複数個並列接続され、それぞれが異なる共振周波数をもつものを備えた。
 よって、並列接続された直列共振回路10が、送信帯周波数と複数の帯域外周波数との複数の差周波で共振周波数を持つようにすることで、バイアス回路6で発生した複数の差周波をもつ雑音を複数の直列共振回路10を介してグランドに流し、高周波信号増幅用トランジスタへ3の入力を抑制することができる。
As described above, according to the second embodiment, a plurality of series resonant circuits 10 are connected in parallel, each having a different resonant frequency.
Therefore, the series resonance circuit 10 connected in parallel has a plurality of difference frequencies generated by the bias circuit 6 by having resonance frequencies at a plurality of difference frequencies between the transmission band frequency and the plurality of out-of-band frequencies. Noise can be caused to flow through the plurality of series resonance circuits 10 to the ground, and input to the high frequency signal amplifying transistor 3 can be suppressed.

実施の形態3.
 図3にこの発明による実施の形態3の高周波電力増幅器の構成図を示す。
 この実施の形態3の直列共振回路11は、前記実施の形態1による高周波電力増幅器の直列共振回路7を構成するキャパシタ9の代わりに、それぞれスイッチ12を介して並列接続される複数のキャパシタ9を備え、スイッチ12のオン/オフにより、キャパシタ9の数または大きさが切り替えられることで、共振周波数を可変にしたものである。
Embodiment 3 FIG.
FIG. 3 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 3 of the present invention.
The series resonant circuit 11 of the third embodiment includes a plurality of capacitors 9 connected in parallel via switches 12 instead of the capacitors 9 constituting the series resonant circuit 7 of the high frequency power amplifier according to the first embodiment. The resonance frequency is made variable by switching the number or size of the capacitors 9 by turning on / off the switch 12.

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態3は、このような場合に、複数の送信帯周波数に対して複数の受信帯およびその他の周波数バンドにおける帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In this case, the third embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.

 この実施の形態3は、前記実施の形態1とは接続される直列共振回路11のみが異なり、前記実施の形態1で得られる効果に加えて、さらに、雑音レベルを低減したい帯域外の周波数バンドに応じて直列共振回路11のキャパシタ9の値を切替えることで、バイアス回路6で発生した複数の差周波をもつ雑音を直列共振回路11を介してグランドに流し、高周波信号増幅用トランジスタ3への入力を抑制する。 The third embodiment is different from the first embodiment only in the series resonant circuit 11 that is connected. In addition to the effects obtained in the first embodiment, the frequency band outside the band where the noise level is desired to be further reduced. By switching the value of the capacitor 9 of the series resonance circuit 11 according to the above, noise having a plurality of difference frequencies generated in the bias circuit 6 is caused to flow to the ground via the series resonance circuit 11, and is supplied to the high frequency signal amplifying transistor 3. Suppress input.

 また、前記実施の形態1と同様に、インダクタ8のインダクタンスを、高周波信号増幅用トランジスタ3の入力インピーダンスに対して直列共振回路11のインピーダンスを十分高くなるように設定することで、送信帯の信号が直列共振回路11を介してグランドへ流れるのを抑制する。 Similarly to the first embodiment, the inductance of the inductor 8 is set so that the impedance of the series resonant circuit 11 is sufficiently higher than the input impedance of the high-frequency signal amplification transistor 3, so that the signal in the transmission band is set. Is prevented from flowing to the ground via the series resonant circuit 11.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、雑音を低減したい周波数バンドに応じて帯域外雑音レベルを低減することが可能となる。
 また、この実施の形態3は、前記実施の形態2に対して、サイズの大きいインダクタ8を共通化し、小型なスイッチ12により実現できるため、小型化が可能である。
As described above, by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain, the out-of-band noise level according to the frequency band in which the noise is desired to be reduced. Can be reduced.
In addition, the third embodiment can be downsized because the inductor 8 having a large size is shared with the second embodiment and can be realized by the small switch 12.

 以上のように、この実施の形態3によれば、直列共振回路11のキャパシタ9は、それぞれがスイッチ12を介して複数個並列接続され、スイッチ12のオン/オフにより、キャパシタ9が切り替えられ、直列共振回路11の共振周波数が変化するものを備えた。
 よって、雑音レベルを低減したい帯域外の周波数バンドに応じて直列共振回路11のキャパシタ9の値を切替えることで、バイアス回路6で発生した複数の差周波をもつ雑音を直列共振回路11を介してグランドに流し、高周波信号増幅用トランジスタ3への入力を抑制することができる。
As described above, according to the third embodiment, a plurality of capacitors 9 of the series resonant circuit 11 are connected in parallel via the switch 12, and the capacitor 9 is switched by turning on / off the switch 12. A circuit in which the resonance frequency of the series resonance circuit 11 is changed is provided.
Therefore, by switching the value of the capacitor 9 of the series resonance circuit 11 according to the frequency band outside the band where the noise level is desired to be reduced, the noise having a plurality of difference frequencies generated in the bias circuit 6 is passed through the series resonance circuit 11. It is possible to suppress the input to the high-frequency signal amplification transistor 3 by flowing to the ground.

実施の形態4.
 図4にこの発明による実施の形態4の高周波電力増幅器の構成図を示す。
 この実施形態4では、前記実施の形態1による高周波電力増幅器の直列共振回路7の代わりに、高周波信号増幅用トランジスタ3とバイアス回路6との間に直列接続され、インダクタ14およびキャパシタ15の並列接続からなる並列共振回路13を備える。
Embodiment 4 FIG.
FIG. 4 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 4 of the present invention.
In the fourth embodiment, instead of the series resonant circuit 7 of the high frequency power amplifier according to the first embodiment, the high frequency signal amplifying transistor 3 and the bias circuit 6 are connected in series, and the inductor 14 and the capacitor 15 are connected in parallel. A parallel resonant circuit 13 is provided.

 なお、並列共振回路13を構成するインダクタ14は、スパイラルインダクタもしくはチップインダクタにより形成され、キャパシタ15は、MIMキャパシタもしくはチップコンデンサにより形成される。 The inductor 14 constituting the parallel resonance circuit 13 is formed by a spiral inductor or a chip inductor, and the capacitor 15 is formed by an MIM capacitor or a chip capacitor.

 この実施の形態4では、並列共振回路13の共振周波数が差周波付近となるようにインダクタ14およびキャパシタ15の値を設定することで、差周波における並列共振回路13のインピーダンスを高くする。
 これにより、差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
In the fourth embodiment, the values of the inductor 14 and the capacitor 15 are set so that the resonance frequency of the parallel resonance circuit 13 is in the vicinity of the difference frequency, thereby increasing the impedance of the parallel resonance circuit 13 at the difference frequency.
As a result, noise having a difference frequency is prevented from being input to the high frequency signal amplification transistor 3.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、帯域外雑音レベルの低減が可能となる。 As described above, the out-of-band noise level can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain.

 なお、2段以上の高周波信号増幅用トランジスタ3で構成される多段増幅器の場合には、いずれかの増幅段、もしくは全ての増幅段のバイアス回路6と高周波信号増幅用トランジスタ3との間に並列共振回路13を接続しても良い。
 特に1段目の高周波信号増幅用トランジスタ3において生じる雑音については、後段で増幅されるため、出力される帯域外雑音に対する影響が大きい。
 よって、1段目に並列共振回路13を接続した場合に得られる帯域外雑音レベルの低減効果は大きく、また、接続する並列共振回路13の数を削減できるため、小型化が可能である。
 一方、最終段においては高効率を実現するためにバックオフの小さな出力で使用されるため、歪みが大きくなりミキシングによる帯域外雑音が発生しやすい。
 よって、最終段に並列共振回路13を接続した場合に得られる帯域外雑音レベルの低減効果も大きく、また、接続する並列共振回路13の数を削減できるため、小型化が可能である。
In the case of a multi-stage amplifier including two or more stages of high-frequency signal amplification transistors 3, a parallel connection between the bias circuit 6 of any amplification stage or all amplification stages and the high-frequency signal amplification transistors 3 is performed. A resonance circuit 13 may be connected.
In particular, the noise generated in the first-stage high-frequency signal amplifying transistor 3 is amplified in the subsequent stage, and thus has a great influence on the output out-of-band noise.
Therefore, the effect of reducing the out-of-band noise level obtained when the parallel resonance circuit 13 is connected to the first stage is great, and the number of parallel resonance circuits 13 to be connected can be reduced, and the size can be reduced.
On the other hand, in the final stage, since it is used with an output with a small back-off in order to realize high efficiency, distortion becomes large and out-of-band noise due to mixing tends to occur.
Therefore, the effect of reducing the out-of-band noise level obtained when the parallel resonance circuit 13 is connected to the final stage is great, and the number of parallel resonance circuits 13 to be connected can be reduced, and the size can be reduced.

 また、インダクタ14にスパイラルインダクタを用いることで小型化が可能となる。
 一方、チップインダクタを用いることで低損失となるため、送信帯利得の低下を抑制する効果が得られる。
 キャパシタ15については、必要な容量値が小さい場合にはMIMキャパシタを用いることで小型化が可能となる。
 一方、チップコンデンサを用いることで大きなキャパシタンスを実現できるため、差周波が低い場合にも対応が可能となる。
Further, the use of a spiral inductor for the inductor 14 enables miniaturization.
On the other hand, since the loss is reduced by using the chip inductor, an effect of suppressing the decrease in the transmission band gain can be obtained.
The capacitor 15 can be miniaturized by using an MIM capacitor when the required capacitance value is small.
On the other hand, since a large capacitance can be realized by using a chip capacitor, it is possible to cope with a case where the difference frequency is low.

 以上のように、この実施の形態4によれば、高周波信号増幅用トランジスタ3とバイアス回路6との間に直列接続され、インダクタ14およびキャパシタ15を含む並列共振回路13を備えた。
 よって、バイアス回路6において発生する差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制することで、送信帯利得を低下させることなく、帯域外雑音を抑制することができる。
As described above, according to the fourth embodiment, the parallel resonant circuit 13 including the inductor 14 and the capacitor 15 is provided in series between the high-frequency signal amplification transistor 3 and the bias circuit 6.
Therefore, by suppressing the noise having the difference frequency generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3, the out-of-band noise can be suppressed without reducing the transmission band gain.

 また、この実施の形態4によれば、高周波信号増幅用トランジスタ3は、2段以上からなる多段増幅器であり、並列共振回路13は、1段目の高周波信号増幅用トランジスタ3とバイアス回路6との間に直列接続されるものを備えた。
 よって、1段目に並列共振回路13を接続した場合に得られる帯域外雑音レベルの低減効果は大きく、また、接続する並列共振回路13の数を削減できるため、小型化を可能とすることができる。
Further, according to the fourth embodiment, the high-frequency signal amplification transistor 3 is a multistage amplifier having two or more stages, and the parallel resonance circuit 13 includes the first-stage high-frequency signal amplification transistor 3 and the bias circuit 6. The one connected in series was provided.
Therefore, the effect of reducing the out-of-band noise level obtained when the parallel resonant circuit 13 is connected to the first stage is great, and the number of parallel resonant circuits 13 to be connected can be reduced, thereby enabling downsizing. it can.

実施の形態5.
 図5にこの発明による実施の形態5の高周波電力増幅器の構成図を示す。
 この実施の形態5は、前記実施の形態4による高周波電力増幅器の並列共振回路13を複数個直列接続し、それぞれの並列共振回路を構成するインダクタ14およびキャパシタ15に異なる値を設定することで、それぞれ異なる複数の共振周波数を持たせたものである。
Embodiment 5 FIG.
FIG. 5 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 5 of the present invention.
In the fifth embodiment, a plurality of parallel resonant circuits 13 of the high-frequency power amplifier according to the fourth embodiment are connected in series, and different values are set for the inductor 14 and the capacitor 15 constituting each parallel resonant circuit. Each has a plurality of different resonance frequencies.

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態5は、このような場合に、複数の送信帯周波数に対して複数の受信帯およびその他の周波数バンドにおける帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In such a case, the fifth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.

 この実施の形態5は、前記実施の形態4とは接続される並列共振回路16のみが異なり、前記実施の形態4で得られる効果に加えて、さらに、直列接続された並列共振回路16が送信帯周波数と複数の帯域外周波数との複数の差周波で共振周波数を持つようにすることで、複数の差周波における並列共振回路16のインピーダンスを高くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
The fifth embodiment is different from the fourth embodiment only in the parallel resonance circuit 16 connected. In addition to the effects obtained in the fourth embodiment, the parallel resonance circuit 16 connected in series further transmits. The impedance of the parallel resonant circuit 16 at a plurality of difference frequencies is increased by having resonance frequencies at a plurality of difference frequencies between the band frequency and the plurality of out-of-band frequencies.
As a result, the noise having a plurality of difference frequencies generated in the bias circuit 6 is suppressed from being input to the high frequency signal amplification transistor 3.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、複数の周波数バンドにおける帯域外雑音レベルを低減することが可能となる。 As described above, the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.

 以上のように、この実施の形態5によれば、並列共振回路16は、複数個直列接続され、それぞれが異なる共振周波数をもつものを備えた。
 よって、直列接続された並列共振回路16が、送信帯周波数と複数の帯域外周波数との複数の差周波で共振周波数を持つようにすることで、複数の差周波における並列共振回路16のインピーダンスを高くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制することができる。
As described above, according to the fifth embodiment, a plurality of parallel resonant circuits 16 are connected in series, each having a different resonant frequency.
Therefore, the parallel resonance circuit 16 connected in series has resonance frequencies at a plurality of difference frequencies between the transmission band frequency and the plurality of out-of-band frequencies, thereby reducing the impedance of the parallel resonance circuit 16 at the plurality of difference frequencies. Make it high.
Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3.

実施の形態6.
 図6にこの発明による実施の形態6の高周波電力増幅器の構成図を示す。
 この実施の形態6は、前記実施の形態4による高周波電力増幅器の並列共振回路13を構成するキャパシタ15の代わりに、それぞれがスイッチ18を介して並列接続される複数のキャパシタ15を備え、スイッチ18のオン/オフにより、キャパシタ15の数または大きさを切り替えることで、共振周波数を可変にしたものである。
Embodiment 6 FIG.
FIG. 6 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 6 of the present invention.
In the sixth embodiment, instead of the capacitor 15 constituting the parallel resonant circuit 13 of the high-frequency power amplifier according to the fourth embodiment, a plurality of capacitors 15 each connected in parallel via a switch 18 are provided. The resonance frequency is made variable by switching the number or size of the capacitors 15 by turning on / off.

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態6は、このような場合に、複数の送信帯周波数に対して複数の受信帯およびその他の周波数バンドにおける帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In this case, the sixth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands with respect to a plurality of transmission band frequencies.

 この実施の形態6は、前記実施の形態4とは接続される並列共振回路17のみが異なり、前記実施の形態4で得られる効果に加えて、さらに、雑音レベルを低減したい帯域外の周波数バンドに応じて並列共振回路17のキャパシタ15の値を切替えることで、複数の周波数バンドに対して並列共振回路17のインピーダンスを高くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
The sixth embodiment is different from the fourth embodiment only in the parallel resonant circuit 17 connected. In addition to the effects obtained in the fourth embodiment, the frequency band outside the band where the noise level is desired to be further reduced. By switching the value of the capacitor 15 of the parallel resonance circuit 17 according to the above, the impedance of the parallel resonance circuit 17 is increased for a plurality of frequency bands.
As a result, the noise having a plurality of difference frequencies generated in the bias circuit 6 is suppressed from being input to the high frequency signal amplification transistor 3.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、雑音を低減したい周波数バンドごとに帯域外雑音レベルを低減することが可能となる。
 また、この実施の形態6は、前記実施の形態5に対して、サイズの大きいインダクタ14を共通化し、小型なスイッチ18により実現できるため、小型化が可能である。
As described above, by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high frequency signal amplification transistor 3 without reducing the transmission band gain, the out-of-band noise level can be set for each frequency band in which noise is desired to be reduced. It becomes possible to reduce.
Further, the sixth embodiment can be miniaturized because the inductor 14 having a large size is shared with the fifth embodiment and can be realized by the small switch 18.

 以上のように、この実施の形態6によれば、並列共振回路17のキャパシタ15は、それぞれがスイッチ18を介して複数個並列接続され、スイッチ18のオン/オフにより、キャパシタ15が切り替えられ、並列共振回路17の共振周波数が変化するものを備えた。
 よって、雑音レベルを低減したい帯域外の周波数バンドに応じて並列共振回路17のキャパシタの値を切替えることで、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制することができる。
As described above, according to the sixth embodiment, a plurality of capacitors 15 of the parallel resonant circuit 17 are connected in parallel via the switch 18, and the capacitor 15 is switched by turning on / off the switch 18. The parallel resonance circuit 17 is provided with a variable resonance frequency.
Therefore, by switching the value of the capacitor of the parallel resonant circuit 17 according to the frequency band outside the band where the noise level is desired to be reduced, noise having a plurality of difference frequencies generated in the bias circuit 6 is input to the high frequency signal amplifying transistor 3. Can be suppressed.

実施の形態7.
 図7にこの発明による実施の形態7の高周波電力増幅器の構成図を示す。
 この実施の形態7の直列共振回路19は、前記実施の形態1による高周波電力増幅器の直列共振回路7に、抵抗20を直列接続したもので、直列共振回路19のインピーダンスをより広い周波数帯域対して低くしたものである。
Embodiment 7 FIG.
FIG. 7 shows a configuration diagram of a high-frequency power amplifier according to Embodiment 7 of the present invention.
The series resonant circuit 19 of the seventh embodiment is obtained by connecting a resistor 20 in series to the series resonant circuit 7 of the high-frequency power amplifier according to the first embodiment. The impedance of the series resonant circuit 19 is set to a wider frequency band. It is a low one.

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態7は、このような場合に、複数の送信帯周波数において複数の受信帯およびその他の周波数バンドの帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In this case, the seventh embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands in a plurality of transmission band frequencies.

 この実施の形態7は、前記実施の形態1とは接続される直列共振回路19のみが異なり、前記実施の形態1で得られる効果に加えて、さらに、抵抗20を含む直列共振回路19の共振周波数が、周波数の近い複数の差周波の中間周波数となるようにインダクタ8およびキャパシタ9の値を設定することで、複数の差周波における直列共振回路19のインピーダンスを低くする。
 これにより、複数の差周波をもつ雑音を直列共振回路19を介してグランドへ流すことで、複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
The seventh embodiment is different from the first embodiment only in the series resonance circuit 19 that is connected. In addition to the effects obtained in the first embodiment, the resonance of the series resonance circuit 19 including the resistor 20 is further obtained. By setting the values of the inductor 8 and the capacitor 9 so that the frequency becomes an intermediate frequency between the plurality of difference frequencies close to the frequency, the impedance of the series resonance circuit 19 at the plurality of difference frequencies is lowered.
Thus, noise having a plurality of difference frequencies is caused to flow to the ground via the series resonance circuit 19, thereby suppressing the noise having the plurality of difference frequencies from being input to the high frequency signal amplification transistor 3.

 また、前記実施の形態1と同様に、インダクタ8のインダクタンスを、高周波増幅用トランジスタ3の入力インピーダンスに対して直列共振回路19のインピーダンスを十分高くなるように設定することで、送信帯の信号が直列共振回路19を介してグランドへ流れるのを抑制する。 Similarly to the first embodiment, by setting the inductance of the inductor 8 so that the impedance of the series resonance circuit 19 is sufficiently higher than the input impedance of the high frequency amplification transistor 3, the signal in the transmission band can be obtained. The flow to the ground via the series resonance circuit 19 is suppressed.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、複数の周波数バンドにおける帯域外雑音レベルを低減することが可能となる。
 また、この実施の形態7は、前記実施の形態2および前記実施の形態3に対して、複数のインダクタ8およびキャパシタ9を共通化できるため、小型化が可能である。
As described above, the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.
In addition, the seventh embodiment can be downsized because a plurality of inductors 8 and capacitors 9 can be used in common with the second and third embodiments.

 以上のように、この実施の形態7によれば、直列共振回路19は、インダクタ8およびキャパシタ9に、直列接続された抵抗20を含むものを備えた。
 よって、抵抗20を含む直列共振回路19の共振周波数が、周波数の近い複数の差周波の中間周波数となるようにインダクタ8およびキャパシタ9の値を設定することで、複数の差周波における直列共振回路19のインピーダンスを低くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音を直列共振回路19を介してグランドに流すことで、高周波信号増幅用トランジスタ3へ入力されるのを抑制することができる。
As described above, according to the seventh embodiment, the series resonance circuit 19 includes the inductor 8 and the capacitor 9 including the resistor 20 connected in series.
Therefore, by setting the values of the inductor 8 and the capacitor 9 so that the resonance frequency of the series resonance circuit 19 including the resistor 20 becomes an intermediate frequency between the plurality of difference frequencies close to each other, the series resonance circuit at the plurality of difference frequencies. 19 Impedance is lowered.
Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high-frequency signal amplification transistor 3 by flowing to the ground via the series resonance circuit 19.

実施の形態8.
 図8にこの発明による実施の形態8の高周波電力増幅器の構成図を示す。
 この実施の形態8は、前記実施の形態4による高周波電力増幅器の並列共振回路13に抵抗22を直列接続したもので、並列共振回路21のインピーダンスをより広い周波数帯域に対して高くしたものである。
Embodiment 8 FIG.
FIG. 8 shows a configuration diagram of a high-frequency power amplifier according to an eighth embodiment of the present invention.
In the eighth embodiment, a resistor 22 is connected in series to the parallel resonant circuit 13 of the high-frequency power amplifier according to the fourth embodiment, and the impedance of the parallel resonant circuit 21 is increased over a wider frequency band. .

 送信帯と受信帯およびその他の周波数バンドとの差周波が複数ある場合や、送信帯周波数によって差周波が異なる場合がある。
 この実施の形態8は、このような場合に、複数の送信帯周波数において複数の受信帯およびその他の周波数バンドの帯域外雑音を低減するものである。
There may be a case where there are a plurality of difference frequencies between the transmission band, the reception band, and other frequency bands, or the difference frequency may differ depending on the transmission band frequency.
In this case, the eighth embodiment reduces out-of-band noise in a plurality of reception bands and other frequency bands in a plurality of transmission band frequencies.

 この実施の形態8は、前記実施の形態4とは接続される並列共振回路21のみが異なり、前記実施の形態4で得られる効果に加えて、さらに、抵抗22を含む並列共振回路21の共振周波数が、周波数の近い複数の差周波の中間周波数となるように、インダクタ14およびキャパシタ15の値を設定することで、複数の差周波における並列共振回路21のインピーダンスを高くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制する。
The eighth embodiment is different from the fourth embodiment only in the connected parallel resonance circuit 21. In addition to the effects obtained in the fourth embodiment, the resonance of the parallel resonance circuit 21 including the resistor 22 is further obtained. By setting the values of the inductor 14 and the capacitor 15 so that the frequency becomes an intermediate frequency of the plurality of difference frequencies close to the frequency, the impedance of the parallel resonant circuit 21 at the plurality of difference frequencies is increased.
As a result, the noise having a plurality of difference frequencies generated in the bias circuit 6 is suppressed from being input to the high frequency signal amplification transistor 3.

 以上により、送信帯利得を低下させることなく、バイアス回路6から高周波信号増幅用トランジスタ3への差周波をもつ雑音の入力を抑制することで、複数の周波数バンドにおける帯域外雑音レベルを低減することが可能となる。
 また、この実施の形態8は、前記実施の形態5および前記実施の形態6に対して、複数のインダクタ14およびキャパシタ15を共通化できるため、小型化が可能である。
As described above, the out-of-band noise level in a plurality of frequency bands can be reduced by suppressing the input of noise having a difference frequency from the bias circuit 6 to the high-frequency signal amplification transistor 3 without reducing the transmission band gain. Is possible.
Further, in the eighth embodiment, since the plurality of inductors 14 and the capacitors 15 can be made common to the fifth and sixth embodiments, the size can be reduced.

 以上のように、この実施の形態8によれば、並列共振回路21は、インダクタ14およびキャパシタ15に、直列接続された抵抗22を含むものを備えた。
 よって、抵抗22を含む並列共振回路21の共振周波数が、周波数の近い複数の差周波の中間周波数となるようにインダクタ14およびキャパシタ15の値を設定することで、複数の差周波における並列共振回路21のインピーダンスを高くする。
 これにより、バイアス回路6で発生した複数の差周波をもつ雑音が高周波信号増幅用トランジスタ3へ入力されるのを抑制することができる。
As described above, according to the eighth embodiment, the parallel resonant circuit 21 includes the inductor 14 and the capacitor 15 including the resistor 22 connected in series.
Therefore, by setting the values of the inductor 14 and the capacitor 15 so that the resonance frequency of the parallel resonance circuit 21 including the resistor 22 becomes an intermediate frequency of the plurality of difference frequencies close to each other, the parallel resonance circuit at the plurality of difference frequencies Increase the impedance of 21.
Thereby, it is possible to suppress the noise having a plurality of difference frequencies generated in the bias circuit 6 from being input to the high frequency signal amplification transistor 3.

 なお、前記実施の形態1から前記実施の形態8に示した高周波電力増幅器は、電力増幅する複数の送信帯域間に受信帯域を含むような広帯域マルチバンド電力増幅器に適用することができる。 The high-frequency power amplifiers shown in the first to eighth embodiments can be applied to a wideband multiband power amplifier that includes a reception band between a plurality of transmission bands for power amplification.

 なお、本願発明はその発明の範囲内において、各実施の形態の自由な組み合わせ、あるいは各実施の形態の任意の構成要素の変形、もしくは各実施の形態において任意の構成要素の省略が可能である。 In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

 以上のように、この発明に係る高周波電力増幅器は、高周波信号増幅用トランジスタ3とバイアス回路6との間に一端が接続されると共に他端がグランド接続され、インダクタ8およびキャパシタ9を含む直列共振回路7を備えるように構成したので、広帯域マルチバンド電力増幅器に用いるのに適している。 As described above, in the high frequency power amplifier according to the present invention, one end is connected between the high frequency signal amplifying transistor 3 and the bias circuit 6 and the other end is connected to the ground, and the series resonance including the inductor 8 and the capacitor 9 is performed. Since the circuit 7 is provided, it is suitable for use in a wideband multiband power amplifier.

 1 入力端子、2 入力整合回路、3 高周波信号増幅用トランジスタ、4 出力整合回路、5 出力端子、6 バイアス回路、7,10,11,19 直列共振回路、8,14 インダクタ、9,15 キャパシタ、12,18 スイッチ、13,16,17,21 並列共振回路、20,22 抵抗。 1 input terminal, 2 input matching circuit, 3 high frequency signal amplification transistor, 4 output matching circuit, 5 output terminal, 6 bias circuit, 7, 10, 11, 19 series resonance circuit, 8, 14 inductor, 9, 15 capacitor, 12, 18 switch, 13, 16, 17, 21 parallel resonant circuit, 20, 22 resistance.

Claims (19)

 高周波信号を増幅する高周波信号増幅用トランジスタと、
 前記高周波信号増幅用トランジスタの高周波信号入力側にバイアスを供給するバイアス回路と、
 前記高周波信号増幅用トランジスタと前記バイアス回路との間に一端が接続されると共に他端が接地され、インダクタおよびキャパシタを含む直列共振回路と、
を備えた高周波電力増幅器。
A high frequency signal amplification transistor for amplifying the high frequency signal;
A bias circuit for supplying a bias to the high-frequency signal input side of the high-frequency signal amplification transistor;
A series resonant circuit including one end connected between the high frequency signal amplification transistor and the bias circuit and the other end grounded, including an inductor and a capacitor,
High frequency power amplifier with
 前記直列共振回路は、
 複数個並列接続され、それぞれが異なる共振周波数をもつことを特徴とする請求項1記載の高周波電力増幅器。
The series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein a plurality of the high frequency power amplifiers are connected in parallel, and each has a different resonance frequency.
 前記直列共振回路のキャパシタは、
 それぞれがスイッチを介して複数個並列接続されることを特徴とする請求項1記載の高周波電力増幅器。
The capacitor of the series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein a plurality of each are connected in parallel via a switch.
 前記スイッチのオン/オフにより、前記キャパシタが切り替えられ、前記直列共振回路の共振周波数が変化することを特徴とする請求項3記載の高周波電力増幅器。 4. The high-frequency power amplifier according to claim 3, wherein the capacitor is switched by turning on / off the switch to change a resonance frequency of the series resonance circuit.  前記インダクタのインダクタンスをL[H]、
 前記高周波信号増幅用トランジスタにより増幅される高周波信号の周波数をfRF[Hz]、
 前記高周波信号増幅用トランジスタの入力インピーダンスをRintr[Ω]とした場合に、
 L>5×Rintr/2π・fRF
であることを特徴とする請求項1記載の高周波電力増幅器。
The inductance of the inductor is L [H],
The frequency of the high frequency signal amplified by the high frequency signal amplifying transistor is fRF [Hz],
When the input impedance of the high frequency signal amplification transistor is Rintr [Ω],
L> 5 × Rintr / 2π · fRF
The high-frequency power amplifier according to claim 1, wherein
 前記直列共振回路は、
 インダクタおよびキャパシタに、直列接続された抵抗を含むことを特徴とする請求項1記載の高周波電力増幅器。
The series resonant circuit is:
The high-frequency power amplifier according to claim 1, wherein the inductor and the capacitor include a resistor connected in series.
 高周波信号を増幅する高周波信号増幅用トランジスタと、
 前記高周波信号増幅用トランジスタの高周波信号入力側にバイアスを供給するバイアス回路と、
 前記高周波信号増幅用トランジスタと前記バイアス回路との間に直列接続され、インダクタおよびキャパシタを含む並列共振回路と、
を備えた高周波電力増幅器。
A high frequency signal amplification transistor for amplifying the high frequency signal;
A bias circuit for supplying a bias to the high-frequency signal input side of the high-frequency signal amplification transistor;
A parallel resonant circuit connected in series between the high-frequency signal amplification transistor and the bias circuit, and including an inductor and a capacitor;
High frequency power amplifier with
 前記並列共振回路は、
 複数個直列接続され、それぞれが異なる共振周波数をもつことを特徴とする請求項7記載の高周波電力増幅器。
The parallel resonant circuit is:
8. The high-frequency power amplifier according to claim 7, wherein a plurality of the high-frequency power amplifiers are connected in series, each having a different resonance frequency.
 前記並列共振回路のキャパシタは、
 それぞれがスイッチを介して複数個並列接続されることを特徴とする請求項7記載の高周波電力増幅器。
The capacitor of the parallel resonant circuit is:
8. The high frequency power amplifier according to claim 7, wherein a plurality of each are connected in parallel via a switch.
 前記スイッチのオン/オフにより、前記キャパシタが切り替えられ、前記並列共振回路の共振周波数が変化することを特徴とする請求項9記載の高周波電力増幅器。 10. The high frequency power amplifier according to claim 9, wherein the capacitor is switched by turning on / off the switch to change a resonance frequency of the parallel resonance circuit.  前記並列共振回路は、
 インダクタおよびキャパシタに、直列接続された抵抗を含むことを特徴とする請求項7記載の高周波電力増幅器。
The parallel resonant circuit is:
8. The high frequency power amplifier according to claim 7, further comprising a resistor connected in series with the inductor and the capacitor.
 前記高周波信号増幅用トランジスタは、
 2段以上からなる多段増幅器であり、
 前記直列共振回路は、
 1段目の前記高周波信号増幅用トランジスタと前記バイアス回路との間に一端が接続されることを特徴とする請求項1記載の高周波電力増幅器。
The high-frequency signal amplification transistor includes:
A multistage amplifier consisting of two or more stages,
The series resonant circuit is:
The high-frequency power amplifier according to claim 1, wherein one end is connected between the first-stage high-frequency signal amplification transistor and the bias circuit.
 前記高周波信号増幅用トランジスタは、
 2段以上からなる多段増幅器であり、
 前記並列共振回路は、
 1段目の前記高周波信号増幅用トランジスタと前記バイアス回路との間に直列接続されることを特徴とする請求項7記載の高周波電力増幅器。
The high-frequency signal amplification transistor includes:
A multistage amplifier consisting of two or more stages,
The parallel resonant circuit is:
The high-frequency power amplifier according to claim 7, wherein the first-stage high-frequency signal amplification transistor and the bias circuit are connected in series.
 電力増幅する複数の送信帯域間に受信帯域を含むような広帯域マルチバンド電力増幅器であることを特徴とする請求項1記載の高周波電力増幅器。 2. The high frequency power amplifier according to claim 1, wherein the power amplifier is a wideband multiband power amplifier including a reception band between a plurality of transmission bands for power amplification.  電力増幅する複数の送信帯域間に受信帯域を含むような広帯域マルチバンド電力増幅器であることを特徴とする請求項7記載の高周波電力増幅器。 The high-frequency power amplifier according to claim 7, wherein the high-frequency power amplifier is a wideband multiband power amplifier including a reception band between a plurality of transmission bands for power amplification.  前記直列共振回路のインダクタは、
 スパイラルインダクタであることを特徴とする請求項1記載の高周波電力増幅器。
The inductor of the series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein the high frequency power amplifier is a spiral inductor.
 前記直列共振回路のインダクタは、
 チップインダクタであることを特徴とする請求項1記載の高周波電力増幅器。
The inductor of the series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein the high frequency power amplifier is a chip inductor.
 前記直列共振回路のキャパシタは、
 MIMキャパシタであることを特徴とする請求項1記載の高周波電力増幅器。
The capacitor of the series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein the high frequency power amplifier is an MIM capacitor.
 前記直列共振回路のキャパシタは、
 チップコンデンサであることを特徴とする請求項1記載の高周波電力増幅器。
The capacitor of the series resonant circuit is:
2. The high frequency power amplifier according to claim 1, wherein the high frequency power amplifier is a chip capacitor.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780735B1 (en) 2016-03-30 2017-10-03 Murata Manufacturing Co., Ltd. High-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication apparatus
JP2018061104A (en) * 2016-10-04 2018-04-12 株式会社村田製作所 Bias T circuit
JP2018101975A (en) * 2016-12-20 2018-06-28 エヌエックスピー ユーエスエイ インコーポレイテッドNXP USA,Inc. Multi-baseband termination components for rf power amplifier with enhanced video bandwidth
CN109075751A (en) * 2016-03-30 2018-12-21 株式会社村田制作所 High-frequency signal amplifying circuit, power amplifier module, front-end circuit and communication device
EP3534537A4 (en) * 2016-10-31 2020-07-01 Vanchip (Tianjin) Technology Co., Ltd. Radio frequency power amplifier for inhibiting harmonic wave and stray, chip and communication terminal
JPWO2020202532A1 (en) * 2019-04-04 2020-10-08
US10855235B2 (en) 2017-12-27 2020-12-01 Murata Manufacturing Co., Ltd. Power amplifier circuit
JPWO2022180658A1 (en) * 2021-02-24 2022-09-01

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685516U (en) * 1993-05-11 1994-12-06 日立電子株式会社 Trap circuit
JP2002171138A (en) * 2000-12-01 2002-06-14 Nec Corp Microwave power amplifier
JP2011530225A (en) * 2008-07-30 2011-12-15 クゥアルコム・インコーポレイテッド Drive amplifier having programmable output impedance adjustment circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685516U (en) * 1993-05-11 1994-12-06 日立電子株式会社 Trap circuit
JP2002171138A (en) * 2000-12-01 2002-06-14 Nec Corp Microwave power amplifier
JP2011530225A (en) * 2008-07-30 2011-12-15 クゥアルコム・インコーポレイテッド Drive amplifier having programmable output impedance adjustment circuit

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9780735B1 (en) 2016-03-30 2017-10-03 Murata Manufacturing Co., Ltd. High-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication apparatus
CN109075751A (en) * 2016-03-30 2018-12-21 株式会社村田制作所 High-frequency signal amplifying circuit, power amplifier module, front-end circuit and communication device
US10389310B2 (en) 2016-03-30 2019-08-20 Murata Manufacturing Co., Ltd. Radio-frequency signal amplifier circuit, power amplifier module, front-end circuit, and communication device
JP2018061104A (en) * 2016-10-04 2018-04-12 株式会社村田製作所 Bias T circuit
EP3534537A4 (en) * 2016-10-31 2020-07-01 Vanchip (Tianjin) Technology Co., Ltd. Radio frequency power amplifier for inhibiting harmonic wave and stray, chip and communication terminal
US10879850B2 (en) 2016-10-31 2020-12-29 Vanchip (Tianjin) Technology Co., Ltd. Radio frequency power amplifier for inhibiting harmonic wave and stray, chip and communication terminal
JP2018101975A (en) * 2016-12-20 2018-06-28 エヌエックスピー ユーエスエイ インコーポレイテッドNXP USA,Inc. Multi-baseband termination components for rf power amplifier with enhanced video bandwidth
JP7133305B2 (en) 2016-12-20 2022-09-08 エヌエックスピー ユーエスエイ インコーポレイテッド Multi-baseband termination component for RF power amplifier with enhanced video bandwidth
US10855235B2 (en) 2017-12-27 2020-12-01 Murata Manufacturing Co., Ltd. Power amplifier circuit
US11368131B2 (en) 2017-12-27 2022-06-21 Murata Manufacturing Co., Ltd. Power amplifier circuit
WO2020202532A1 (en) * 2019-04-04 2020-10-08 三菱電機株式会社 Power amplifier
CN113632374A (en) * 2019-04-04 2021-11-09 三菱电机株式会社 Power amplifier
JPWO2020202532A1 (en) * 2019-04-04 2020-10-08
JP7207522B2 (en) 2019-04-04 2023-01-18 三菱電機株式会社 power amplifier
JPWO2022180658A1 (en) * 2021-02-24 2022-09-01
WO2022180658A1 (en) * 2021-02-24 2022-09-01 三菱電機株式会社 Power amplifier
JP7559922B2 (en) 2021-02-24 2024-10-02 三菱電機株式会社 Power Amplifiers

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