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WO2014072410A1 - Puce de semi-conducteur optoélectronique et procédé de fabrication d'une puce de semi-conducteur optoélectronique - Google Patents

Puce de semi-conducteur optoélectronique et procédé de fabrication d'une puce de semi-conducteur optoélectronique Download PDF

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Publication number
WO2014072410A1
WO2014072410A1 PCT/EP2013/073277 EP2013073277W WO2014072410A1 WO 2014072410 A1 WO2014072410 A1 WO 2014072410A1 EP 2013073277 W EP2013073277 W EP 2013073277W WO 2014072410 A1 WO2014072410 A1 WO 2014072410A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
electrode
silver
contact point
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2013/073277
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German (de)
English (en)
Inventor
Alexander F. PFEUFFER
Lutz Höppel
Dominik Scholz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Publication of WO2014072410A1 publication Critical patent/WO2014072410A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies

Definitions

  • Optoelectronic semiconductor chip configured to generate electromagnetic radiation during operation.
  • the semiconductor chip is a light-emitting diode. In operation of the semiconductor chip is
  • the ⁇ generates near ultraviolet radiation, visible light or near-infrared radiation.
  • the ⁇ generates near ultraviolet radiation, visible light or near-infrared radiation.
  • the ⁇ generates near ultraviolet radiation, visible light or near-infrared radiation.
  • Semiconductor layer sequence includes an n-type layer and a p-type layer. Between the n-type Layer and the p-type layer is disposed an active zone. In the active zone, the radiation is generated during operation.
  • the active zone includes at least one pn junction and / or at least one quantum well structure.
  • the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
  • the semiconductor material is, for example, a nitride compound semiconductor material such as Al n In] __ n _ m Ga m N or a phosphide compound semiconductor material such as Al n In] __ n _ m Ga m P or an arsenide compound semiconductor material such as Al n In ] __ n _ m Ga m As, where each 0 ⁇ n ⁇ 1, 0 ⁇ m ⁇ 1 and n + m -S 1.
  • the semiconductor layer sequence may have dopants and additional constituents.
  • the semiconductor layer sequence is preferably based on AlInGaN.
  • Semiconductor chip a carrier.
  • the semiconductor layer sequence is arranged indirectly or directly on the carrier, wherein the p-conducting layer is preferably closer to the carrier than the n-conducting layer.
  • the semiconductor layer sequence is soldered onto the carrier.
  • the carrier may be different from a growth substrate of the preferably epitaxially grown semiconductor layer sequence.
  • the first electrode is configured to contact the n-type layer.
  • the first electrode is or is preferably based on one or more metals.
  • the second electrode is preferably based on one or more metals or consists of at least one metal. According to at least one embodiment, the
  • Semiconductor chip an electrical contact point, which is adapted for external electrical contacting of the second electrode.
  • the semiconductor chip is externally electrically contacted via the second electrode and the electrical contact point.
  • the electrical contact point in plan view of a
  • the main radiation side is
  • a carrier facing away from the main side of the semiconductor layer sequence For example, a carrier facing away from the main side of the semiconductor layer sequence.
  • the electrical contact point is on the same side of the carrier as the
  • the contact point is attached to one of the semiconductor layer sequence opposite bottom of the carrier and via an electrical
  • the first electrode Through contact with the semiconductor layer sequence facing side of the carrier is electrically connected. According to at least one embodiment, the first
  • Electrode on a flat first area and at least one inseiform second area.
  • the first electrode has a plurality of soap-shaped first regions.
  • the soap-shaped areas extend
  • the island-shaped region starting from the planar first region, extends through the second electrode, the p-conducting layer and the active zone into the n-conducting layer.
  • the p-type layer is in this case closer to the carrier and to the planar first region than the n-type layer.
  • the n-type and p-type layers are reversed in position.
  • the first electrode is then preferably shaped like the second electrode and vice versa.
  • Electrode as a current-carrying layer on a silver layer.
  • the silver layer is set to the
  • a portion of the silver layer is at a current distribution in the second
  • the silver layer is then not or only in a subordinate manner to the layer which is chiefly responsible for a lateral current distribution and further constituents of the second electrode contribute to a current distribution.
  • an average resistance along a lateral direction of the silver layer is at least a factor of 10 over all others
  • the silver layer is in direct contact with the semiconductor layer sequence.
  • the semiconductor layer sequence is in direct contact with the semiconductor layer sequence.
  • a layer for improving an electrical contact is attached, for example, a thin layer of a metal such as platinum or a thin layer of a transparent conductive oxide. In this case, a distance between the
  • Silver layer and the semiconductor layer sequence preferably at most 100 nm or 10 nm or 1 nm. According to at least one embodiment, the silver layer as a mirror for in the semiconductor layer sequence in
  • the silver layer has a reflectivity of at least 90% or at least 94% for the radiation generated in the semiconductor layer sequence.
  • the silver layer preferably reflects specularly and not diffusely.
  • the silver layer is formed comparatively thick. This may mean that a quotient of an average thickness of the silver layer and a mean edge length or an average diameter of the semiconductor layer sequence, seen in plan view,
  • the silver layer has an average thickness of at least 250 nm, in the event that the quotient amounts to at least 5 ⁇ 10 -4.
  • a thickness of the silver layer is preferably at least 80 nm or 150 nm or 200 nm. In at least one embodiment, FIG
  • optoelectronic semiconductor chip preferably a
  • Light emitting diode is, a semiconductor layer sequence with an n-type layer, a p-type layer and an active zone arranged therebetween.
  • Semiconductor layer sequence is arranged on a carrier.
  • a first electrode is arranged for contacting the n-type layer and a second electrode for contacting the p-type layer.
  • the first electrode has a flat first region and at least one second soap-shaped region.
  • the at least one island-shaped second region extends through the second electrode, the p-conducting layer and the active zone into the n-conducting layer.
  • the second electrode comprises as current-carrying
  • Layer a silver layer at least in part is located between the planar first region of the first electrode and the semiconductor layer sequence and that is a mirror.
  • a ratio of an average thickness of the silver layer and an average edge length of the semiconductor layer sequence is at least 80 nm is at least 2.5 x lO ⁇ unc ⁇ b e i.
  • Semiconductor chips such as light-emitting diode chips, require a sufficiently conductive layer for the second electrode for uniform current injection, in particular if the second electrode lies between the first electrode and the second electrode
  • a comparatively small, technically feasible layer thickness of the current spreading layer is one
  • This current spreading layer can also be called
  • Encapsulation of a silver mirror can be used.
  • Silver mirror and the gold layer to provide a diffusion barrier, in order to mix the two layers
  • the silver mirror is manufactured with a significantly greater thickness than necessary for an optical effect and serves as current-carrying layer. This is, especially in comparison to a gold layer as a current-carrying layer, a
  • the silver layer extends continuously and coherently to below the contact point. In other words, then overtops the silver layer.
  • Silver layer the active zone at least or only in the region of the contact point, seen in plan view of the main radiation side.
  • the silver layer is then not restricted to the active zone, seen in plan view.
  • the second electrode may be free or substantially free of gold.
  • the second electrode comprises a cover layer.
  • the cover layer is preferably located directly at the contact point and / or at the
  • the cover layer comprises or consists of one or more of the following materials: chromium, cobalt, platinum, ruthenium, tantalum, indium tin oxide, tantalum nitride, Titanium nitride, titanium tungsten nitride, zinc oxide, tin oxide, tungsten.
  • chromium, cobalt, platinum, ruthenium, tantalum, indium tin oxide, tantalum nitride, Titanium nitride, titanium tungsten nitride, zinc oxide, tin oxide, tungsten By using such materials for the cover layer, efficient encapsulation of the silver layer can be achieved. It is possible that the cover layer is formed from exactly one layer of constant material composition or that the cover layer has a layer stack.
  • an average thickness of the cover layer is at most 100% or at most 50% or at most 25% or at most 10% or at most 5% of the mean thickness of the silver layer. It is then the cover layer, compared to the silver layer, thin.
  • the silver layer extends as far as below the cover layer, viewed in plan view on the main radiation side. It is then the cover layer partially or completely between the
  • Cover layer partially between the semiconductor layer sequence and the silver mirror. It is possible that the cover layer contacts the semiconductor layer sequence in places or has a distance to the semiconductor layer sequence of at most 10 nm or at most 1 nm.
  • the cover layer is in an area adjacent to the active zone and / or adjacent to
  • an area fraction of the semiconductor layer sequence which, when viewed in plan view, covers the cover layer is at most 5% or 2%, based on the area of the semiconductor layer sequence and / or the active zone.
  • the cover layer preferably covers only a small part of a side of the silver layer facing away from the semiconductor layer sequence, for example at most 10% or at most 2%.
  • cover layer and the silver layer seen in plan view of the main radiation side, not. Then the cover layer and the silver layer only touch in one direction perpendicular to a direction of growth of the
  • the p-type layer extends below the electrical contact point, seen in plan view. It is then the p-type
  • the p-type layer in places between the electrical contact point and the second electrode.
  • the p-type layer completely covers the silver layer, seen in plan view. It preferably has the p-type layer larger lateral dimensions than the active zone.
  • the p-type layer in the region of the electrical contact point a Protective layer for the silver layer.
  • the n-type layer and the active zone at the electrical contact point are completely removed, in plan view of FIG.
  • the p-type layer between the electrical pad and the silver layer is preferably completely or partially obtained.
  • the p-type layer is re-doped at the electrical contact point. Due to the re-doping, the p-type layer has an n-type subregion. This portion is between the electrical contact point and the silver layer
  • the subarea can be complete or
  • the electrical insulating layer is, for example, a layer of a silicon oxide, a silicon nitride or an aluminum oxide.
  • the primer layer comprises or consists of one or more of the following materials: chromium, indium tin oxide, titanium, zinc oxide.
  • a thickness of the adhesion promoting layer is preferably at most 100 nm or at most 20 nm or at most 5 nm.
  • the insulating layer has, for example, a thickness of at least 25 nm or at least 100 nm and / or at most 500 nm or at most 2000 nm.
  • the planar first region of the first electrode is formed by a solder layer or by a solderable layer.
  • the carrier may be an electrically conductive carrier.
  • Silver layer and the electrical contact point in a common plane parallel to the active zone. It is possible that the pad does not protrude beyond the silver layer, away from the substrate. Alternatively or additionally, the cover layer is closer to the support than the electrical contact point and / or the silver layer.
  • the method comprises at least the following steps: A) growing the semiconductor layer sequence onto a growth substrate,
  • step F) the semiconductor layer sequence is removed as far as the p-conducting layer, from a side facing away from the carrier.
  • the p-type layer is completely retained, with a tolerance of, for example, at most 10% or at most 5% of the original thickness of the p-type layer. Partially removing the
  • Semiconductor layer sequence occurs approximately with an etching process, which is selective in terms of a conductivity type.
  • FIGS 1 to 9 and 11 are schematic sectional views of embodiments of optoelectronic semiconductor chips described herein.
  • Figure 10 is a schematic sectional view of a
  • the semiconductor chip 1 has a
  • the semiconductor layer sequence 3 comprises an n-type layer 31, a p-type layer 33 and an intermediate active zone 32.
  • the second electrode 5 includes a silver layer 51 which is adapted to a lateral current distribution and which has a comparatively large thickness. Furthermore, the second electrode 5 has a
  • the cover layer 52 on. Compared to the silver layer 51, the cover layer 52 is thin.
  • the first electrode 4 has a flat first region 41 and an inner second region 42 in the form of a soap. Starting from the first region 41, the second region 42 extends through the silver layer 51, the p-type layer 33 and the active region 32 into the n-type layer 31. Deviating from the illustration, the semiconductor chip 1 preferably has a plurality of Islands 42 on. A current flow thus takes place via the first region 41, the second region 42 and through the
  • an electrical contact point 6 is formed on the cover layer 52 of the second electrode 5.
  • the electrical contact point 6 is, for example, a bonding pad for the external electrical contacting of the semiconductor chip 1.
  • a further electrical contact point for contacting the first electrode 4 is not shown in the figures in order to simplify the illustration. Such a further contact point is located, for example, at one of
  • a roughening 8 is mounted on a remote from the carrier 2 main radiation side 80 of the semiconductor layer sequence 3 to improve light extraction.
  • the radiation main side 80 unlike the one shown, may be arranged downstream of a conversion means for the at least partial conversion of radiation generated in the active zone 32 into radiation of other wavelengths or else at least one optical element.
  • the first electrode 4 and the second electrode 5 are insulated from each other by an electrical insulating layer 71. At the main radiation side 80, on flanks of the
  • a further electrical insulating layer 72 is preferably attached. It is also optional, as in all others
  • the second electrode 5 extends in an approximately equal thickness in the lateral direction over the semiconductor layer sequence 3 and the electrical contact point 6.
  • the silver layer 51 is completely laterally and vertically surrounded by the insulating layer 71 and the cover layer 52 at the contact point 6.
  • a thickness of the cover layer 52 is, for example, to
  • the semiconductor chip 1 is produced in particular as follows: On a growth substrate, not shown
  • the cover layer 52 is preferably local
  • the silver layer 51 is patterned and recesses are produced in the semiconductor layer sequence 3 for the soap-like second regions 52.
  • the insulating layer 71 is applied and the first electrode 4, 41, 42 are formed. Thereafter, the carrier 2 by means of the flat first portion 41 at the
  • Semiconductor layer sequence 3 are attached. Subsequently, the growth substrate is removed and the
  • Semiconductor layer sequence 3 is approximately by etching
  • the electrical contact point 6 is generated, which contains, for example, gold, nickel, palladium and / or tin.
  • the cover layer 52 as in the exemplary embodiment according to FIG. 1, is located in places between the semiconductor layer sequence 3 and the silver layer 51a, 51b.
  • Silver layer near the pad 6 extends further into the sheet-like first region 41 as remaining regions 51a of the silver layer.
  • the silver layer 51a, 51b and the cover layer 52 have comparable thicknesses.
  • the silver layer 51 is preferably applied in front of the cover layer 52a, 52b. As in the case of FIG. 2, the silver layer does not project beyond the semiconductor layer sequence 3 in a lateral direction.
  • a partial region 52a of the cover layer extends further into the flat first region 41 as a partial region 52b of the cover layer directly at the contact point 6.
  • the p-type layer 33 preferably completely covers the silver layer 51, so that a
  • a thickness of the p-type layer 33 between the pad 6 and the silver layer 51 is, for example, at least 100 nm or at
  • the semiconductor layer sequence 3 is wet-chemically or dry-chemically etchable down to the p-type layer 33.
  • An end point detection of an etching process is preferably carried out optically, in particular with photoluminescence on the basis of the active zone 32. In the case of a non-selective etching process, the photoluminescence of the active zone 32 then disappears
  • the n-conducting layer 31 and the active zone 32 are through
  • the partial region 36 is preferably limited to the contact point 6, for example with a tolerance of at most 25% or at most 50% of the surface of the contact point 6.
  • the portion 36 may be surrounded all around by p-type regions of the p-type layer 33, in FIG.
  • the p-type layer 33 is complete and the n-type layer 31 is at least partially obtained.
  • n-conducting layer 31 is therefore p-conducting.
  • the n-type layer 31 in direct contact with the portion 36 is changed all around in a region 36a such that this region 36a acts as an electrical insulator.
  • Subarea 36 is preferably limited to the area of pad 6, for example with a tolerance of at most 25% or at most 50%.
  • the silver layer 51 extends continuously below the contact point 6.
  • the cover layer 52 is formed in a locally limited manner.
  • the cover layer 52 is designed such that it at least the later
  • Insulating layer 72 then removed and the electrical
  • the cover layer 52 and the silver layer 51 have approximately equal thicknesses.
  • FIG. 10 shows a modification of the semiconductor chip
  • the silver layer 51 is only
  • a current spreading in the lateral direction takes place via a current distribution layer 56 made of gold. Between the current distribution layer 56 and the silver layer 51 is not shown
  • Silver layer 51 according to the figures 1 to 7 and by the Cover layer 52 and / or the p-type layer 33 at the contact point 6, a structure of the second electrode 5 is simplified and a cost savings in terms of the material of the current distribution layer 51 can be achieved.
  • FIG. 11 shows a further exemplary embodiment of the invention
  • the outer insulating layers 71a, 71b located furthest from the substrate 2 optionally have different thicknesses, as is possible in all other exemplary embodiments. This is enough
  • Insulating layer 71b from the substrate 2, for example, only up to the semiconductor layer sequence 3 and thus laterally bounds the silver layer 51.
  • the silver layer 51 is first attached to the semiconductor layer sequence 3. Subsequently, the upper direction away from the substrate 2 away insulating layer 72a is applied and patterned. In this case, the upper insulating layer 72a has the same or a similar thickness as the cover layer 52, which overlaps with the silver layer 51 seen in plan view. Thereafter, the closer to the substrate 2 located, lower insulating layer 72b is applied.
  • Insulating layer 72a and into the lower insulating layer 72b is a planarization toward the substrate 2
  • the semiconductor layer sequence 3 is subsequently fastened to the substrate 2 by means of the areal area 41, in particular formed by a solder.
  • the invention described here is not by the

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Abstract

Dans au moins un mode de réalisation, la puce de semi-conducteur optoélectronique (1) comporte une succession de couches semi-conductrices (3) comprenant une couche conductrice de type n (31), une couche conductrice de type p (33) et une zone active (33) disposée entre lesdites couches. La succession de couches semi-conductrices (3) est disposée sur un substrat (2). Une première électrode (4) est configurée pour établir un contact électrique avec la couche conductrice de type n (31) et une seconde électrode (5) est configurée pour établir un contact électrique avec la couche conductrice de type p (33). Un point de contact électrique (6) servant à établir un contact électrique externe avec la seconde électrode (5) se trouve, vu de dessus, à côté de la zone active (32) et sur le même côté du substrat (2) que la succession de couches semi-conductrices (3). La première électrode (4) comporte une première zone plane (41) et au moins une seconde zone (42) en forme d'îlot. La ou les secondes zones (42) en forme d'îlot pénètrent jusque dans la couche conductrice de type n (31). La seconde électrode (5) comprend en tant que couche électriquement conductrice une couche d'argent (51) qui est disposée entre la première zone plane (41) et la succession de couches semi-conductrices (3) et qui forme un miroir. Le quotient de l'épaisseur moyenne de la couche d'argent (51) sur la longueur d'arête moyenne de la succession de couches semi-conductrices (3) est au moins égal à 2,5 x 10-4 et d'au moins 80 nm.
PCT/EP2013/073277 2012-11-09 2013-11-07 Puce de semi-conducteur optoélectronique et procédé de fabrication d'une puce de semi-conducteur optoélectronique Ceased WO2014072410A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102012110775.0 2012-11-09
DE102012110775.0A DE102012110775A1 (de) 2012-11-09 2012-11-09 Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips

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WO2014072410A1 true WO2014072410A1 (fr) 2014-05-15

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DE (1) DE102012110775A1 (fr)
TW (1) TW201429000A (fr)
WO (1) WO2014072410A1 (fr)

Families Citing this family (3)

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Publication number Priority date Publication date Assignee Title
DE102014107123A1 (de) * 2014-05-20 2015-11-26 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterchips sowie optoelektronischer Halbleiterchip
DE102015108532A1 (de) 2015-05-29 2016-12-01 Osram Opto Semiconductors Gmbh Anzeigevorrichtung mit einer Mehrzahl getrennt voneinander betreibbarer Bildpunkte
DE102015108545A1 (de) 2015-05-29 2016-12-01 Osram Opto Semiconductors Gmbh Optoelektronisches Bauelement und Verfahren zur Herstellung eines optoelektronischen Bauelements

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TW201429000A (zh) 2014-07-16

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