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WO2013038768A1 - Cellule solaire et son procédé de fabrication - Google Patents

Cellule solaire et son procédé de fabrication Download PDF

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Publication number
WO2013038768A1
WO2013038768A1 PCT/JP2012/066111 JP2012066111W WO2013038768A1 WO 2013038768 A1 WO2013038768 A1 WO 2013038768A1 JP 2012066111 W JP2012066111 W JP 2012066111W WO 2013038768 A1 WO2013038768 A1 WO 2013038768A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
semiconductor layer
side electrode
amorphous semiconductor
type amorphous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2012/066111
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English (en)
Japanese (ja)
Inventor
有二 菱田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2013533547A priority Critical patent/JP6048940B2/ja
Publication of WO2013038768A1 publication Critical patent/WO2013038768A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell and a manufacturing method thereof.
  • Patent Document 1 discloses, as an example, an n-type single crystal silicon substrate, a p-type amorphous silicon film and an n-type amorphous silicon film disposed on one main surface of the n-type single crystal silicon substrate. And a photoelectric conversion unit having a p-type amorphous silicon film and an n-type amorphous silicon film and an i-type amorphous silicon film disposed between the n-type single crystal silicon substrate Is described.
  • the passivation characteristics can be improved by providing an i-type amorphous silicon film between a p-type amorphous silicon film and an n-type amorphous silicon film.
  • three types of silicon films are formed: a p-type amorphous silicon film, an n-type amorphous silicon film, and an i-type amorphous silicon film.
  • the solar cell described in Patent Document 1 requires a complicated manufacturing process.
  • the main object of the present invention is to provide a solar cell that has improved passivation characteristics and does not require complicated processes for manufacturing.
  • the solar cell according to the present invention includes a photoelectric conversion unit, a p-side electrode, and an n-side electrode.
  • the p-side electrode and the n-side electrode are disposed on the photoelectric conversion unit.
  • the photoelectric conversion unit includes a substrate made of a semiconductor material and a substantially intrinsic i-type amorphous semiconductor layer.
  • the i-type amorphous semiconductor layer is disposed between the p-side electrode and the n-side electrode and the substrate.
  • a p-type region in which the p-type dopant is diffused and crystallized is provided in a portion of the i-type amorphous semiconductor layer located between the p-side electrode and the substrate.
  • An n-type dopant is diffused and a crystallized n-type region is provided in a portion of the i-type amorphous semiconductor layer located between the n-side electrode and the substrate.
  • a substantially intrinsic i-type amorphous semiconductor layer is formed on a substrate made of a semiconductor material.
  • a portion of the i-type amorphous semiconductor layer is doped with a p-type dopant and the portion is crystallized.
  • the other part of the i-type amorphous semiconductor layer is doped with an n-type dopant and the other part is crystallized.
  • a p-side electrode is formed on one part of the i-type amorphous semiconductor layer.
  • An n-side electrode is formed on the other part of the i-type amorphous semiconductor layer.
  • FIG. 1 is a schematic rear view of the solar cell according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the solar cell in the first embodiment.
  • FIG. 4 is a schematic cross-sectional view for explaining the method of manufacturing the solar cell in the first embodiment.
  • FIG. 5 is a schematic cross-sectional view of a solar cell according to the second embodiment.
  • the solar cell 1 includes a photoelectric conversion unit 10.
  • the photoelectric conversion unit 10 is a member that generates carriers such as holes and electrons when receiving light.
  • the photoelectric conversion unit 10 has a first main surface 10a and a second main surface 10b.
  • the photoelectric conversion unit 10 receives light mainly on the first main surface 10a.
  • the 1st main surface 10a may be called a light-receiving surface
  • the 2nd main surface 10b may be called a back surface.
  • the photoelectric conversion unit 10 may generate carriers only when light is received on the first main surface 10a, or when light is received on any of the first and second main surfaces 10a and 10b. May also generate a carrier.
  • the n-side electrode 21 and the p-side electrode 22 are disposed on the second main surface 10b of the photoelectric conversion unit 10.
  • the n-side electrode 21 is an electrode that collects electrons.
  • the p-side electrode 22 is an electrode that collects holes.
  • Each of the n-side electrode 21 and the p-side electrode 22 has a comb-like shape. The n-side electrode 21 and the p-side electrode 22 are inserted into each other.
  • Each of the n-side electrode 21 and the p-side electrode 22 is appropriately made of a metal such as Ag, Cu, or Sn, an alloy containing at least one of those metals, or a transparent conductive oxide such as indium tin oxide (ITO).
  • the conductive material can be used.
  • Each of the n-side electrode 21 and the p-side electrode 22 may be composed of a stacked body of a plurality of conductive layers made of the conductive material as described above.
  • the photoelectric conversion unit 10 includes a substrate 11 and a substantially intrinsic i-type amorphous semiconductor layer 12.
  • the substrate 11 is made of a semiconductor material.
  • the substrate 11 can be made of, for example, crystalline silicon such as a single crystal silicon substrate.
  • the substrate 11 has first and second main surfaces 11a and 11b.
  • the first main surface 11 a of the substrate 11 constitutes the first main surface 10 a of the photoelectric conversion unit 10.
  • the i-type amorphous semiconductor layer 12 is disposed on the second main surface 11b.
  • the i-type amorphous semiconductor layer 12 covers substantially the entire second main surface 11b. At least a part of the i-type amorphous semiconductor layer 12 is disposed between the n-side electrode 21 and the p-side electrode 22 and the substrate 11.
  • the i-type amorphous semiconductor layer 12 can be made of, for example, substantially intrinsic i-type amorphous silicon.
  • the thickness of the i-type amorphous semiconductor layer 12 is preferably 500 nm or less, and more preferably 100 nm or less. However, if the i-type amorphous semiconductor layer 12 is too thin, carriers may be transmitted. Therefore, the thickness of the i-type amorphous semiconductor layer 12 is preferably 10 nm or more, and more preferably 50 nm or more.
  • a p-type dopant is diffused, and a crystallized p-type region 12p is provided.
  • an n-type dopant is diffused and a crystallized n-type region 12n is provided. Yes.
  • a part of the portion of the i-type amorphous semiconductor layer 12 located under the n-side electrode 21 becomes the n-type region 12n, and the portion of the i-type amorphous semiconductor layer 12 located under the p-side electrode 22 Is configured to be a p-type region 12p.
  • Each of the p-type region 12p and the n-type region 12n extends from the surface 12a of the i-type amorphous semiconductor layer 12 opposite to the substrate 11 to the surface 12b of the i-type amorphous semiconductor layer 12 on the substrate 11 side. Is provided. Therefore, the p-type region 12 p is in contact with the p-side electrode 22 and also in contact with the substrate 11. The n-type region 12 n is in contact with the n-side electrode 21 and is also in contact with the substrate 11.
  • a specific example of the p-type dopant is, for example, boron.
  • Specific examples of the n-type dopant include phosphorus and the like.
  • a substantially intrinsic i-type amorphous semiconductor layer 12 is formed on a substrate 11 made of a semiconductor material.
  • the i-type amorphous semiconductor layer 12 can be formed by, for example, a CVD (Chemical Vapor Deposition) method.
  • a portion of the i-type amorphous semiconductor layer 12 is doped with a p-type dopant such as boron, and the portion is crystallized.
  • the other part of the i-type amorphous semiconductor layer 12 is doped with an n-type dopant such as phosphorus, and the other part is crystallized.
  • the n-type region 12n and the p-type region 12p are formed in the i-type amorphous semiconductor layer 12.
  • the n-type region 12n and the p-type region 12p can be formed by crystallization by, for example, annealing using a laser or the like after the i-type amorphous semiconductor layer 12 is doped with a dopant.
  • the doping and crystallization of the n-type region 12n and the p-type region 12p may be performed by simultaneously doping the dopant and crystallization using a laser, for example.
  • the substrate 11 may be doped with a dopant as long as the conductivity type of the substrate 11 does not change.
  • the n-side electrode 21 is formed on the n-type region 12 n of the i-type amorphous semiconductor layer 12.
  • a p-side electrode 22 is formed on the p-type region 12 p of the i-type amorphous semiconductor layer 12.
  • the formation method of the electrodes 21 and 22 can be appropriately selected according to the conductive material to be used.
  • the electrodes 21 and 22 can be formed by, for example, a CVD (Chemical Vapor Deposition) method, a sputtering method, a plating method, or the like.
  • the solar cell 1 does not require a complicated process for manufacturing.
  • the entire main surface 11b of the substrate 11 is covered with the i-type amorphous semiconductor layer 12, excellent passivation characteristics can be realized.
  • the solar cell 1 has excellent passivation characteristics and does not require a complicated process for manufacturing.
  • each of the n-type region 12 n and the p-type region 12 p is provided across the surface 12 a and the surface 12 b of the i-type amorphous semiconductor layer 12. For this reason, the electrical resistivity between the board
  • the solar cell 2 shown in FIG. 5 differs from the solar cell 1 in the configuration of the n-type region 12n and the p-type region 12p, and the other configuration is substantially the same as that of the solar cell 1.
  • the n-type region 12n and the p-type region 12p are respectively provided in a part of the i-type amorphous semiconductor layer 12 in the thickness direction.
  • the i-type amorphous semiconductor layer 12 has a substantially intrinsic i-type region 12 i between each of the n-type region 12 n and the p-type region 12 p and the substrate 11. For this reason, the passivation characteristic can be further improved.
  • the thickness of the i-type region 12i is preferably such that the heterojunction is not impaired. Specifically, the thickness of the i-type region 12i is preferably 0.5 nm to 50 nm, and preferably 5 nm to 15 nm.

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne une cellule solaire qui offre des caractéristiques améliorées de passivation et qui ne nécessite pas un processus compliqué de fabrication. Une cellule solaire (1) comprend une unité de conversion photoélectrique (10), une électrode côté p (22) et une électrode côté n (21). L'électrode côté p (22) et l'électrode côté n (21) sont disposées sur l'unité de conversion photoélectrique (10). L'unité de conversion photoélectrique (10) possède un substrat (11) fait d'un matériau semi-conducteur et une couche semi-conductrice amorphe de type i (12) substantiellement intrinsèque. La couche semi-conductrice amorphe de type i (12) est disposée entre le substrat (11) et les électrodes, à savoir l'électrode côté p (22) et l'électrode côté n (21). Dans une partie de la couche semi-conductrice amorphe de type i (12) placée entre l'électrode côté p (22) et le substrat (11), un dopant de type p est diffusé et une région cristallisée de type p (12p) est formée. Dans une partie de la couche semi-conductrice amorphe de type i (12) placée entre l'électrode côté n (21) et le substrat (11), un dopant de type n est diffusé et une région cristallisée de type n (12n) est formée.
PCT/JP2012/066111 2011-09-12 2012-06-25 Cellule solaire et son procédé de fabrication Ceased WO2013038768A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013533547A JP6048940B2 (ja) 2011-09-12 2012-06-25 太陽電池及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011197869 2011-09-12
JP2011-197869 2011-09-12

Publications (1)

Publication Number Publication Date
WO2013038768A1 true WO2013038768A1 (fr) 2013-03-21

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JP (1) JP6048940B2 (fr)
WO (1) WO2013038768A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015142132A (ja) * 2014-01-29 2015-08-03 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法
US20180287003A1 (en) * 2017-03-30 2018-10-04 Panasonic Corporation Solar cell and method of manufacturing solar cell
JP2019057619A (ja) * 2017-09-21 2019-04-11 株式会社カネカ バックコンタクト型太陽電池
CN110383501A (zh) * 2017-03-29 2019-10-25 松下电器产业株式会社 太阳能电池单元及太阳能电池单元的制造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105048B2 (ja) 1986-03-28 1995-11-13 横河電機株式会社 アイパタ−ン検出回路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297428A (ja) * 1994-04-28 1995-11-10 Hitachi Ltd 薄膜太陽電池とその製造方法
JP2007281156A (ja) * 2006-04-06 2007-10-25 Japan Advanced Institute Of Science & Technology Hokuriku 裏面電極型半導体へテロ接合太陽電池ならびにその製造方法と製造装置
JP2008085374A (ja) * 2007-12-19 2008-04-10 Sanyo Electric Co Ltd 光起電力素子
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2010504636A (ja) * 2006-09-26 2010-02-12 コミサリア、ア、レネルジ、アトミク 背面ヘテロ接合太陽電池製造方法
JP2011009733A (ja) * 2009-05-28 2011-01-13 Kyocera Corp 太陽電池素子、太陽電池モジュールおよび太陽光発電装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07297428A (ja) * 1994-04-28 1995-11-10 Hitachi Ltd 薄膜太陽電池とその製造方法
JP2007281156A (ja) * 2006-04-06 2007-10-25 Japan Advanced Institute Of Science & Technology Hokuriku 裏面電極型半導体へテロ接合太陽電池ならびにその製造方法と製造装置
JP2010504636A (ja) * 2006-09-26 2010-02-12 コミサリア、ア、レネルジ、アトミク 背面ヘテロ接合太陽電池製造方法
JP2008085374A (ja) * 2007-12-19 2008-04-10 Sanyo Electric Co Ltd 光起電力素子
WO2009096539A1 (fr) * 2008-01-30 2009-08-06 Kyocera Corporation Élément de batterie solaire et procédé de fabrication d'élément de batterie solaire
JP2011009733A (ja) * 2009-05-28 2011-01-13 Kyocera Corp 太陽電池素子、太陽電池モジュールおよび太陽光発電装置

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015142132A (ja) * 2014-01-29 2015-08-03 エルジー エレクトロニクス インコーポレイティド 太陽電池及びその製造方法
KR20150090607A (ko) * 2014-01-29 2015-08-06 엘지전자 주식회사 태양 전지 및 이의 제조 방법
KR102173644B1 (ko) * 2014-01-29 2020-11-03 엘지전자 주식회사 태양 전지 및 이의 제조 방법
CN110383501A (zh) * 2017-03-29 2019-10-25 松下电器产业株式会社 太阳能电池单元及太阳能电池单元的制造方法
US11430904B2 (en) * 2017-03-29 2022-08-30 Panasonic Holdings Corporation Solar cell and method of manufacturing solar cell
US20180287003A1 (en) * 2017-03-30 2018-10-04 Panasonic Corporation Solar cell and method of manufacturing solar cell
JP2018170482A (ja) * 2017-03-30 2018-11-01 パナソニック株式会社 太陽電池セル及び太陽電池セルの製造方法
JP2019057619A (ja) * 2017-09-21 2019-04-11 株式会社カネカ バックコンタクト型太陽電池

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Publication number Publication date
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JPWO2013038768A1 (ja) 2015-03-23

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