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WO2013078700A1 - 薄膜晶体管阵列基板、液晶显示器及其制作方法 - Google Patents

薄膜晶体管阵列基板、液晶显示器及其制作方法 Download PDF

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Publication number
WO2013078700A1
WO2013078700A1 PCT/CN2011/083441 CN2011083441W WO2013078700A1 WO 2013078700 A1 WO2013078700 A1 WO 2013078700A1 CN 2011083441 W CN2011083441 W CN 2011083441W WO 2013078700 A1 WO2013078700 A1 WO 2013078700A1
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Prior art keywords
layer
substrate
sealant
display area
liquid crystal
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English (en)
French (fr)
Inventor
文松贤
蔡荣茂
廖学士
庄益壮
邓明锋
张小新
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/380,051 priority Critical patent/US20130135549A1/en
Publication of WO2013078700A1 publication Critical patent/WO2013078700A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region

Definitions

  • the present invention relates to the field of liquid crystal production technologies, and in particular, to a thin film transistor array substrate, a liquid crystal display, and a method of fabricating the same.
  • TFT Thin Film Transistor
  • Liquid Crystal Display Liquid Crystal Display
  • CF substrate color filter array
  • the TFT substrate and the CF substrate are formed by a chemical or physical method, and are exposed, developed, and etched to obtain an array substrate required for design.
  • the main component of the sealant is a resin, including a thermosetting resin and a photocurable resin.
  • a sealant when a sealant is applied on a TFT substrate or a CF substrate, a pattern is first formed on the substrate, and then coated according to the shape of the pattern.
  • the above coating method may result in uneven width and height of the coated sealant, and leakage of glue and uneven thickness may occur after bonding of the TFT substrate and the CF substrate, and the above coating method may cause sealant and liquid crystal. Direct contact causes liquid crystal contamination, which in turn affects the display effect of the liquid crystal display.
  • An object of the present invention is to provide a method for fabricating a liquid crystal display, which solves the problems of leakage of glue and uneven thickness of a capacitor after bonding a TFT substrate and a CF substrate due to uneven width and height of the sealant in the prior art. Moreover, the direct contact between the sealant and the liquid crystal may cause contamination of the liquid crystal, thereby affecting the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a method of fabricating a liquid crystal display, the method comprising the steps of:
  • the first substrate has a display area and a non-display area, and the non-display area is located around the display area;
  • the coating layer includes a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer;
  • the first substrate and the second substrate are bonded by the sealant.
  • the superposed layer has a supporting height; the sum of the supporting height and the bonding distance is equal to the bonding of the first substrate and the second substrate. The distance from the inside of the position.
  • the superposed layer includes at least one of a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer.
  • the trench and the pixel electrode of the display region are formed in the same mask process.
  • Another object of the present invention is to provide a method for fabricating a liquid crystal display, which solves the problems of leakage of glue and uneven thickness of the TFT substrate after bonding between the TFT substrate and the CF substrate due to the width and height unevenness of the sealant in the prior art. Moreover, the direct contact between the sealant and the liquid crystal may cause contamination of the liquid crystal, thereby affecting the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a method of manufacturing a liquid crystal display, the method comprising the following steps:
  • the first substrate has a display area and a non-display area, and the non-display area is located around the display area;
  • the first substrate and the second substrate are bonded by the sealant.
  • the height of the sealant is higher than the groove by a bonding distance; the superposed layer has a supporting height; and the sum of the supporting height and the bonding distance And a distance corresponding to an inner side of the sealant position after the first substrate and the second substrate are bonded.
  • the coating layer formed on the display region and the non-display region includes a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer;
  • the stacked layer includes a gate electrode At least one of an insulating layer, an amorphous silicon layer, and an ohmic contact layer.
  • the trench is formed simultaneously with a pixel electrode of the switch array.
  • Another object of the present invention is to provide a liquid crystal display to solve the problem that in the prior art, due to the width and height unevenness of the sealant, the glue substrate and the CF substrate may be leaky and the thickness of the box may be uneven, and the frame may be The direct contact between the glue and the liquid crystal causes contamination of the liquid crystal, thereby affecting the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a liquid crystal display comprising:
  • a switch array disposed in the display area of the first substrate; an overlying layer formed in the non-display area of the first substrate, the superposed layer including at least one coating layer; and a trench Forming the superposed layer;
  • the height of the sealant is higher than the groove by a bonding distance; the superposed layer has a supporting height; and the sum of the supporting height and the bonding distance is equal to the The distance between the first substrate and the second substrate after bonding to the inner side of the sealant position.
  • the superposed layer includes at least one of a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer.
  • a further object of the present invention is to provide a thin film transistor array substrate, which solves the problems of leakage of glue and uneven thickness of the TFT substrate and the CF substrate due to the width and height unevenness of the sealant in the prior art. Moreover, the direct contact between the sealant and the liquid crystal may cause contamination of the liquid crystal, thereby affecting the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a thin film transistor array substrate, and the thin film transistor array substrate includes:
  • a switch array disposed in a display area of the substrate
  • An overlying layer comprising at least one coating layer and formed in a non-display area of the first substrate;
  • a groove is formed on the superposed layer for filling the sealant.
  • the height of the sealant is higher than the groove by a bonding distance; the superposed layer has a supporting height; and the sum of the supporting height and the bonding distance is equal to After the first substrate and the second substrate are bonded, a distance corresponding to an inner side of the sealant position.
  • the superposed layer includes at least one of a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer.
  • the present invention preserves a coating layer in a non-display area during formation of a first substrate (such as a thin film transistor array substrate) to form a superposed layer, and forms a trench in the superposed layer, and finally in the
  • the coating of the sealant in the groove not only can precisely control the shape of the sealant, but also avoids leakage of glue; and, since the groove penetrates into the first substrate, the height of the sealant in the longitudinal direction of the first substrate can be made uniform. Therefore, the phenomenon of uneven thickness of the box is avoided, and the sealant is coated in the groove, which effectively isolates the contact between the sealant and the liquid crystal, avoids contamination of the liquid crystal, and improves the display effect of the liquid crystal display.
  • FIG. 1 is a schematic flow chart of a preferred embodiment of a method of fabricating a liquid crystal display according to the present invention
  • FIG. 2 is a top plan view of a preferred embodiment of a TFT substrate in the present invention.
  • 3A-3E are schematic views of a preferred embodiment of a process for forming a trench in the present invention.
  • FIG. 1 is a schematic flow chart of a preferred embodiment of a method of fabricating a liquid crystal display according to the present invention.
  • step S101 a first substrate is provided, and a plurality of coating layers are formed on the display area and the non-display area of the first substrate.
  • a first metal layer, a gate insulating layer, an amorphous silicon layer, an ohmic contact layer, a second metal layer, a transparent conductive layer, a protective layer, and the like are deposited on the first substrate.
  • the first substrate is a TFT substrate.
  • the first substrate may also be a unitary body of the TFT substrate and the CF substrate.
  • step S102 the coating layer of the first substrate and the non-display area are patterned to form a switch array in the display area, and an overlying layer is formed in the non-display area.
  • the coating layer coated in step S101 is subjected to exposure, development, and etching treatment to form a switch array (such as a TFT) in a display region of a first substrate (such as a TFT array substrate).
  • a switch array such as a TFT
  • the coating layer of the non-display area is left to form an overlying layer in the non-display area.
  • a gate insulating layer of the non-display region is left to form the superposed layer.
  • the superposed layer includes one or more layers of a gate insulating layer, an amorphous silicon layer, an ohmic contact layer, and a protective layer.
  • a gate insulating layer an amorphous silicon layer
  • ohmic contact layer an ohmic contact layer
  • protective layer an ohmic contact layer
  • other coating layers may also be included. List.
  • step S103 the superposed layer of the trenches in the non-display area is formed.
  • the coating layer in the display area of the first substrate is patterned to form a switch array in the display area, the overlapping layer of the trench in the non-display area is simultaneously formed.
  • FIG. 2 is a top view of a preferred embodiment of a TFT substrate according to the present invention.
  • the first substrate 31 includes a display area A and a non-display area B, and the main trench 32 and the auxiliary trench 33 are formed on an overlying layer (not shown) of the non-display area B.
  • the main groove 32 is used to add a main sealant
  • the auxiliary groove 33 is used to add a secondary sealant.
  • step S104 a sealant is applied in the groove.
  • the width of the groove is consistent with the width of the sealant to be formed, and the depth of the groove is slightly smaller than the height of the sealant to be formed.
  • the sealant is higher than the groove by a bonding distance, and the sealant is higher than the groove by the bonding distance.
  • the bonding distance between the TFT substrate and the CF substrate is sufficient, for example, the bonding distance is 0.2 mm.
  • the coated sealant includes a main sealant located in the main groove 32 shown in FIG. 3, and a secondary sealant located in the auxiliary groove 33.
  • the superposed layer has a supporting height, and the sum of the supporting height and the bonding distance is equal to the inner side of the frame glue position after the first substrate 31 and the second substrate 32 are bonded. the distance.
  • step S105 the first substrate and the second substrate are bonded by the sealant.
  • FIGS. 3A-3E are schematic diagrams showing a preferred embodiment of a trench formation process of the present invention. This embodiment will be described by taking an example of performing exposure and development on a plurality of photomask processes while forming a switch array (TFT) and trenches (steps 102 and 103).
  • TFT switch array
  • the gate electrode 42 is formed on the display area A of the first substrate 31.
  • the gate 42 is formed by a first photomask process.
  • a gate insulating layer 43, a semiconductor layer 44, and an ohmic contact layer 45 are sequentially formed on the first substrate 31, and each of the coating layers covers the display area A and the non-display of the first substrate 31. District B.
  • the semiconductor layer 44 and the ohmic contact layer 45 are patterned by exposure development of a second photomask process to form a semiconductor island on the gate insulating layer 43.
  • the gate insulating layer 43, the semiconductor layer 44, and the ohmic contact layer 45 remain on the non-display area B without being removed to form an overlying layer (not shown).
  • the drain electrode 46a and the source electrode 46b are formed on the semiconductor island by the exposure and development of the third photomask process, and the channel C is formed between the drain electrode 46a and the source electrode 46b.
  • a protective layer 47 is formed on the channel C, the drain electrode 46a, and the source electrode 46b by exposure development of a fourth photomask process, wherein the protective layer 47 has at least one via hole 47a to expose a portion of the leakage current. Pole 46a.
  • the protective layer 47 may also remain on the superposed layer of the non-display area B without being removed.
  • the superposed layer includes four coating layers, which are a gate insulating layer 43, a semiconductor layer 44, an ohmic contact layer 45, and a protective layer 47 in this order.
  • the pixel electrode layer 48 is formed on the protective layer 47 by exposure development of a fifth photomask process. Since the pixel electrode layer 48 covers the connection hole 47a (refer to FIG. 3D), the connection hole 47a of the protection layer 47 can be electrically connected to the drain electrode 46a, so that the switching array (TFT) is completed on the first substrate 31. Display area A.
  • the overlying layers (the gate insulating layer 43, the semiconductor layer 44, the ohmic contact layer 45, and the protective layer 47) are simultaneously patterned by exposure development of a fifth photomask process to form A trench D is on the overlay. In the present embodiment, since the trench D is in the last photomask process, the depth of the trench D can be ensured.
  • the switch array (TFT) of the first substrate is completed by five photomask processes.
  • the switch array can also be masked by four or fewer channels.
  • the film process is completed.
  • the trench D on the non-display area B and the pixel electrode of the switch array are simultaneously formed in the same photomask process (last photomask process) to simplify the process steps and ensure the depth of the trench D. .
  • a coating layer of the non-display area of the first substrate is retained to form a superposed layer, and a trench is formed on the superposed layer, and a sealant is coated in the trench.
  • the shape of the sealant can be precisely controlled to avoid leakage.
  • the trenches in the embodiment are deep into the first substrate, the height of the sealant in the longitudinal direction of the first substrate can be made uniform, thereby avoiding the phenomenon of uneven thickness, and the sealant is coated on the trench. Inside, it also effectively isolates the contact between the sealant and the liquid crystal, avoids contamination of the liquid crystal, and improves the display effect of the liquid crystal display.
  • the invention also provides a liquid crystal display.
  • the liquid crystal display includes a first substrate and a second substrate.
  • the display area of the first substrate is formed with a switch array, and a non-display area of the first substrate is formed with an overlay layer, and the overlay layer includes at least one a coating layer on which a groove is formed.
  • the trench is formed by exposing, developing, and etching the stacked layer.
  • the groove is coated with a sealant, and the first substrate and the second substrate are bonded by a sealant in the groove.
  • the superposed layer includes one or more layers of a gate insulating layer, an amorphous silicon layer, and an ohmic contact layer.
  • a gate insulating layer for a gate insulating layer
  • amorphous silicon layer for a gate insulating layer
  • ohmic contact layer for a gate insulating layer
  • other coating layers may also be included, which are not enumerated here.
  • the trench is formed by exposing and developing the superposed layer through a mask, and the mask is provided with a pattern, and the shape of the pattern corresponds to the shape of the sealant. 2 and the description for FIG. 2, which are not enumerated here.
  • the width of the groove is consistent with the width of the sealant, and the height of the sealant is higher than the groove by a bonding distance. Specifically, after the glue forming the sealant is applied into the groove, the sealant is higher than the groove by a bonding distance, and the groove is higher than the groove.
  • the sealant is sufficient to bond the first substrate and the second substrate, for example, a bonding distance of 0.2 mm.
  • the superposed layer has a supporting height, and a sum of the supporting height and the bonding distance is equal to a distance corresponding to an inner side of the sealant position after the first substrate and the second substrate are bonded.
  • the present invention also provides a thin film transistor array substrate (TFT) substrate,
  • the TFT substrate includes a substrate, and a switch array is formed in a display area of the substrate, and a superimposed layer is formed in a non-display area of the substrate, the superposed layer is formed with a trench, and the trench is used for a coating frame gum.
  • the trench is formed by exposure, development and etching of the superposed layer, the superposed layer comprising one or more layers of a gate insulating layer, an amorphous silicon layer and an ohmic contact layer.
  • the trench is formed by exposing and developing the superposed layer through a mask, and the mask is provided with a pattern, and the shape of the pattern corresponds to the shape of the sealant. 2 and the description for FIG. 2, which are not enumerated here.
  • the width of the groove is consistent with the width of the sealant, and the height of the sealant is higher than the groove by a bonding distance. Specifically, after the glue forming the sealant is applied into the groove, the sealant is higher than the groove by a bonding distance, and the groove is higher than the groove.
  • the sealant is sufficient to bond the first substrate and the second substrate, for example, a bonding distance of 0.2 mm.
  • the superposed layer has a supporting height, and a sum of the supporting height and the bonding distance is equal to a distance corresponding to an inner side of the sealant position after the first substrate and the second substrate are bonded.
  • an overlying layer is formed in the non-display area during formation of the TFT substrate, the superposed layer includes at least one coating layer, a trench is formed on the superposed layer, and a sealant is coated in the trench
  • the shape of the sealant can be precisely controlled to avoid leakage.
  • the trenches penetrate into the TFT substrate, the height of the sealant in the longitudinal direction of the TFT substrate can be made uniform, thereby avoiding the phenomenon of uneven thickness of the case, and coating the sealant in the groove, and effectively The contact between the frame glue and the liquid crystal is isolated, the liquid crystal pollution is avoided, and the display quality of the liquid crystal display is improved.

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  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种薄膜晶体管阵列基板、液晶显示器及其制作方法，所述方法包括：形成涂布层于第一基板（31）的显示区（A）及非显示区（B）上；形成一叠加层于非显示区（B）；通过曝光显影形成沟槽（D）于叠加层；在沟槽（D）内填充框胶；通过所述框胶将第一基板（31）和第二基板（32）粘接。该方法可准确地控制框胶的形状，还可避免漏胶，避免盒厚不均。

Description

薄膜晶体管阵列基板、液晶显示器及其制作方法 技术领域
本发明涉及液晶生产技术领域，尤其涉及一种薄膜晶体管阵列基板、液晶显示器及其制作方法。
 背景技术
随着液晶显示技术的不断发展，对液晶显示器功能的要求也越来越高。
薄膜晶体管阵列（Thin Film Transistor，以下简称TFT）-液晶显示器（Liquid Crystal Display ，LCD）是由TFT基板和彩色滤光阵列(Color Filter，以下简称CF)基板以及上述两基板之间的液晶构成。其中，TFT基板与CF基板是经由化学或物理的方法成膜、曝光、显影以及蚀刻处理后得到设计所需的阵列基板。
为了切断两基板之间的液晶分子与外界的接触，需要在真空环境下使用框胶对TFT基板与CF基板进行密封，框胶的主要成分为树脂，包括热固化型树脂和光固化型树脂。
现有技术在TFT基板或者CF基板上涂布框胶时，基本上都是先在基板上形成一图案，然后根据图案的形状进行涂布。但是上述涂布方式会导致涂布出的框胶的宽度以及高度不均匀，TFT基板与CF基板粘接后会出现漏胶以及盒厚不均等现象，而且上述涂布方式会导致框胶和液晶直接接触，造成液晶的污染，进而影响液晶显示器的显示效果。
 技术问题
本发明的一个目的在于提供一种液晶显示器的制造方法，以解决现有技术中由于框胶的宽度以及高度不均匀，TFT基板与CF基板粘接后会出现漏胶以及盒厚不均等现象，而且框胶和液晶直接接触，会造成液晶的污染，进而影响液晶显示器的显示效果的技术问题。
 技术解决方案
本发明构造了一种液晶显示器的制造方法，所述方法包括以下步骤：
提供第一基板，所述第一基板具有显示区及非显示区，所述非显示区位于所述显示区周围；
形成涂布层于所述显示区及所述非显示区上；所述涂布层包括栅极绝缘层、非晶硅层以及欧姆接触层；
分别图案化所述显示区及所述非显示区内的所述涂布层，以形成一开关阵列于所述显示区，形成一叠加层于所述非显示区；
通过曝光显影形成沟槽于所述叠加层；
在所述沟槽内填充框胶；其中，所述框胶的高度相对所述沟槽高出一粘接距离；
通过所述框胶将所述第一基板和第二基板粘接。
在本发明的液晶显示器的制造方法中，所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
在本发明的液晶显示器的制造方法中，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
在本发明的液晶显示器的制造方法中，在通过曝光显影形成沟槽于所述叠加层时，所述沟槽与所述显示区的像素电极是于同一道光罩制程形成。
本发明的另一个目的在于提供一种液晶显示器的制造方法，以解决现有技术中由于框胶的宽度以及高度不均匀，TFT基板与CF基板粘接后会出现漏胶以及盒厚不均等现象，而且框胶和液晶直接接触，会造成液晶的污染，进而影响液晶显示器的显示效果的技术问题。
为解决上述技术问题，本发明构造了一种液晶显示器的制造方法，所述方法包括以下步骤：
提供第一基板，所述第一基板具有显示区及非显示区，所述非显示区位于所述显示区周围；
形成涂布层于所述显示区及所述非显示区上；
分别图案化所述显示区及所述非显示区内的所述涂布层，以形成一开关阵列于所述显示区，形成一叠加层于所述非显示区，其中，所述叠加层包括至少一层的涂布层；
通过曝光显影形成沟槽于所述叠加层；
在所述沟槽内填充框胶；以及
通过所述框胶将所述第一基板和第二基板粘接。
在本发明的液晶显示器的制造方法中，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
在本发明的液晶显示器的制造方法中，在所述显示区及所述非显示区上形成的涂布层包括栅极绝缘层、非晶硅层以及欧姆接触层；所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
在本发明的液晶显示器的制造方法中，在通过曝光显影形成沟槽于所述叠加层时，所述沟槽与所述开关阵列的像素电极是同时形成。
本发明的又一个目的在于提供一种液晶显示器，以解决现有技术中由于框胶的宽度以及高度不均匀，TFT基板与CF基板粘接后会出现漏胶以及盒厚不均等现象，而且框胶和液晶直接接触，会造成液晶的污染，进而影响液晶显示器的显示效果的技术问题。
本发明构造了一种液晶显示器，所述液晶显示器包括：
第一基板；
开关阵列，设置于所述第一基板的所述显示区内；一叠加层，形成于所述第一基板的非显示区内，所述叠加层包括至少一层涂布层；以及沟槽，形成所述叠加层上；
框胶，涂布于所述沟槽内；以及
第二基板，通过所述框胶粘接所述第一基板。
在本发明的液晶显示器中，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
在本发明的液晶显示器中，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
本发明的又一个目的在于提供一种薄膜晶体管阵列基板，以解决现有技术中由于框胶的宽度以及高度不均匀，TFT基板与CF基板粘接后会出现漏胶以及盒厚不均等现象，而且框胶和液晶直接接触，会造成液晶的污染，进而影响液晶显示器的显示效果的技术问题。
为解决上述技术问题，本发明构造了一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
基板；
开关阵列，设置于所述基板的显示区内；
一叠加层，其包括至少一层涂布层，且形成于所述第一基板的非显示区内；以及
沟槽，形成所述叠加层上，用于填充框胶。
在本发明的薄膜晶体管阵列基板中，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
在本发明的薄膜晶体管阵列基板中，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
 有益效果
本发明相对于现有技术，通过在第一基板（譬如薄膜晶体管阵列基板）形成过程中在非显示区保留涂布层以形成一叠加层，并在所述叠加层形成沟槽，最后在所述沟槽内涂布框胶，不仅可以精确的控制框胶的形状，进而避免漏胶；而且，由于沟槽深入所述第一基板内，可以使得在第一基板纵向上框胶的高度一致，从而避免盒厚不均的现象，而且将框胶涂布在沟槽内，还有效地隔绝了框胶与液晶的接触，避免造成液晶的污染，提高了液晶显示器的显示效果。
 附图说明
图1为本发明中液晶显示器的制造方法的较佳实施例的流程示意图；
图2为本发明中TFT基板的较佳实施例俯视图；
图3A-3E为本发明中沟槽的形成过程的较佳实施例示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
图1为本发明中液晶显示器的制造方法的较佳实施例的流程示意图。
在步骤S101中，提供第一基板，并形成多个涂布层于所述第一基板的显示区及非显示区上。
譬如，在所述第一基板上沉积有第一金属层、栅极绝缘层、非晶硅层、欧姆接触层、第二金属层、透明导电层以及保护层等。
在具体实施过程中，所述第一基板为TFT基板。当然，所述第一基板也可以为TFT基板与CF基板的统一体。
在步骤S102中，图案化所述第一基板的显示区和非显示区内的涂布层，以形成一开关阵列于所述显示区内，并在所述非显示区形成一叠加层。
在具体实施过程中，通过对步骤S101中涂布的涂布层进行曝光、显影以及蚀刻处理以形成开关阵列(譬如TFT)于第一基板(譬如TFT阵列基板)的显示区内。
本实施例中，在对所述第一基板的涂布层进行曝光、显影以及蚀刻处理的过程中，保留非显示区的涂布层，以在所述非显示区形成一叠加层。譬如在对栅极绝缘层曝光显影形成栅极的过程中，保留非显示区的栅极绝缘层以形成所述叠加层。
在本实施例中，所述叠加层包括栅极绝缘层、非晶硅层、欧姆接触层以及保护层中的一层或者多层，当然也可以包括其它的涂布层，此处不一一列举。
在步骤S103中，形成沟槽于所述非显示区的所述叠加层。
在具体实施过程中，在图案化所述第一基板的显示区内的涂布层，以形成开关阵列于所述显示区内时，同时形成沟槽于所述非显示区的所述叠加层。
请参阅图2，图2为本发明中TFT基板的较佳实施例俯视图。在图2中，所述第一基板31包括显示区A以及非显示区B，而主沟槽32和辅沟槽33形成于所述非显示区B的叠加层（图未标示）上。所述主沟槽32用来添加主框胶，所述辅沟槽33用来添加辅框胶。
在步骤S104中，在所述沟槽内涂布框胶。
在具体实施过程中，所述沟槽的宽度与待形成的框胶的宽度一致，所述沟槽的深度略小于待形成的框胶的高度。具体说来，形成框胶的胶液涂布进所述沟槽后，所述框胶相对所述沟槽高出一粘接距离，相对所述沟槽高出所述粘接距离的框胶以足够将TFT基板和CF基板粘接为准，譬如粘接距离为0.2mm。
其中，涂布的框胶包括位于图3所示的主沟槽32内的主框胶，以及位于辅沟槽33内的辅框胶。
在具体实施过程中，所述叠加层具有一支撑高度，所述支撑高度与所述粘接距离的和等于所述第一基板31和第二基板32粘接后对应所述框胶位置的内侧的距离。
在步骤S105中，通过所述框胶将所述第一基板和第二基板粘接。
请参阅图3A-3E，图3A-3E为本发明中沟槽的形成过程的较佳实施例示意图。本实施例以对多道光掩膜制程进行曝光显影同时形成开关阵列(TFT)及沟槽(步骤102、103)为例进行说明。
请参阅图3A，形成栅极42于第一基板31的显示区A。该栅极42通过第一道光掩膜制程来形成。
请参阅图3B，在所述第一基板31上依次形成栅极绝缘层43、半导体层44及欧姆接触层45，上述各涂布层均覆盖所述第一基板31的显示区A和非显示区B。并通过第二道光掩膜制程的曝光显影来图案化半导体层44、欧姆接触层45，以形成半导体岛于栅极绝缘层43上。此时，栅极绝缘层43、半导体层44及欧姆接触层45保留于非显示区B上，而未被移除，以形成一叠加层（图未标示）。
请参阅图3C，通过第三道光掩膜制程的曝光显影来形成漏电极46a及源电极46b于半导体岛上，并形成沟道C于漏电极46a及源电极46b之间。
请参阅图3D，通过第四道光掩膜制程的曝光显影来形成保护层47于沟道C、漏电极46a及源电极46b上，其中保护层47具有至少一接孔47a，以暴露出部分漏电极46a。此时，保护层47亦可保留于非显示区B的叠加层上，而未被移除。此时叠加层包括有四个涂布层，依次为栅极绝缘层43、半导体层44、欧姆接触层45以及保护层47。
请参阅图3E，通过第五道光掩膜制程的曝光显影来形成像素电极层48于保护层47上。由于像素电极层48是覆盖于接孔47a（请参阅图3D）上，因而可利用保护层47的接孔47a来电性连接于漏电极46a，故完成开关阵列(TFT)于第一基板31的显示区A上。在第五道光掩膜制程中，同时通过第五道光掩膜制程的曝光显影来图案化所述叠加层(栅极绝缘层43、半导体层44、欧姆接触层45和保护层47)，以形成沟槽D于所述叠加层。在本实施例中，由于沟槽D是在最后一道光掩膜制程中，因而可确保沟槽D的深度。
在本实施例中，第一基板的开关阵列(TFT)是通过五道光掩膜制程来完成，然不限此，在其它实施例中，开关阵列亦可通过四道或更少道的光掩膜制程来完成。有利地，非显示区B上的沟槽D与开关阵列的像素电极是在同一道光掩膜制程(最后一道光掩膜制程)中同时形成，以简化制程步骤，并可确保沟槽D的深度。
本实施例在第一基板形成过程中，通过保留第一基板非显示区的涂布层以形成一叠加层，并在所述叠加层上形成沟槽，在所述沟槽内涂布框胶，可以精确的控制框胶的形状，从而避免漏胶。
而且，由于本实施例中的沟槽深入所述第一基板内，可以使得在第一基板纵向上框胶的高度一致，从而避免盒厚不均的现象，而且将框胶涂布在沟槽内，还有效地隔绝了框胶与液晶的接触，避免造成液晶的污染，提高了液晶显示器的显示效果。
本发明还提供一种液晶显示器。
其中，所述液晶显示器包括第一基板和第二基板，所述第一基板的显示区形成有开关阵列，所述第一基板的非显示区内形成有叠加层，所述叠加层包括至少一涂布层，所述叠加层上形成有沟槽。
其中，所述沟槽由所述叠加层经曝光、显影以及蚀刻处理所形成。所述沟槽内涂布有框胶，所述第一基板和所述第二基板通过所述沟槽内的框胶粘接。
在具体实施过程中，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的一层或者多层，当然也可以包括其它的涂布层，此处不一一列举。
在具体实施过程中，所述沟槽经一掩模对所述叠加层进行曝光显影而形成，所述掩模设置有图案，所述图案的形状对应所述框胶的形状，具体请参阅图2以及针对图2的描述，此处不一一列举。
其中，所述沟槽的宽度与所述框胶的宽度一致，所述框胶的高度相对所述沟槽高出一粘接距离。具体说来，形成所述框胶的胶液涂布进所述沟槽后，所述框胶相对所述沟槽高出一粘接距离，相对所述沟槽高出所述粘接距离的框胶以足够将所述第一基板和所述第二基板粘接，譬如粘接距离为0.2mm。
在具体实施过程中，所述叠加层具有一支撑高度，所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
鉴于本实施例中所述沟槽的形成过程在上文已有详细的描述，此处不再赘述。
本发明还提供一种薄膜晶体管阵列基板（TFT）基板，
所述TFT基板包括基板，所述基板的显示区内形成有开关阵列，所述基板的非显示区内形成有叠加层，所述叠加层形成有沟槽，所述沟槽用于涂布框胶。
其中，所述沟槽由所述叠加层经曝光、显影以及蚀刻处理所形成，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的一层或者多层。
在具体实施过程中，所述沟槽经一掩模对所述叠加层进行曝光显影而形成，所述掩模设置有图案，所述图案的形状对应所述框胶的形状，具体请参阅图2以及针对图2的描述，此处不一一列举。
其中，所述沟槽的宽度与所述框胶的宽度一致，所述框胶的高度相对所述沟槽高出一粘接距离。具体说来，形成所述框胶的胶液涂布进所述沟槽后，所述框胶相对所述沟槽高出一粘接距离，相对所述沟槽高出所述粘接距离的框胶以足够将所述第一基板和所述第二基板粘接，譬如粘接距离为0.2mm。
在具体实施过程中，所述叠加层具有一支撑高度，所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
鉴于本实施例中所述沟槽的形成过程在上文已有详细的描述，此处不再赘述。
本实施例通过在TFT基板形成过程中在非显示区形成一叠加层，所述叠加层包括至少一涂布层，在所述叠加层上形成沟槽，在所述沟槽内涂布框胶，可以精确的控制框胶的形状，从而避免漏胶。而且，由于沟槽深入所述TFT基板内，可以使得在所述TFT基板纵向上框胶的高度一致，从而避免盒厚不均的现象，而且将框胶涂布在沟槽内，还有效地隔绝了框胶与液晶的接触，避免造成液晶的污染，提高了液晶显示器的显示质量。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
本发明的实施方式
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Claims (14)

  1. 一种液晶显示器的制造方法，其特征在于，所述方法包括以下步骤：
    提供第一基板，所述第一基板具有显示区及非显示区，所述非显示区位于所述显示区周围；
    形成涂布层于所述显示区及所述非显示区上；所述涂布层包括栅极绝缘层、非晶硅层以及欧姆接触层；
    分别图案化所述显示区及所述非显示区内的所述涂布层，以形成一开关阵列于所述显示区，形成一叠加层于所述非显示区；
    通过曝光显影形成沟槽于所述叠加层；
    在所述沟槽内填充框胶；其中，所述框胶的高度相对所述沟槽高出一粘接距离；
    通过所述框胶将所述第一基板和第二基板粘接。
  2. 根据权利要求1所述的液晶显示器的制造方法，其特征在于，所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
  3. 根据权利要求1所述的液晶显示器的制造方法，其特征在于，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
  4. 根据权利要求1所述的液晶显示器的制造方法，其特征在于，在通过曝光显影形成沟槽于所述叠加层时，所述沟槽与所述显示区的像素电极是于同一道光罩制程形成。
  5. 一种液晶显示器的制造方法，其特征在于，所述方法包括以下步骤：
    提供第一基板，所述第一基板具有显示区及非显示区，所述非显示区位于所述显示区周围；
    形成涂布层于所述显示区及所述非显示区上；
    分别图案化所述显示区及所述非显示区内的所述涂布层，以形成一开关阵列于所述显示区，形成一叠加层于所述非显示区，其中，所述叠加层包括至少一层的涂布层；
    通过曝光显影形成沟槽于所述叠加层；
    在所述沟槽内填充框胶；以及
    通过所述框胶将所述第一基板和第二基板粘接。
  6. 根据权利要求5所述的液晶显示器的制造方法，其特征在于，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
  7. 根据权利要求5所述的液晶显示器的制造方法，其特征在于，在所述显示区及所述非显示区上形成的涂布层包括栅极绝缘层、非晶硅层以及欧姆接触层；所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
  8. 根据权利要求5所述的液晶显示器的制造方法，其特征在于，在通过曝光显影形成沟槽于所述叠加层时，所述沟槽与所述显示区的像素电极是于同一道光罩制程形成。
  9. 一种液晶显示器，其特征在于：所述液晶显示器包括：
    第一基板；
    开关阵列，设置于所述第一基板的所述显示区内；一叠加层，形成于所述第一基板的非显示区内，所述叠加层包括至少一层涂布层；以及沟槽，形成所述叠加层上；
    框胶，涂布于所述沟槽内；以及
    第二基板，通过所述框胶来粘接所述第一基板。
  10. 根据权利要求9所述的液晶显示器，其特征在于，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
  11. 根据权利要求9所述的液晶显示器，其特征在于，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
  12. 一种薄膜晶体管阵列基板，其特征在于：所述薄膜晶体管阵列基板包括：
    基板；
    开关阵列，设置于所述基板的显示区内；
    一叠加层，其包括至少一层涂布层，且形成于所述第一基板的非显示区内；以及
    沟槽，形成所述叠加层上，用于填充框胶。
  13. 根据权利要求12所述的薄膜晶体管阵列基板，其特征在于，所述框胶的高度相对所述沟槽高出一粘接距离；所述叠加层具有一支撑高度；所述支撑高度与所述粘接距离的和等于所述第一基板和第二基板粘接后对应所述框胶位置的内侧的距离。
  14. 根据权利要求12所述的薄膜晶体管阵列基板，其特征在于，所述叠加层包括栅极绝缘层、非晶硅层以及欧姆接触层中的至少一层。
PCT/CN2011/083441 2011-11-29 2011-12-05 薄膜晶体管阵列基板、液晶显示器及其制作方法 Ceased WO2013078700A1 (zh)

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CN113050320A (zh) * 2019-12-26 2021-06-29 财团法人工业技术研究院 调光装置
CN117148631A (zh) * 2023-08-29 2023-12-01 京东方科技集团股份有限公司 显示基板、显示面板及边框胶的涂布方法

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CN104252065A (zh) * 2013-06-26 2014-12-31 北京京东方光电科技有限公司 一种显示基板及制作方法、显示装置
CN103955084B (zh) * 2014-03-31 2016-06-08 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN116169211B (zh) * 2021-11-25 2025-05-27 成都辰显光电有限公司 键合辅助模组和键合方法

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