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WO2013004050A1 - 薄膜晶体管阵列基板及其制法 - Google Patents

薄膜晶体管阵列基板及其制法 Download PDF

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Publication number
WO2013004050A1
WO2013004050A1 PCT/CN2011/079854 CN2011079854W WO2013004050A1 WO 2013004050 A1 WO2013004050 A1 WO 2013004050A1 CN 2011079854 W CN2011079854 W CN 2011079854W WO 2013004050 A1 WO2013004050 A1 WO 2013004050A1
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WIPO (PCT)
Prior art keywords
signal line
electrode
opening
thin film
film transistor
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PCT/CN2011/079854
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English (en)
French (fr)
Inventor
张骢泷
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/376,913 priority Critical patent/US8867004B2/en
Publication of WO2013004050A1 publication Critical patent/WO2013004050A1/zh
Anticipated expiration legal-status Critical
Priority to US14/487,129 priority patent/US9214483B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/18, H10D48/04 and H10D48/07, with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D64/011—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to a thin film transistor array substrate, and more particularly to a thin film transistor array substrate and a method of fabricating the same.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, Thin Film Transistor Liquid
  • the structure of the crystal display mainly comprises two glass substrates and a liquid crystal layer disposed therebetween, wherein the upper glass substrate is provided with a color filter (Color) Filter), the color filter contains a color photoresist and a black matrix; and the lower glass substrate is provided with a thin film transistor and a pixel electrode, so it is generally called a thin film transistor array substrate (TFT LCD Array) Substrate).
  • TFT LCD Array Thin Film Transistor Liquid Crystal Display, Thin Film Transistor Liquid
  • TFT LCD Array thin film transistor array substrate
  • a sub-pixel structure includes a pixel electrode, a thin film transistor, and a storage capacitor, wherein a gate of the thin film transistor is connected to a scan signal line, a source thereof is connected to the data signal line, and a drain thereof is connected to the drain a pixel electrode; the storage capacitor is connected to the pixel electrode.
  • the thin film transistor is turned on by applying a voltage to the gate of the thin film transistor through the scanning signal line.
  • the source of the thin film transistor receives the data signal through the data signal line and transmits it to the drain, and then writes to the pixel electrode and stores it in the storage capacitor.
  • FIG. 1 is a partial structural diagram of a conventional thin film transistor array substrate.
  • a thin film transistor 9 is located near the intersection of a scanning signal line 8 and a data signal line 7, wherein the thin film transistor 9 includes a gate electrode 90, a semiconductor layer 91, a drain electrode 92, and a source electrode.
  • the gate electrode 90 is a part of the scanning signal line 8; the semiconductor layer 91 is disposed on the gate electrode 90 via an insulating layer (not shown);
  • a pole electrode 92 is disposed on the semiconductor layer 91; the source electrode 93 extends from one side of the data signal line 7 and surrounds the drain electrode 92 along an edge of the semiconductor layer 91.
  • a parasitic capacitance is generated between the drain electrode 92 and the gate electrode 90.
  • the gate electrode 90 is further provided with an opening 900 corresponding to the position of the drain electrode 92, so that the The overlapping portion of the gate electrode 90 to the drain electrode 92 is reduced, thereby reducing the parasitic capacitance formed therebetween.
  • the opening 900 of the gate electrode 90 makes the area of the scanning signal line 8 small, thereby increasing the resistance of the scanning signal line 8.
  • the transmission speed of the scanning signal line 8 will be adversely affected by the increase in resistance.
  • the present invention provides a thin film transistor array substrate and a method of fabricating the same to solve the problem of increasing the resistance of the signal line in order to reduce the parasitic capacitance between the drain electrode and the gate electrode.
  • the invention provides a thin film transistor array substrate comprising:
  • the scanning signal line is disposed on the substrate in a horizontal direction and has a first side and a second side opposite to the first side;
  • a data signal line disposed on the substrate along a vertical direction and insulated from the scanning signal lines;
  • a thin film transistor is formed adjacent to the intersection of the scan signal line and the data signal line, and includes a gate electrode, a semiconductor layer, a drain electrode, and a source electrode, wherein the gate electrode is the Scanning a portion of the signal line and having an opening, the opening being located at a center of the gate electrode and extending to a first side of the scan signal line; the semiconductor layer being insulatingly disposed over the gate electrode; a drain electrode is disposed on the semiconductor layer and corresponding to an opening of the gate electrode; the source electrode extends from one side of the data signal line and surrounds the edge of the semiconductor layer An opening of the drain electrode and the gate electrode;
  • a compensation electrode extending integrally from the second side of the scan signal line and corresponding to the gate electrode; an area of the compensation electrode being equal to an area of the opening of the gate electrode, and the compensation electrode and the The distance between the data signal lines is greater than 3.5 microns.
  • the present invention further provides a thin film transistor array substrate comprising:
  • the scanning signal line is disposed on the substrate in a horizontal direction and has a first side and a second side opposite to the first side;
  • a data signal line disposed on the substrate along a vertical direction and interlaced with the scan signal lines;
  • a thin film transistor is formed in the vicinity of the intersection of the scan signal line and the data signal line, and includes a gate electrode, a semiconductor layer, a drain electrode and a source electrode, wherein the gate electrode is Part of the scanning signal line has an opening, the opening is located at a center of the gate electrode and extends to a first side of the scanning signal line; the semiconductor layer is insulatingly disposed above the gate electrode.
  • the drain electrode is disposed on the semiconductor layer and corresponds to an opening of the gate electrode; the source electrode extends from one side of the data signal line and along the semiconductor layer An opening surrounding the drain electrode and the gate electrode; and
  • the compensation electrode extends integrally from the second side of the scanning signal line and corresponds to the gate electrode.
  • the opening of the gate electrode has a rectangular shape.
  • the drain electrode has an inverted T shape and includes a horizontal portion and a vertical portion, and the horizontal portion is parallel to the first side and the second side of the scanning signal line. And corresponding to the opening of the gate electrode; the vertical portion extends from a side of the horizontal portion and is perpendicular to a first side of the scanning signal line, and corresponds to an opening of the gate electrode.
  • the width of the vertical portion is smaller than the width of the opening of the gate electrode.
  • the area of the compensation electrode is equal to the area of the opening.
  • the compensation electrode is trapezoidal.
  • the distance between the compensation electrode and the data signal line is greater than 3.5 microns.
  • the invention further provides a method for fabricating a thin film transistor array substrate, the method comprising the following steps:
  • the scan signal line includes a first side, a second side opposite to the first side, and an opening extending to the first side
  • the compensation electrode extends from the second side of the scanning signal line
  • a data signal line, a drain electrode, and a source electrode on the substrate, wherein the data signal line and the scan signal line are insulated from each other, and the drain electrode is located on the semiconductor layer and corresponds to the scan signal line An opening of the source electrode extending from one side of the data signal line on the semiconductor layer and surrounding the drain electrode and the gate electrode along an edge of the semiconductor layer Opening.
  • the method further includes the following steps:
  • the compensation electrode has a trapezoidal shape and a distance from the data signal line is greater than 3.5 microns.
  • the invention mainly comprises extending the compensation electrode on the opposite side of the scanning signal line according to the opening of the scanning signal line, so as to prevent the opening from increasing the resistance of the scanning signal line, and still reducing the parasitic generated between the drain electrode and the gate electrode. capacitance.
  • FIG. 1 is a partial structural schematic view of a conventional thin film transistor array substrate.
  • FIG. 2 is a partial structural schematic view of another conventional thin film transistor array substrate
  • FIG 3 is a partial structural schematic view of a first embodiment of a thin film transistor array substrate of the present invention.
  • FIG. 4 is a partial structural schematic view showing a second embodiment of the thin film transistor array substrate of the present invention.
  • 5A-5E are flow diagrams showing the fabrication of a preferred embodiment of the thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate of the present invention is mainly composed of a thin film transistor array provided on a substrate.
  • FIG. 3 is a partial structural diagram of a first embodiment of a thin film transistor array substrate according to the present invention.
  • the thin film transistor array substrate in addition to the substrate (not shown), the thin film transistor array substrate further includes a scan signal line 1, a data signal line 2, a thin film transistor 3, and a compensation electrode 100.
  • the number of the foregoing elements is merely for convenience of description and understanding of the invention, and is not intended to limit the number of elements of the invention.
  • the scanning signal line 1 is disposed on the substrate in a horizontal direction and has a first side and a second side opposite to the first side.
  • the data signal lines 2 are disposed on the substrate in a vertical direction and are insulated from the scanning signal lines 1 from each other.
  • the thin film transistor 3 is formed near the intersection of the scanning signal line 1 and the data signal line 2, and includes a gate electrode 30, a semiconductor layer 31, a drain electrode 32, and a source electrode 33.
  • the gate electrode 30 is a part of the scanning signal line 1 and has an opening 300 located at the center of the gate electrode 30 and extending to the first side of the scanning signal line 1.
  • the opening 300 is preferably rectangular.
  • the semiconductor layer 31 is provided over the gate electrode 30 in an insulating manner (preferably via an insulating layer).
  • the drain electrode 32 is disposed on the semiconductor layer 31 and corresponds to the opening 300 of the gate electrode 30.
  • the drain electrode 32 is preferably in an inverted T shape, and includes a horizontal portion 32a and a vertical portion 32b.
  • the extending direction of the horizontal portion 32a is parallel to the first side and the second side of the scanning signal line 1, and the horizontal portion 32a corresponds to the opening 300 of the gate electrode 30.
  • the horizontal portion 32a partially overlaps the gate electrode 30, and preferably the edge of the horizontal portion 32a overlaps the gate electrode 30.
  • the vertical portion 32b extends from one side of the horizontal portion 32a, is perpendicular to the first side of the scanning signal line 1, and corresponds to the opening 300 of the gate electrode 30.
  • the width of the vertical portion 32b is preferably smaller than the width of the opening 300 of the gate electrode 30.
  • the source electrode 33 extends from one side of the data signal line 2 and surrounds the drain electrode 32 and the opening 300 of the gate electrode 30 along an edge of the semiconductor layer 31.
  • the compensation electrode 100 integrally extends from the second side of the scanning signal line 1 and corresponds to the gate electrode 30.
  • the area of the compensation electrode 100 is preferably equal to the area of the opening 300, and the opening 300 is rectangular.
  • FIG. 4 is a partial structural diagram of a second embodiment of the thin film transistor array substrate of the present invention.
  • the second embodiment of the present invention is similar to the first embodiment of the present invention, and generally uses the same component name, but differs from the first embodiment in that the compensation electrode 100 is trapezoidal. And the distance between the compensation electrode 100 and the data signal line 2 is preferably greater than 3.5 microns.
  • the present invention can avoid that the resistance value of the scanning signal line 1 becomes large due to the formation of the opening 300.
  • FIGS. 5A to 5E are flowcharts showing the fabrication of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • the method for fabricating the thin film transistor array substrate of the present invention comprises the following steps:
  • S1 forming a scanning signal line 1 and a compensation electrode 100 on the substrate, wherein the scanning signal line 1 includes a first side, a second side opposite to the first side, and an opening 300.
  • the opening 300 Extending to the first side; the compensation electrode 100 extends from the second side of the scanning signal line 1 (as shown in FIG. 5A);
  • S4 forming a data signal line 2, a drain electrode 32, and a source electrode 33 on the substrate, wherein the data signal line 2 and the scan signal line 1 are insulated from each other, and the drain electrode 32 has an inverted T shape.
  • the source electrode 33 Located on the semiconductor layer 31 and corresponding to the opening 300 of the scanning signal line 1, the source electrode 33 extends from one side of the data signal line 2 to be located on the semiconductor layer 31, and along the edge The edge of the semiconductor layer 31 surrounds the drain electrode 32 and the opening 300 of the gate electrode 30 (as shown in FIG. 5C);
  • the thin film transistor array substrate as shown in FIG. 4 can be completed.
  • the present invention mainly extends the compensation electrode on the opposite side of the scanning signal line according to the opening of the scanning signal line to complement the originally reduced portion of the scanning signal line area, thereby preventing the formation of the opening and the scanning signal.
  • the line resistance value becomes large, and the effect of reducing the parasitic capacitance generated between the drain electrode and the gate electrode can be maintained.

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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Thin Film Transistor (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明公开一种薄膜晶体管阵列基板及其制法。所述阵列基板包含薄膜晶体管及补偿电极。所述薄膜晶体管的栅极电极为扫描信号线的一部分并具有一开口，所述开口延伸至扫描信号线的一侧边。所述薄膜晶体管的漏极电极位置对应所述开口。所述薄膜晶体管的源极电极自数据信号线的一侧边延伸出并环绕漏极电极。补偿电极自扫描信号线的另一侧边延伸出而对应栅极电极。因此，本发明可减少漏极电极与栅极电极之间的寄生电容而不提高扫描信号线的阻值。

Description

薄膜晶体管阵列基板及其制法 技术领域
本发明是有关于一种薄膜晶体管阵列基板，特别是有关于一种薄膜晶体管阵列基板及其制法。
 背景技术
现有技术中，TFT-LCD（薄膜晶体管液晶显示器, Thin Film Transistor Liquid Crystal Display）的构造主要包含两片玻璃基板以及配置于两者之间的液晶层，其中上层玻璃基板表面设有彩色滤光片（Color Filter），彩色滤光片包含了彩色光阻及黑色矩阵；而下层玻璃基板则设有薄膜晶体管与像素电极，故一般称为薄膜晶体管阵列基板(TFT LCD Array Substrate)。
在薄膜晶体管阵列基板中，一个子像素的结构包含了像素电极、薄膜晶体管及存储电容，其中所述薄膜晶体管的栅极连接扫描信号线，其源极连接数据信号线，其漏极则连接所述像素电极；所述存储电容则连接所述像素电极。通过扫描信号线对薄膜晶体管的栅极施加电压，即可使薄膜晶体管导通。薄膜晶体管的源极再通过数据信号线接受数据信号并传送到漏极，进而写入像素电极并存储于所述存储电容。
除了前述的存储电容，所述薄膜晶体管的实际结构中还存在许多寄生电容(Parasitic Capacitance)，这些寄生电容对于所述薄膜晶体管是不必要的，且会造成电荷流失而影响薄膜晶体管的操作特性。
请参考图1，图1为一现有薄膜晶体管阵列基板的局部结构示意图。如图1所示，一薄膜晶体管9位于一扫描信号线8与一资料信号线7的交叉处附近，其中，薄膜晶体管9包含栅极电极90、半导体层91、漏极电极92及源极电极93，其中，所述栅极电极90是所述扫描信号线8的一部分；所述半导体层91是隔着一绝缘层(图中未示)设置于所述栅极电极90上；所述漏极电极92设置于所述半导体层91上；所述源极电极93是自所述数据信号线7的一侧延伸出而沿着所述半导体层91的边缘围绕所述漏极电极92。在漏极电极92与栅极电极90之间会产生寄生电容。
请进一步参考图2所示，为了降低前述漏极电极92与栅极电极90之间所产生的寄生电容，所述栅极电极90进一步设置一个对应漏极电极92位置的开口900，使得所述栅极电极90对漏极电极92的重叠部分减少，进而降低两者之间所形成的寄生电容。
然而，所述栅极电极90的开口900会使扫描信号线8的面积变小，从而提高扫描信号线8的阻值。所述扫描信号线8的传输速度将会因为阻值变大而受到不利影响。
故，有必要提供一种薄膜晶体管阵列基板及其制法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种薄膜晶体管阵列基板及其制法，以解决为了减少漏极电极与栅极电极之间的寄生电容而导致信号线阻值升高的问题。
有鉴于现有技术的缺点，本发明的主要目的在于提供一种薄膜晶体管阵列基板，其可减少漏极电极与栅极电极之间所产生的寄生电容而不提高扫描信号线的阻值。
 技术解决方案
本发明提供一种薄膜晶体管阵列基板，其包含：
基板；
扫描信号线，沿一水平方向设置于所述基板上，并具有一第一侧边与一相对于第一侧边的第二侧边；
数据信号线，沿一垂直方向设置于所述基板上而与所述扫描信号线彼此绝缘交错；
薄膜晶体管，形成于所述扫描信号线与所述数据信号线交叉处附近，并包含一栅极电极、一半导体层、一漏极电极及一源极电极，其中所述栅极电极为所述扫描信号线的一部分并具有一开口，所述开口位于所述栅极电极的中央并延伸至扫描信号线的第一侧边；所述半导体层绝缘地设于所述栅极电极上方；所述漏极电极设于所述半导体层上且位置对应所述栅极电极的开口；所述源极电极自所述数据信号线的一侧边延伸出，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口；以及
补偿电极，自所述扫描信号线的第二侧边一体延伸出并对应所述栅极电极；所述补偿电极的面积与所述栅极电极的开口的面积相等，且所述补偿电极与所述数据信号线之间的距离大于3.5微米。
为达成本发明的前述目的，本发明另提供一种薄膜晶体管阵列基板，其包含：
基板；
扫描信号线，沿一水平方向设置于所述基板上，并具有一第一侧边与一相对于第一侧边的第二侧边；
数据信号线，沿一垂直方向设置于所述基板上而与所述扫描信号线彼此交错；
一薄膜晶体管，形成于所述扫描信号线与所述数据信号线交叉处附近，并包含一栅极电极、一半导体层、一漏极电极及一源极电极，其中所述栅极电极为所述扫描信号线的一部分并具有一开口，所述开口位于所述栅极电极的中央并延伸至扫描信号线的第一侧边；所述半导体层绝缘地设于所述所述栅极电极上方；所述漏极电极设于所述半导体层上且位置对应所述栅极电极的开口；所述源极电极自所述数据信号线的一侧边延伸出，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口；以及
补偿电极，自所述扫描信号线的第二侧边一体延伸出并对应所述栅极电极。
在本发明的一实施例中，所述栅极电极的开口呈矩形。
在本发明的一实施例中，所述漏极电极呈倒T字形而包含一水平部及一垂直部，所述水平部与所述扫描信号线的第一侧边及第二侧边平行，并对应所述栅极电极的开口；所述垂直部自所述水平部一侧延伸而与所述扫描信号线的第一侧边垂直，并对应所述栅极电极的开口。
在本发明的一实施例中，所述垂直部的宽度小于所述栅极电极的开口的宽度。
在本发明的一实施例中，所述补偿电极的面积与所述开口的面积相等。
在本发明的一实施例中，所述补偿电极呈梯形。
在本发明的一实施例中，所述补偿电极与所述数据信号线之间的距离大于3.5微米。
本发明另提供一种薄膜晶体管阵列基板的制法，所述制法包含下列步骤：
于基板上形成扫描信号线及补偿电极，其中所述扫描信号线包含一第一侧边、一相对于第一侧边的第二侧边及一开口，所述开口延伸至所述第一侧边；所述补偿电极自所述扫描信号线的第二侧边延伸出；
于扫描信号线上形成一第一绝缘层；
于第一绝缘层上形成一半导体层，其中所述半导体层对应位于所述开口上；以及
于基板上形成数据信号线、漏极电极及源极电极，其中所述数据信号线与所述扫描信号线彼此绝缘交错，所述漏极电极位于所述半导体层上并对应所述扫描信号线的开口，所述源极电极自所述数据信号线的一侧边延伸出而位于所述半导体层上，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口。
在本发明的一实施例中，所述制法进一步包含下列步骤：
于半导体层、漏极电极及源极电极上方形成第二绝缘层，其中所述第二绝缘层具有一开孔；所述开孔对应使所述漏极电极部分裸露；以及
于所述扫描信号线与数据信号线所定义的像素区内形成像素电极，其中所述像素电极通过所述第二绝缘层的开孔连接所述漏极电极。
在本发明的一实施例中，所述补偿电极呈梯形，且与所述数据信号线之间的距离大于3.5微米。
 有益效果
本发明主要是根据扫描信号线的开口，在扫描信号线的相对侧延伸出补偿电极，以避免开口提高扫描信号线阻值，且仍能减少漏极电极与栅极电极之间所产生的寄生电容。
 附图说明
图1是现有薄膜晶体管阵列基板的局部结构示意图。
图2是另一现有薄膜晶体管阵列基板的局部结构示意图
图3是本发明薄膜晶体管阵列基板第一实施例的局部结构示意图。
图4是本发明薄膜晶体管阵列基板第二实施例的局部结构示意图。
图5A~5E是本发明薄膜晶体管阵列基板一较佳实施例的制作流程图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明的薄膜晶体管阵列基板主要是由在一基板上设置薄膜晶体管阵列所构成。请参考图3所示，图3为本发明薄膜晶体管阵列基板第一实施例的局部结构示意图。如图3所示，除了所述基板(图中未示)，所述薄膜晶体管阵列基板还包含一扫描信号线1、一数据信号线2、一薄膜晶体管3及一补偿电极100。前述各元件的数目仅是用以方便说明及理解本发明，而非用以限制本发明的各元件的数目。
所述扫描信号线1沿一水平方向设置于所述基板上，并具有一第一侧边与一相对于第一侧边的第二侧边。
所述数据信号线2沿一垂直方向设置于所述基板上而与所述扫描信号线1彼此绝缘交错。
所述薄膜晶体管3形成于所述扫描信号线1与所述资料信号线2交叉处附近，并包含一栅极电极30、一半导体层31、一漏极电极32及一源极电极33。
所述栅极电极30为所述扫描信号线1的一部分，并具有一开口300，所述开口300位于所述栅极电极30的中央并延伸至扫描信号线1的第一侧边。在本实施例中，所述开口300优选是呈矩形。
所述半导体层31是绝缘地(优选是通过一绝缘层)设于所述栅极电极30上方。
所述漏极电极32设于所述半导体层31上且位置对应所述栅极电极30的开口300。本实施例中，所述漏极电极32优选是呈倒T字形，其包含有一水平部32a及一垂直部32b。所述水平部32a的延伸方向是与所述扫描信号线1的第一侧边及第二侧边平行，且所述水平部32a对应所述栅极电极30的开口300。所述水平部32a与所述栅极电极30部分重叠，且优选是所述水平部32a的边缘与所述栅极电极30重叠。所述垂直部32b自所述水平部32a的一侧延伸出，与所述扫描信号线1的第一侧边垂直，并且对应所述栅极电极30的开口300。所述垂直部32b的宽度优选是小于所述栅极电极30的开口300的宽度。
所述源极电极33自所述数据信号线2的一侧边延伸出，并沿着所述半导体层31的边缘环绕所述漏极电极32及所述栅极电极30的开口300。
所述补偿电极100自所述扫描信号线1的第二侧边一体延伸出并对应所述栅极电极30。本实施例中，所述补偿电极100的面积优选是与所述开口300的面积相等，且对应所述开口300呈矩形。
请参考图4所示，图4是本发明薄膜晶体管阵列基板第二实施例的局部结构示意图。本发明第二实施例相似于本发明第一实施例，并大致沿用相同组件名称，但与第一实施例不同之处在于：所述补偿电极100是呈梯形。且所述补偿电极100与所述资料信号线2之间的距离优选大于3.5微米。
由于在扫描信号线1的相对侧延伸出补偿电极100，本发明可避免因为开口300的形成导致扫描信号线1的阻值变大。
请参考图5A~5E所示，图5A~5E是本发明薄膜晶体管阵列基板一较佳实施例的制作流程图。配合图5A~5E，本发明薄膜晶体管阵列基板的制法包含下列步骤：
S1：于基板上形成扫描信号线1及补偿电极100，其中所述扫描信号线1包含一第一侧边、一相对于第一侧边的第二侧边及一开口300，所述开口300延伸至所述第一侧边；所述补偿电极100自所述扫描信号线1的第二侧边延伸出(如图5A所示)；
S2：于扫描信号线1上形成一第一绝缘层(图中未示)；
S3：于第一绝缘层上形成一半导体层31，其中所述半导体层31对应位于所述开口300上(如图5B所示)；
S4：于基板上形成数据信号线2、漏极电极32及源极电极33，其中所述数据信号线2与所述扫描信号线1彼此绝缘交错，所述漏极电极32呈倒T字形而位于所述半导体层31上，并对应所述扫描信号线1的开口300，所述源极电极33自所述数据信号线2的一侧边延伸出而位于所述半导体层31上，并沿着所述半导体层31的边缘环绕所述漏极电极32及所述栅极电极30的开口300(如图5C所示)；
S5：于半导体层31、漏极电极32及源极电极33上方形成第二绝缘层101，其中所述第二绝缘层101具有一开孔102；所述开孔102对应使所述漏极电极32部分裸露(如图5D所示)；以及
S6：于所述扫描信号线1与数据信号线2所定义的像素区内形成像素电极34，其中所述像素电极34通过所述第二绝缘层101的开孔102连接所述漏极电极32(如图5E所示)。
如此依照上述S1~S6的制作流程，即可完成如同图4所示的薄膜晶体管阵列基板。
综上所述，本发明主要是根据扫描信号线的开口，在扫描信号线的相对侧延伸出补偿电极，以补足扫描信号线面积原本减少的部份，进而可以避免其开口的形成造成扫描信号线阻值变大，同时可以保有减少漏极电极与栅极电极之间所产生的寄生电容的效果。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
工业实用性
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Claims (15)

  1. 一种薄膜晶体管阵列基板，其特征在于：所述薄膜晶体管阵列基板包含：
    基板；
    扫描信号线，沿一水平方向设置于所述基板上，并具有一第一侧边与一相对于第一侧边的第二侧边；
    数据信号线，沿一垂直方向设置于所述基板上而与所述扫描信号线彼此绝缘交错；
    薄膜晶体管，形成于所述扫描信号线与所述数据信号线交叉处附近，并包含一栅极电极、一半导体层、一漏极电极及一源极电极，其中所述栅极电极为所述扫描信号线的一部分并具有一开口，所述开口位于所述栅极电极的中央并延伸至扫描信号线的第一侧边；所述半导体层绝缘地设于所述栅极电极上方；所述漏极电极设于所述半导体层上且位置对应所述栅极电极的开口；所述源极电极自所述数据信号线的一侧边延伸出，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口；以及
    补偿电极，自所述扫描信号线的第二侧边一体延伸出并对应所述栅极电极；所述补偿电极的面积与所述栅极电极的开口的面积相等，且所述补偿电极与所述数据信号线之间的距离大于3.5微米。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其特征在于：
    所述栅极电极的开口呈矩形；以及
    所述漏极电极呈倒T字形而包含一水平部及一垂直部，所述水平部与所述扫描信号线的第一侧边及第二侧边平行，并对应所述栅极电极的开口；所述垂直部自所述水平部一侧延伸而与所述扫描信号线的第一侧边垂直，并对应所述栅极电极的开口。
  3. 如权利要求2所述的薄膜晶体管阵列基板，其特征在于：所述垂直部的宽度小于所述栅极电极的开口的宽度。
  4. 如权利要求3所述的薄膜晶体管阵列基板，其特征在于：所述补偿电极对应所述栅极电极的开口的形状。
  5. 如权利要求3所述的薄膜晶体管阵列基板，其特征在于：所述补偿电极呈梯形。
  6. 一种薄膜晶体管阵列基板，其特征在于：所述薄膜晶体管阵列基板包含：
    基板；
    扫描信号线，沿一水平方向设置于所述基板上，并具有一第一侧边与一相对于第一侧边的第二侧边；
    数据信号线，沿一垂直方向设置于所述基板上而与所述扫描信号线彼此绝缘交错；
    薄膜晶体管，形成于所述扫描信号线与所述数据信号线交叉处附近，并包含一栅极电极、一半导体层、一漏极电极及一源极电极，其中所述栅极电极为所述扫描信号线的一部分并具有一开口，所述开口位于所述栅极电极的中央并延伸至扫描信号线的第一侧边；所述半导体层绝缘地设于所述栅极电极上方；所述漏极电极设于所述半导体层上且位置对应所述栅极电极的开口；所述源极电极自所述数据信号线的一侧边延伸出，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口；以及
    补偿电极，自所述扫描信号线的第二侧边一体延伸出并对应所述栅极电极。
  7. 如权利要求6所述的薄膜晶体管阵列基板，其特征在于：所述栅极电极的开口呈矩形。
  8. 如权利要求7所述的薄膜晶体管阵列基板，其特征在于：所述漏极电极呈倒T字形而包含一水平部及一垂直部，所述水平部与所述扫描信号线的第一侧边及第二侧边平行，并对应所述栅极电极的开口；所述垂直部自所述水平部一侧延伸而与所述扫描信号线的第一侧边垂直，并对应所述栅极电极的开口。
  9. 如权利要求8所述的薄膜晶体管阵列基板，其特征在于：所述垂直部的宽度小于所述栅极电极的开口的宽度。
  10. 如权利要求9所述的薄膜晶体管阵列基板，其特征在于：所述补偿电极的面积与所述开口的面积相等。
  11. 如权利要求9所述的薄膜晶体管阵列基板，其特征在于：所述补偿电极呈梯形。
  12. 如权利要求6所述的薄膜晶体管阵列基板，其特征在于：所述补偿电极与所述数据信号线之间的距离大于3.5微米。
  13. 一种薄膜晶体管阵列基板的制法，其特征在于：所述制法包含下列步骤：
    于基板上形成扫描信号线及补偿电极，其中所述扫描信号线包含一第一侧边、一相对于第一侧边的第二侧边及一开口，所述开口延伸至所述第一侧边；所述补偿电极自所述扫描信号线的第二侧边延伸出；
    于扫描信号线上形成一第一绝缘层；
    于第一绝缘层上形成一半导体层，其中所述半导体层对应位于所述开口上；以及
    于基板上形成数据信号线、漏极电极及源极电极，其中所述数据信号线与所述扫描信号线彼此绝缘交错，所述漏极电极位于所述半导体层上并对应所述扫描信号线的开口，所述源极电极自所述数据信号线的一侧边延伸出而位于所述半导体层上，并沿着所述半导体层的边缘环绕所述漏极电极及所述栅极电极的开口。
  14. 如权利要求13所述薄膜晶体管阵列基板的制法，其特征在于：所述制法进一步包含下列步骤：
    于半导体层、漏极电极及源极电极上方形成第二绝缘层，其中所述第二绝缘层具有一开孔；所述开孔对应使所述漏极电极部分裸露；以及
    于所述扫描信号线与数据信号线所定义的像素区内形成像素电极，其中所述像素电极通过所述第二绝缘层的开孔连接所述漏极电极。
  15. 如权利要求14所述薄膜晶体管阵列基板的制法，其特征在于：所述补偿电极呈梯形，且与所述数据信号线之间的距离大于3.5微米。
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