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WO2012164719A1 - Substrat avec composant incorporé, et procédé de production dudit substrat - Google Patents

Substrat avec composant incorporé, et procédé de production dudit substrat Download PDF

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Publication number
WO2012164719A1
WO2012164719A1 PCT/JP2011/062693 JP2011062693W WO2012164719A1 WO 2012164719 A1 WO2012164719 A1 WO 2012164719A1 JP 2011062693 W JP2011062693 W JP 2011062693W WO 2012164719 A1 WO2012164719 A1 WO 2012164719A1
Authority
WO
WIPO (PCT)
Prior art keywords
component
layer
adhesive layer
conductive
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2011/062693
Other languages
English (en)
Japanese (ja)
Inventor
光昭 戸田
松本　徹
圭男 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meiko Electronics Co Ltd
Original Assignee
Meiko Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Electronics Co Ltd filed Critical Meiko Electronics Co Ltd
Priority to PCT/JP2011/062693 priority Critical patent/WO2012164719A1/fr
Priority to TW101117968A priority patent/TW201316856A/zh
Publication of WO2012164719A1 publication Critical patent/WO2012164719A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H10W70/093—
    • H10W72/073—
    • H10W72/9413—
    • H10W74/019—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a component-embedded substrate in which components are embedded and a method for manufacturing the same.
  • a component-embedded substrate in which components such as electronic components are embedded in an insulating layer is known (for example, see Patent Document 1).
  • an adhesive is applied to an area corresponding to the component when the component is mounted.
  • voids due to bubbles are locally generated in the adhesive.
  • Such a state is called a void, and this void expands in the subsequent reflow process, or causes peeling or a short circuit.
  • the adhesive is in contact with the circuit pattern that electrically connects the built-in components. For this reason, it is necessary that the adhesive is a material having an electrically good insulating property. Furthermore, the built-in component is electrically connected to the circuit pattern on the surface. For this reason, vias are also formed in the adhesive as a pretreatment. High connection reliability is required for a so-called conductive via in which conductivity is imparted to the via by plating or the like. Therefore, it is necessary to select an adhesive in consideration of laser processability for forming vias, plating coverage, and productivity.
  • the present invention is a component-embedded substrate that can prevent generation of voids in an adhesive and has improved electrical insulation reliability, and a method for manufacturing the same.
  • an insulating layer In the present invention, an insulating layer, a conductive layer formed on the surface of the insulating layer, an electrical or electronic component embedded in the insulating layer, and provided in the component and electrically connected to the conductive layer
  • the adhesive layer is formed only within a range substantially equal to the outer edge of the terminal, A component main body which is a portion other than the terminal in the component is in contact with only the insulating layer.
  • a plurality of the terminals are formed only on the peripheral edge of the component body, and the adhesive layer is formed on all of the terminals.
  • a plurality of the terminals are formed over the entire one surface of the component main body, and the adhesive layer is formed on a part or all of the terminals.
  • the adhesive layer is formed of an epoxy resin or a polyimide resin.
  • the adhesive layer has a thickness of 10 ⁇ m to 120 ⁇ m.
  • the adhesive layer is formed by stacking a plurality of adhesive portions of different materials or the same material.
  • the adhesive layer has at least a first adhesive part in contact with the conductive layer and a second adhesive part in contact with the component as the adhesive part, and the glass transition temperature of the first adhesive part is 40.
  • the glass transition temperature of the second adhesive portion is equal to or higher than the glass transition temperature of the first adhesive portion, and is in the range of 40 ° C. to 200 ° C. (TMA method).
  • the thickness of the first adhesive portion is 5 ⁇ m to 60 ⁇ m
  • the thickness of the second adhesive portion is 5 ⁇ m to 60 ⁇ m.
  • an adhesive layer forming step of forming the adhesive layer on the metal layer formed on the support plate, and bonding the terminal formed on the component to the adhesive layer, the adhesive layer A component-embedded board comprising: a component mounting step for mounting the component thereon; and a stacking step for stacking the insulating base material to be the insulating layer while pressing the component under vacuum.
  • the method further includes a conductive via forming step of forming a first conductive via by forming a via reaching the terminal from the outside of the metal layer after the laminating step and performing a conductive treatment on the via.
  • the support plate used in the adhesive layer forming step is an aluminum plate, and the metal layer is a copper foil attached to the aluminum plate.
  • the support plate used in the adhesive layer forming step is stainless steel, and the metal layer is a copper plating foil deposited on the stainless steel.
  • a plurality of either or both of a semiconductor component having a plurality of electrodes and a passive component having a plurality of electrodes are mounted in the component mounting step.
  • a circuit board having either a conductive circuit, a conductive via, a conductive through hole, or a combination thereof in addition to the insulating layer is disposed on the side of the component, and the conductive via forming step Then, a second conductive via for electrically connecting the conductive layer and the circuit board is formed.
  • the second conductive via is a filled via.
  • the connection by the second conductive via has an any layer structure.
  • the second adhesive portion is formed after the first adhesive portion is cured.
  • the second conductive via has a diameter corresponding to a depth of the via to be formed, so that a depth: diameter ratio (aspect ratio of the hole) is 1 or less. And a diameter equal to or larger than that of the first conductive via.
  • the insulating base material having a thermal expansion coefficient close to that of the component is used.
  • the adhesive layer is formed only in a range within approximately the same as the outer edge of the terminal.
  • the adhesive layer is the minimum necessary for mounting components. It will be formed in the size of. Therefore, voids can be prevented from occurring in the adhesive layer, and a highly reliable component-embedded substrate can be obtained.
  • the component main body which is parts other than the terminal in components contacts only the insulating layer. That is, this insulating layer is interposed between the adhesive layers. Therefore, high electrical insulation can be ensured between the terminals.
  • the adhesive layer corresponding to only the terminal portion it is possible to form a stable adhesive layer even in a component having unevenness due to electronic circuits on the surface. As a result, it is possible to ensure the formation of stable conductive vias and high electrical connection reliability.
  • the interval between the terminals via the component main body is wide, and thus the interval between the adhesive layers can be widened. As a result, further electrical insulation can be ensured.
  • the built-in component has a plurality of terminals formed over the entire surface of one side of the component body, and the adhesive layer is formed on a part of the terminal, the distance between the adhesive layers is increased. It can be provided and high electrical insulation can be secured. Even when a plurality of terminals are formed over the entire surface of one side of the component body, an adhesive layer may be formed for all the terminals if there is a sufficient space between the terminals. Even in this case, high electrical insulation can be ensured.
  • the adhesive layer is formed only in the same range as the outer edge of the terminal in the adhesive layer forming step, the adhesive layer and the terminal are bonded in the next component mounting step, and the next laminating step Press the insulating substrate.
  • the insulating base material enters between the metal layer and the component main body, and the adhesive layers are adjacent to each other via the insulating base material. Therefore, high insulation between the terminals can be ensured when the terminals are conducted in the subsequent process.
  • the lamination process is performed under vacuum, no voids are generated in the insulating base material.
  • the insulating base material a material having a thermal expansion coefficient close to that of the component is preferably used. As a result, the behavior of the insulating substrate in a high-temperature environment can be brought close to that of the component, and it is possible to reduce the load caused by heat, such as internal stress, and to improve the connection reliability more effectively. Can do.
  • FIG. 1 is a schematic cross-sectional view of a component built-in substrate according to the present invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. It is the schematic which shows in order the manufacturing method of
  • FIG. 1 It is a partial schematic diagram of another component built-in substrate according to the present invention. It is a partial schematic diagram of still another component-embedded substrate according to the present invention. It is AA sectional drawing of FIG. It is the schematic of another another component-embedded board which concerns on this invention.
  • a component-embedded substrate 1 has a component 3 embedded in an insulating layer 2.
  • the insulating layer 2 is formed by curing an insulating base material such as a prepreg.
  • the component 3 is an electrical or electronic component, and is a chip component provided with terminals 4 serving as electrodes or a multi-pin component such as WL-CSP having a large number of terminals (FIG. 1 shows an example of a chip component). ing). That is, the component 3 is formed of a plurality of terminals 4 and other component bodies 5.
  • a conductive layer 6 is formed on the surface of the insulating layer 2. In the figure, a double-sided substrate having conductive layers 6 formed on both sides is shown as an example.
  • the conductive layer 6 is a metal conductor such as copper, and is patterned.
  • the conductive layer 6 is electrically connected to the terminal 4 through the conductive via 7.
  • the conductive layer 6 is partially exposed and covered with a solder resist 8.
  • a conductive through hole 18 that penetrates the substrate 1 and is subjected to a conductive process is formed.
  • the conductive layers 6 on the front and back sides are electrically connected by the conductive through hole 18.
  • the substrate 1 is a so-called double-sided substrate.
  • An adhesive layer 10 is disposed between the terminal 4 and the conductive layer 6.
  • This adhesive layer 10 is formed only in a range substantially within the same range as the outer edge of the terminal 4 (FIG. 1 shows the adhesive layer 10 formed in a range equivalent to the outer edge of the terminal 4). Therefore, the component main body 5 which is a portion other than the terminal 4 in the component 3 is in contact with only the insulating layer 2.
  • the adhesive layer 10 is formed only in a range substantially within the outer edge of the terminal 4, and the adhesive layer 10 faces the conductive layer 6 of the terminal 4. Therefore, the adhesive layer 10 is formed in a minimum size necessary for mounting the component 3.
  • the adhesive layer 10 can be stably formed even when the surface of the component 3 has irregularities due to electronic circuits. Thereby, it is possible to ensure the formation of the stable conductive via 7 and the reliability of the high electrical connection thereby.
  • the entire surface including the component main body 5 is included.
  • the insulating layer 2 is formed between the terminals 4 by forming the adhesive layer 10 only for all of the terminals 4, so that high electrical insulation between the conductive vias 7 can be ensured.
  • an adhesive layer forming step is performed.
  • a substrate in which a metal layer 12 is formed on a support plate 11 is prepared.
  • the support plate 11 has a degree of rigidity required for process conditions.
  • the support plate 11 is formed of a rigid SUS (stainless steel) plate or aluminum plate as a support base material.
  • the metal layer 12 is formed by depositing a copper plating foil having a predetermined thickness.
  • the metal layer 12 is formed by attaching a copper foil if the support plate 11 is an aluminum plate.
  • the adhesive layer 10 is applied on the metal layer 12 by, for example, a dispenser or printing.
  • This adhesive layer 10 is formed of an epoxy-based or polyimide-based resin, and adheres the metal layer 12 and a terminal 4 described later.
  • the adhesive layer 10 is formed to have the same size as the terminal 4 to be bonded, specifically, within the same range as the outer edge of the bonding surface of the terminal 4, and the thickness is not limited, but is about 10 ⁇ m to 120 ⁇ m. Are preferred.
  • the component mounting process is performed.
  • an electrical or electronic component 3 such as a chip component is mounted on the metal layer 12.
  • the terminal 4 provided in the component 3 is placed on the adhesive layer 10.
  • the terminal and the adhesive layer 10 are bonded, and thus the metal layer 12 and the component 3 are connected via the adhesive layer 10.
  • the adhesive layer 10 is cured by heating after the components are placed.
  • a plurality of components 3 may be mounted.
  • the adhesive layer 10 is formed corresponding to the number of parts 3.
  • the component 3 in this case, either or both of a semiconductor component having a plurality of electrodes and a passive component having a plurality of electrodes may be used.
  • a lamination process is performed. This step is performed by laying up an insulating base material such as a prepreg on the side opposite to the side on which the metal layer 12 is disposed with respect to the component 3 and pressing it while heating under vacuum.
  • This press is performed using, for example, a vacuum press machine. Since there is a sufficient gap between the component body 5 and the metal layer 12 due to the presence of the adhesive layer 10, the insulating substrate enters between the component body 5 and the metal layer 12 by this pressing. The insulating layer 2 is formed. Since the lamination process is performed under vacuum, no voids are generated in the insulating base material. Thereafter, the support plate 11 is removed. A metal layer 12 is laminated on one surface of the insulating layer 2, and another metal layer 13 is laminated on the other surface.
  • a conductive via formation process is performed.
  • holes are formed using a laser or the like to form vias 14.
  • the via 14 is formed so as to reach the terminal 4 from the metal layer 12 through the adhesive layer 10. Further, depending on the structure, through conduction holes or conduction vias may be formed at this point in order to obtain electrical connection between the respective layers or front and back.
  • a desmear process is performed to remove the resin remaining during the via formation.
  • a plating process (conducting process) is performed, and plating is deposited in the via 14 to form the first conductive via 7.
  • a conductive layer forming step is performed. In this step, as shown in FIG. 8, a conductive pattern is formed on both surfaces of the insulating layer 2 using etching or the like, and the conductive layer 6 is formed. Then, a solder resist 8 is formed at a predetermined location (see FIG. 1).
  • the circuit board 15 having either a conductive circuit, a conductive via, a conductive through-hole, or a combination thereof in addition to the insulating layer 2 is disposed on the side of the component 3, and in the conductive via forming process If the second conductive via 16 for electrically connecting the conductive layer 6 and the circuit board 15 is formed, a substrate 17 as shown in FIG. 12 can be formed.
  • the substrate 17 is a so-called four-layer substrate.
  • the second conductive via 16 can be a filled via.
  • the connection by the second conductive via 16 may have an any layer structure.
  • the adhesive layer 10 is formed only in the range substantially equal to the outer edge of the terminal 4 in the adhesive layer forming step, and the adhesive layer 10 and the terminal 4 are formed in the next component mounting step.
  • the insulating base material is pressed in the subsequent laminating step. Thereby, an insulating base material enters between the metal layer 12 and the component main body 5 which should finally become the conductive layer 6, and the adhesive layers 10 are adjacent to each other through the insulating base material. Therefore, insulation between the terminals 4 can be ensured when the terminals 4 are electrically connected to the conductive layer 6 in the subsequent steps (conductive via forming step, conductive layer forming step).
  • the insulation between the conductive vias 7 can be ensured by the insulating layer 2.
  • the insulating performance can be excluded from the examination items, and the range of the adhesive selection can be widened.
  • the adhesive layer 10 may be formed in two layers.
  • the first adhesive portion 10a is printed on the metal layer 12 by a known coating method (preferably a printing method) and then cured, and further on the second adhesive layer 10a.
  • the adhesive layer 10 and the terminal 4 are adhered and cured in a component mounting process.
  • the adhesive layer 10 having a finally stable thickness can be obtained by forming the thin adhesive portion a plurality of times by one application.
  • about 5 ⁇ m to 60 ⁇ m is preferable in one application. That is, the optimal thickness of the first and second adhesive portions is 5 ⁇ m to 60 ⁇ m.
  • each contact bonding layer 10 can be arrange
  • the depth of the via 14 for connecting to a component can be adjusted by forming a plurality of adhesive portions and adjusting the thickness of the adhesive layer 10.
  • the adhesive layer 10 is not limited to two layers, and may be a plurality of layers.
  • the bonding portion 10a and the bonding portion 10b are not limited to the same material, and each material can be selected according to necessary characteristics and characteristics (for example, the bonding layer 10a has a role as a buffer material for stress). For example, it may be possible to select a material having a relatively low elastic modulus or glass transition point compared to the insulating base material, or to select an adhesive having excellent component adhesion for the purpose of improving the component adhesion of the adhesive layer 10b. ).
  • the glass transition temperature of the first adhesive portion 10a is 40 to 200 ° C. (TMA method)
  • the glass transition temperature of the second adhesive layer 10b is equal to or higher than the glass transition temperature of the first adhesive layer 10a. And it is in the range of 40 ° C. to 200 ° C. (TMA method).
  • the chip component is described as an example of the component 3.
  • an adhesive layer is formed on all the terminals 4 in the adhesive layer forming step.
  • the insulating base material may not easily enter between the component main body 5 and the metal layer 12 in the lamination process. Therefore, in this case, as shown in FIGS. 10 and 11, the adhesive layer 10 is selectively formed on a part of the terminal 4 to ensure the fluidity of the insulating base material. Specifically, as shown in FIG.
  • the insulating base material is A sufficient space can be secured. Furthermore, electrical insulation between the terminals 4 when finally becoming the substrate 1 can be ensured.
  • the description of the insulating layer 2 shown in FIG. 10 is omitted.
  • the selective formation of the adhesive layer 10 in this manner is effective even when the distance between the terminals 4 is small. Or it is effective also when the fluidity
  • the formation location of the adhesive layer 10 is appropriately selected according to the size of the component 3, the number of pins (number of terminals), the pin pitch (interval between terminals), and the material of the insulating base.
  • the adhesive layer 10 it is possible to reduce stress applied to the component body 5 when the insulating base material is cured and contracted. Even when a plurality of terminals 4 are formed over the entire surface of one side of the component body 5, the adhesive layer 10 is attached to all the terminals 4 when there is a sufficient space between the terminals 4. It may be formed. Even in this case, high electrical insulation between the terminals 4 can be ensured.
  • the adhesive layer and the insulating base material are formed according to the diameter of the conductive via to be formed. It can be formed selectively. For example, when a conductive via is formed with a small diameter via having a diameter of 50 ⁇ m or less, a material having good via formability can be selectively applied to the small diameter via portion in either the adhesive layer or the insulating substrate. It is possible to secure better via formation and reliability.
  • a sufficient gap can be provided between the terminals 4 (between the conductive vias 7) by forming the adhesive layer 10 having the same size as the terminal 4, or a slightly smaller or somewhat larger shape, and the insulating layer 2 is formed in this gap. Can be formed. Thereby, the insulation between the terminals 4 can be improved regardless of the insulation of the adhesive layer 10.
  • the insulating layer 2 is molded under vacuum using a vacuum pressure press, it is possible to suppress the generation of voids between the terminals 4 and to obtain high reliability.
  • the behavior of the substrate when heat-treated, such as during laminating press or surface mounting reflow, can be mitigated.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne un substrat (1) doté d'un composant incorporé, le substrat (1) étant muni d'une couche isolante (2), d'une couche conductrice (6) formée sur la surface de la couche isolante (2), un composant électrique ou électronique (3) encastré dans la couche isolante (2), une pluralité de bornes (4) disposées sur le composant (3) et reliées électriquement à la couche conductrice (6), et une couche adhésive (10) servant à faire adhérer les bornes (4) à la couche conductrice (6), la couche adhésive (10) n'étant formée que dans une région qui est approximativement la même que le bord extérieur des bornes (4), et un corps principal (5) de composant n'entrant en contact qu'avec la couche isolante (2), le corps principal (5) de composant étant une section du composant (3) excluant la section sur laquelle sont disposées les bornes (4).
PCT/JP2011/062693 2011-06-02 2011-06-02 Substrat avec composant incorporé, et procédé de production dudit substrat Ceased WO2012164719A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP2011/062693 WO2012164719A1 (fr) 2011-06-02 2011-06-02 Substrat avec composant incorporé, et procédé de production dudit substrat
TW101117968A TW201316856A (zh) 2011-06-02 2012-05-21 內藏元件之基板及其製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/062693 WO2012164719A1 (fr) 2011-06-02 2011-06-02 Substrat avec composant incorporé, et procédé de production dudit substrat

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WO2012164719A1 true WO2012164719A1 (fr) 2012-12-06

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WO (1) WO2012164719A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160118346A1 (en) * 2013-05-20 2016-04-28 Meiko Electronics Co., Ltd. Device embedded substrate and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024112364A (ja) * 2023-02-08 2024-08-21 Tdk株式会社 複合電子部品
JP2024116689A (ja) * 2023-02-16 2024-08-28 Tdk株式会社 複合電子部品

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JP2005039158A (ja) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd 部品内蔵モジュール及びその製造方法
JP2006523375A (ja) * 2003-04-01 2006-10-12 イムベラ エレクトロニクス オサケユキチュア 電子モジュールの製造方法及び電子モジュール
JP2008522397A (ja) * 2004-11-26 2008-06-26 イムベラ エレクトロニクス オサケユキチュア 電子モジュール及びその製造方法
JP2009200389A (ja) * 2008-02-25 2009-09-03 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法
JP2009289802A (ja) * 2008-05-27 2009-12-10 Tdk Corp 電子部品内蔵モジュール及びその製造方法
JP2010157664A (ja) * 2009-01-05 2010-07-15 Meiko:Kk 電気・電子部品内蔵回路基板とその製造方法
JP2010232292A (ja) * 2009-03-26 2010-10-14 Oki Semiconductor Co Ltd 半導体装置の製造方法及び半導体装置
JP2011060875A (ja) * 2009-09-08 2011-03-24 Panasonic Corp 電子部品内蔵基板及びその製造方法とこれを用いた半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006523375A (ja) * 2003-04-01 2006-10-12 イムベラ エレクトロニクス オサケユキチュア 電子モジュールの製造方法及び電子モジュール
JP2005039158A (ja) * 2003-07-18 2005-02-10 Matsushita Electric Ind Co Ltd 部品内蔵モジュール及びその製造方法
JP2008522397A (ja) * 2004-11-26 2008-06-26 イムベラ エレクトロニクス オサケユキチュア 電子モジュール及びその製造方法
JP2009200389A (ja) * 2008-02-25 2009-09-03 Shinko Electric Ind Co Ltd 電子部品内蔵基板の製造方法
JP2009289802A (ja) * 2008-05-27 2009-12-10 Tdk Corp 電子部品内蔵モジュール及びその製造方法
JP2010157664A (ja) * 2009-01-05 2010-07-15 Meiko:Kk 電気・電子部品内蔵回路基板とその製造方法
JP2010232292A (ja) * 2009-03-26 2010-10-14 Oki Semiconductor Co Ltd 半導体装置の製造方法及び半導体装置
JP2011060875A (ja) * 2009-09-08 2011-03-24 Panasonic Corp 電子部品内蔵基板及びその製造方法とこれを用いた半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160118346A1 (en) * 2013-05-20 2016-04-28 Meiko Electronics Co., Ltd. Device embedded substrate and manufacturing method thereof

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