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WO2011021357A1 - Circuit de réception de données - Google Patents

Circuit de réception de données Download PDF

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Publication number
WO2011021357A1
WO2011021357A1 PCT/JP2010/004944 JP2010004944W WO2011021357A1 WO 2011021357 A1 WO2011021357 A1 WO 2011021357A1 JP 2010004944 W JP2010004944 W JP 2010004944W WO 2011021357 A1 WO2011021357 A1 WO 2011021357A1
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WO
WIPO (PCT)
Prior art keywords
data signal
data
signal
delay
circuit
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Ceased
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PCT/JP2010/004944
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English (en)
Japanese (ja)
Inventor
武田憲明
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Panasonic Corp
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Panasonic Corp
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Publication date
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Publication of WO2011021357A1 publication Critical patent/WO2011021357A1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1532—Peak detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00136—Avoiding asymmetry of delay for leading or trailing edge; Avoiding variations of delay due to threshold

Definitions

  • the technology disclosed in this specification relates to a circuit that receives data read from a memory or the like.
  • a data signal output from a DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory
  • one bit is allocated in the period between the rising edge and the falling edge, and the signal level of that period is Data is represented by transitions.
  • the memory controller determines the level of the data signal at the timing of the rising edge and falling edge of the strobe signal. In order to make an accurate determination, it is necessary to adjust the phases of the data signal and the strobe signal so that the edge timing of the strobe signal is within a period in which the level of the data signal is constant.
  • Patent Document 1 describes a device that delays only the phase of the strobe signal DQS by 90 ° out of the data signal DQ and the strobe signal DQS sent from the memory in the same phase as an example of a technique for performing such adjustment. ing.
  • Digital televisions and digital video recorders are required to transmit large amounts of data at high speed within a limited time in order to process high-quality moving images.
  • An error in the transition timing of the data signal or strobe signal narrows the period during which data determination for each bit is possible. Since the time per bit decreases as the transmission speed increases, such a timing error has become a size that cannot be ignored for a period in which data determination is possible.
  • An object of the present invention is to reduce a steady delay difference between a rising edge and a falling edge of a data signal.
  • a data receiving circuit amplifies a data signal for transmitting data and outputs the amplified signal, and delays the output of the amplifying circuit in accordance with a first control signal and outputs the delayed signal as a first delayed data signal
  • a first delay circuit that delays the output of the amplifier circuit in accordance with a second control signal and outputs it as a second delayed data signal, an active edge of the first delayed data signal
  • a data signal reproduction circuit for generating and outputting a reproduction data signal based on an active edge of the second delayed data signal.
  • the timing of the rising edge and the timing of the falling edge of the data signal can be controlled independently. Therefore, it is possible to reduce the steady delay difference between the rising edge and the falling edge of the data signal.
  • the timing of the rising edge and the timing of the falling edge of the data signal can be controlled independently, the steady state between the rising edge and the falling edge of the data signal can be controlled.
  • the difference in delay can be reduced. Since a sufficient eye width in the eye pattern of the data signal can be secured, accurate data determination for the data signal can be performed.
  • FIG. 1 is a block diagram showing a configuration example of a data receiving circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram illustrating a configuration example of the comparator of FIG. 1 to which a data signal is input.
  • FIG. 3 is a circuit diagram illustrating a configuration example of the comparator of FIG. 1 to which a differential data strobe signal is input.
  • FIG. 4 is a block diagram illustrating a configuration example of the delay circuit of FIG.
  • FIG. 5 is a timing chart showing signal waveforms at various parts of the data receiving circuit of FIG. 1 when the edge timing of the data signal is ideal.
  • FIG. 6 is a timing chart showing signal waveform examples of each part of the data receiving circuit of FIG. 1 when the timing of the falling edge of the data signal is earlier than that of FIG.
  • FIG. 1 is a block diagram showing a configuration example of a data receiving circuit according to an embodiment of the present invention.
  • 1 includes a comparator 12, 18 as an amplifier circuit, an inverter 14, delay circuits 21, 22, 23, 24, D flip-flops (hereinafter referred to as D-FF) 32, 42, 44.
  • the D-FF 32 operates as a data signal reproduction circuit, and the D-FFs 42 and 44 each operate as a data determination unit.
  • the data receiving circuit 100 is used for a controller circuit of, for example, a DDR SDRAM (Double Data Rate Synchronous Dynamic Random-Access Memory).
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random-Access Memory
  • the memory 2 outputs a data signal DQ for transmitting data and data strobe signals DQS and DQSB.
  • the memory 2 is, for example, a DDR SDRAM.
  • the data strobe signal DQS periodically changes in level between “H” and “L”.
  • the data strobe signal DQSB is a signal having a phase opposite to that of the data strobe signal DQS, and the data strobe signals DQS and DQSB constitute a differential data strobe signal.
  • the comparator 12 amplifies and outputs the data signal DQ so that the amplitude becomes a predetermined magnitude. Specifically, the comparator 12 compares the voltage of the data signal DQ with the reference voltage VREF. When the data signal DQ is higher than the reference voltage VREF, the comparator 12 sets “H”, and when the data signal DQ is lower, “L”. Output as ROQ.
  • the inverter 14 inverts the data signal ROQ output from the comparator 12 and outputs the inverted signal as the data signal ROQB. Therefore, the timing of the rising edge of the data signal DQ is transmitted as the rising edge of the signal ROQ, and the timing of the falling edge of the data signal DQ is transmitted as the rising edge of the signal ROQB.
  • the comparator 18 amplifies and outputs the differential data strobe signals DQS and DQSB so that the amplitude becomes a predetermined magnitude. That is, the receiver circuit 18 outputs the data strobe signals DQS and DQSB with the higher potential at the “H” level and the lower potential at the “L” level. The comparator 18 outputs a positive-phase data strobe signal ROS and a negative-phase data strobe signal ROSB corresponding to the data strobe signals DQS and DQSB, respectively.
  • the timing of the rising edge of the data strobe signal DQS is transmitted as the timing of the rising edge of the signal ROS
  • the timing of the falling edge of the data strobe signal DQS is transmitted as the timing of the rising edge of the signal ROSB.
  • the delay circuit 21 delays the data signal ROQ according to the control signal CTL1, and outputs the obtained signal to the D-FF 32 as the delayed data signal DDQ.
  • the delay circuit 22 delays the data signal ROQB according to the control signal CTL2, and outputs the obtained signal to the D-FF 32 as a delayed data signal DDQB.
  • the delay circuit 23 delays the data strobe signal ROS according to the control signal CTL3, and outputs the obtained signal to the D-FF 42 as the delayed data strobe signal DDS.
  • the delay circuit 24 delays the data strobe signal ROSB in accordance with the control signal CTL4, and outputs the obtained signal to the D-FF 44 as a delayed data strobe signal DDSB.
  • the rising edges of the delayed data signals DDQ and DDQB and the delayed data strobe signals DDS and DDSB are all active edges.
  • the control signals CTL1 to CTL4 are input from a CPU or the like outside the data receiving circuit 100.
  • FIG. 2 is a circuit diagram showing a configuration example of the comparator 12 of FIG. 1 to which the data signal DQ is input.
  • the comparator 12 includes a differential amplifier 50 and inverters 58 and 59.
  • the differential amplifier 50 includes PMOS (p-channel Metal Oxide Semiconductor) transistors 51 and 52, NMOS (n-channel Metal Oxide Semiconductor) transistors 53 and 54, and a current source 55.
  • the source of the PMOS transistor 51 is supplied with the power supply voltage VDD, and the gate and drain thereof are connected to the node N51.
  • the source of the PMOS transistor 52 is supplied with the power supply voltage VDD, and the gate and drain thereof are connected to the nodes N51 and N52, respectively.
  • the source and drain of the NMOS transistor 53 are connected to nodes N54 and N51, respectively, and the data signal DQ is input to the gates thereof.
  • the source and drain of the NMOS transistor 54 are connected to nodes N54 and N52, respectively, and the reference voltage VREF is input to the gates thereof.
  • the current source 55 is connected between the node N54 and the ground GND.
  • the differential amplifier 50 compares the data signal DQ output from the SDRAM 2 with the reference voltage VREF, and outputs “H” as the potential of the node N52 when the potential of the data signal DQ is higher than the reference voltage VREF. In this case, “L” is output.
  • Inverter 58 inverts and outputs the potential of node N52, and inverter 59 further inverts the output of inverter 58 and outputs it as data signal ROQ. Therefore, the logic level of node N52 is output as data signal ROQ.
  • FIG. 3 is a circuit diagram showing a configuration example of the comparator 18 of FIG. 1 to which the differential data strobe signals DQS and DQSB are inputted.
  • the comparator 18 includes a differential amplifier 60 and inverters 68 and 69.
  • the differential amplifier 60 includes PMOS transistors 61 and 62, NMOS transistors 63 and 64, and a current source 65.
  • the source of the PMOS transistor 61 is supplied with the power supply voltage VDD, and the gate and drain thereof are connected to the node N61.
  • the source of the PMOS transistor 62 is supplied with the power supply voltage VDD, and the gate and drain thereof are connected to the nodes N61 and N62, respectively.
  • the source and drain of the NMOS transistor 63 are connected to the nodes N64 and N61, respectively, and the data strobe signal DQS is input to its gate.
  • the source and drain of the NMOS transistor 64 are connected to the nodes N64 and N62, respectively, and the data strobe signal DQSB is input to the gate.
  • the current source 65 is connected between the node N64 and the ground GND.
  • the differential amplifier 60 compares the data strobe signal DQS output from the SDRAM 2 with the data strobe signal DQSB, and outputs “H” as the potential of the node N62 when the potential of the data strobe signal DQS is higher than the data strobe signal DQSB. In other cases, “L” is output.
  • Inverter 68 inverts the potential of node N62 and outputs the inverted signal as data strobe signal ROSB.
  • Inverter 69 further inverts the output of inverter 68 and outputs it as data strobe signal ROS. Therefore, the logic level of node N62 is output as data strobe signal ROS.
  • FIG. 4 is a block diagram showing a configuration example of the delay circuit 21 in FIG.
  • the delay circuit 21 includes N (N is a natural number) delay cells 72_1, 72_2,..., 72_N, switches 74_0, 74_1, 74_2,. ing.
  • Delay cells 72_1 to 72_N have inverters INN and INP, respectively, and delay the input signal and output it.
  • the delay circuit 21 gives a delay according to the control signal CTL1 to the data signal ROQ input to the terminal IN and outputs the data signal from the terminal OUT.
  • the delay circuits 22 to 24 are configured in the same manner as the delay circuit 21.
  • the delay circuits 21 and 22 include the minimum value of the period from the active edge (rising edge) of the delayed data signal DDQ to the active edge (rising edge) of the delayed data signal DDQB, and the delay data signal DDQ from the active edge of the delayed data signal DDQB.
  • the data signal ROQ or ROQB is delayed so that the minimum value of the period until the active edge becomes equal.
  • a CPU or the like outside the data receiving circuit 100 changes the delay of one or both of the delay circuits 21 and 22 from the minimum value to the maximum value by the control signals CTL1 and CTL2, and outputs normal data
  • the values of the control signals CTL1 and CTL2 as described above are obtained.
  • the margin is made as large as possible, the minimum value of the period from the active edge of the delayed data signal DDQ to the active edge of the delayed data signal DDQB, and the active edge of the delayed data signal DDQB to the active edge of the delayed data signal DDQ
  • the optimum values of the control signals CTL1 and CTL2 can be obtained so that the minimum value of the period until is equal.
  • control signals CTL1 and CTL2 may be obtained in the same manner and the obtained control signals CTL1 and CTL2 may be continuously used.
  • a power supply voltage VDD and delayed data signals DDQ and DDQB are supplied to an input terminal D, a clock terminal, and a reset terminal R of the D-FF 32, respectively.
  • the D-FF 32 generates a reproduction data signal CDQ having a rising edge corresponding to the active edge of the delayed data signal DDQ and a falling edge corresponding to the active edge of the delayed data signal DDQB. Output from.
  • the D-FF 32 changes the reproduction data signal CDQ from “L” to “H”.
  • the D-FF 32 changes the reproduction data signal CDQ from “H” to “L”. That is, the D-FF 32 combines the delayed data signals DDQ and DDQB to generate and output a reproduction data signal CDQ indicating the rising edges of these two signals.
  • the timing of the rising edge of the reproduction data signal CDQ is the timing obtained by delaying the timing of the rising edge of the data signal DQ by the delay circuit 21.
  • the timing of the falling edge of the reproduction data signal CDQ is the timing obtained by delaying the timing of the falling edge of the data signal DQ by the delay circuit 22. That is, according to the data receiving circuit of FIG. 1, it is possible to independently delay the timing of the rising edge and the falling edge of the data signal DQ.
  • FIG. 5 is a timing chart showing signal waveforms of respective parts of the data receiving circuit 100 of FIG. 1 when the edge timing of the data signal DQ is ideal. As shown in FIG. 5, when the timings of the rising edge and falling edge of the data signal DQ are ideal timings, for example, the CPU external to the data receiving circuit 100 may receive the delay given by the delay circuits 21 and 22. Control signals CTL1 and CTL2 are generated and output to delay circuits 21 and 22 so that the amounts are substantially equal.
  • the CPU generates the control signals CTL3 and CTL4 so that the delay amount given by the delay circuits 23 and 24 becomes a delay amount obtained by adding a delay corresponding to a phase difference of 90 ° to the delay amount of the delay circuit 21.
  • the phase difference of 90 ° corresponds to a quarter cycle of the data strobe signal DQS.
  • the edge timings of the delayed data strobe signals DDS and DDSB are set in the middle of a period in which the level of the reproduction data signal CDQ is constant.
  • the reproduction data signal CDQ and the delayed data strobe signal DDS are supplied to the input terminal D and the clock terminal of the D-FF 42, respectively.
  • a reproduction data signal CDQ and a delayed data strobe signal DDSB are supplied to an input terminal D and a clock terminal of the D-FF 44, respectively.
  • the D-FFs 42 and 44 perform data determination according to the rising edge and falling edge of the data strobe signal DQS, respectively.
  • the D-FF 42 determines the value of the reproduction data signal CDQ at the rising edge of the delayed data strobe signal DDS obtained by delaying the data strobe signal DQS by 90 °, and outputs the determination value FIR.
  • the D-FF 44 determines the value of the reproduction data signal CDQ at the rising edge of the delayed data strobe signal DDSB obtained by delaying the data strobe signal DQSB by 90 °, and outputs the determination value FIF. Since the value is determined at the center of the period when the level of the reproduction data signal CDQ is constant, the value can be determined accurately.
  • FIG. 6 is a timing chart showing signal waveform examples of each part of the data receiving circuit 100 of FIG. 1 when the timing of the falling edge of the data signal DQ is earlier than that of FIG.
  • the “H” period of the data signal ROQ output from the comparator 12 is shorter. In this state, the eye width in the eye pattern of the data signal ROQ is narrow, and it can be seen that the setup margin / hold margin at the time of data determination is narrow.
  • the delay circuit 22 delays the delayed data signal DDQB having a rising edge corresponding to the falling edge of the data signal DQ by the time td.
  • the operation of the data receiving circuit 100 of FIG. 1 is the same as that of FIG.
  • the reproduction data signal CDQ output from the D-FF 32 becomes the same as in the case of FIG.
  • the delay circuits 21 and 22 independently control the timing of the rising edge and the falling edge of the data signal DQ, according to the data receiving circuit of FIG. 1, the rising edge and the falling edge of the data signal The difference in steady delay from the edge can be reduced. Since a sufficient eye width in the eye pattern of the reproduced data signal CDQ can be secured, accurate data determination for the data signal can be performed.
  • the delay circuits 21 to 24 can easily adjust the delay time according to the number of the delay cells 72_1 to 72_N passing through the signal. Therefore, as compared with the case where the edge timing is corrected by reducing the absolute value of the slew rate of the signal, the delay circuits 21 to 24 have a wide correction range, and jitter generated when the absolute value of the slew rate is reduced. Can be prevented.
  • the delay circuits 23 and 24 independently correct the timings of the rising edges of the data strobe signals DQS and DQSB, it is possible to ensure the setup margin / hold margin at the time of data determination. .
  • the case where the falling edge of the data signal DQ is earlier than ideal has been described as an example. However, when the falling edge is later than ideal, the delay of the delay circuit 22 may be reduced. When the rising edge of the data signal DQ is earlier than ideal, the delay of the delay circuit 21 is increased, and when it is late, the delay of the delay circuit 21 is decreased. The timing correction of the rising edge of the data signal DQ by the delay circuit 21 and the timing correction of the falling edge of the data signal DQ by the delay circuit 22 may be performed simultaneously.
  • the timing of the rising edge of the data signal DQ is made to correspond to the timing of the rising edge of the data strobe signal ROS has been described, but it may be made to correspond to the timing of the falling edge of the signal ROS.
  • the timing of the falling edge of the data signal DQ is made to correspond to the timing of the rising edge of the delayed data strobe signal ROSB has been described, the timing may be made to correspond to the timing of the falling edge of the signal ROSB.
  • the rising edges of the delayed data signals DDQ and DDQB and the delayed data strobe signals DDS and DDSB are active edges.
  • any of the falling edges of these signals may be the active edge.
  • the D-FFs 32, 42, and 44 may be operated according to the active edge.
  • the D-FF 32 generates a reproduction data signal CDQ having a falling edge corresponding to the active edge of the delayed data signal DDQ and a rising edge corresponding to the active edge of the delayed data signal DDQB, and outputs it from the output terminal Q. Good.
  • the comparator 12 in FIG. 1 may have any configuration as long as it is a circuit that amplifies the data signal DQ to a logic level “H” or “L” and outputs it.
  • the comparator 18 in FIG. 1 may have any configuration as long as it is a circuit that amplifies and outputs the data strobe signals DQS and DQSB to logic levels “H” and “L”.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)

Abstract

On peut réduire une différence constante de retard entre un front montant et un front descendant d'un signal de données. Un circuit de réception de données comprend un circuit d'amplification amplifiant et émettant un signal de données transmettant des données, un premier circuit de retard retardant la sortie du circuit d'amplification conformément à un premier signal de commande et la délivrant en tant que premier signal de données de retard, un second circuit de retard retardant la sortie du circuit d'amplification conformément à un second signal de commande et l'émettant en tant que second signal de données de retard, et un circuit de reproduction de signal de données générant et émettant un signal de données de reproduction sur la base d'un front actif du premier signal de données de retard et d'un front actif du second signal de données de retard.
PCT/JP2010/004944 2009-08-17 2010-08-05 Circuit de réception de données Ceased WO2011021357A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009188569A JP2011041140A (ja) 2009-08-17 2009-08-17 データ受信回路
JP2009-188569 2009-08-17

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WO2011021357A1 true WO2011021357A1 (fr) 2011-02-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016197275A (ja) * 2015-04-02 2016-11-24 富士通株式会社 情報処理装置、情報処理システム、情報処理装置の制御プログラムおよび情報処理装置の制御方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8742627B2 (en) * 2011-03-01 2014-06-03 Tdk Corporation Wireless power feeder
US9524763B2 (en) * 2014-06-12 2016-12-20 Qualcomm Incorporated Source-synchronous data transmission with non-uniform interface topology

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01108809A (ja) * 1987-10-21 1989-04-26 Tdk Corp ディレーライン
JPH0332137A (ja) * 1989-06-28 1991-02-12 Fujitsu Ltd 信号伝送装置
JPH0856143A (ja) * 1994-08-10 1996-02-27 Advantest Corp 周期クロックの可変遅延回路
JP2001195884A (ja) * 1999-11-05 2001-07-19 Mitsubishi Electric Corp 半導体装置
WO2002099810A1 (fr) * 2001-05-30 2002-12-12 Hitachi, Ltd. Dispositif semi-conducteur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01108809A (ja) * 1987-10-21 1989-04-26 Tdk Corp ディレーライン
JPH0332137A (ja) * 1989-06-28 1991-02-12 Fujitsu Ltd 信号伝送装置
JPH0856143A (ja) * 1994-08-10 1996-02-27 Advantest Corp 周期クロックの可変遅延回路
JP2001195884A (ja) * 1999-11-05 2001-07-19 Mitsubishi Electric Corp 半導体装置
WO2002099810A1 (fr) * 2001-05-30 2002-12-12 Hitachi, Ltd. Dispositif semi-conducteur

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016197275A (ja) * 2015-04-02 2016-11-24 富士通株式会社 情報処理装置、情報処理システム、情報処理装置の制御プログラムおよび情報処理装置の制御方法

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