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WO2002099810A1 - Dispositif semi-conducteur - Google Patents

Dispositif semi-conducteur Download PDF

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Publication number
WO2002099810A1
WO2002099810A1 PCT/JP2001/004553 JP0104553W WO02099810A1 WO 2002099810 A1 WO2002099810 A1 WO 2002099810A1 JP 0104553 W JP0104553 W JP 0104553W WO 02099810 A1 WO02099810 A1 WO 02099810A1
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WO
WIPO (PCT)
Prior art keywords
input
clock
signal
internal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2001/004553
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English (en)
Japanese (ja)
Inventor
Takeshi Sakata
Satoru Hanzawa
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2003502836A priority Critical patent/JP4513323B2/ja
Priority to PCT/JP2001/004553 priority patent/WO2002099810A1/fr
Publication of WO2002099810A1 publication Critical patent/WO2002099810A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device capable of inputting and outputting a signal at a high frequency. Further, the present invention relates to a signal input buffer circuit. Background art
  • FIG. 2 schematically shows a configuration example of an input section of a semiconductor device having a synchronous interface.
  • Input buffers IBUF are provided corresponding to the input signals IN0, INI,... and the external clock CLK, respectively, and compared with the reference voltage Vref, the internal signals IN0I, II,... Get CKI.
  • FIG. 3 shows the input timing specifications when using the input unit as shown in FIG.
  • the setup time ts and hold time th of the input signal are defined with respect to the rising edge of the clock. That is, for the input signal INrl which rises from low level to high level and becomes '1', the setting is made after the input signal INrl rises and crosses the reference voltage Vref at the rising edge of the clock CLK and crosses the reference voltage Vref. If the time is longer than the startup time ts, it is guaranteed that the input signal INrl is determined as'.
  • the signal crosses the reference voltage Vref at the rising edge of the clock CLK and then crosses the reference voltage Vref at the falling edge of the input signal INfl. If the hold time is longer than th, it is guaranteed that the input signal INfl is determined to be '.
  • the setup time ts of the input signal INfO that falls to '0' is defined by how fast it should fall before the rise of the clock CLK, while the input signal INrO rising from the '0' state The hold time is defined by how long after the rising edge of the clock CLK it is allowed to rise.
  • the reference voltage Vref is not always set to half the voltage ( ⁇ + VIL) / 2 for the high level VIH and low level VIL of the input signal. If the resistor is terminated at (VIH + VIL) / 2, the reference voltage Vref may be intentionally shifted from (VIH + VIL) / 2 to reduce the shoot-through current in the input buffer. .
  • the case where the reference voltage Vref is lower than half the voltage (VIH + VIL) / 2 is shown. In this case, the time required for the falling signal INf to reach the reference voltage Vref becomes longer than the rising signal INr. Furthermore, it is difficult to make the delay time of the input buffer receiving the input signal the same when it changes to “1” and when it changes to “0”.
  • a delay time difference ⁇ 1 occurs between the rising internal signal INrl and the falling internal signal INf I.
  • the case where the falling internal signal INfl is delayed from the rising internal signal INrl is shown, but the opposite case is naturally possible.
  • the timing specifications as shown in Fig. 3 must enable normal operation even with this delay time difference At. Therefore, the setup time ts and the hold time th of the input signal cannot be reduced.
  • Literature 2 proposes a method to reduce the difference between the rise time and fall time of the output of the input buffer, but does not consider the delay time difference of the input signal itself. Therefore, the effect of reducing the setup time and hold time of the input signal is small with the method of Reference 2.
  • double data rate SDRAM uses a differential clock as shown in Figure 5.
  • the internal clock CKId is generated by comparing the clock CLKt (toner clock) and the clock C and Kb (bar clock) of the bar with the input buffer IBUF.
  • Figure 6 shows the input timing specification in this case. Entering The setup time ts and hold time th of the force signal are defined for the intersection of the differential clocks CLKt and CLKb. Even in this method, a delay time difference occurs as shown in FIG.
  • the time to the intersection is 1 / (l / tr + 1 / tf), and the shorter of the rise time tr and the fall time tf Strong influence.
  • Vref deviates from half the voltage (VIH + VIL) / 2
  • the delay time of the input buffer is large because the differential signal is only differential and the differential signal amplitude is large. If an input buffer with the same configuration is used, the delay time of the clock is reduced by the clock delay time td. As a result, the influence of the delay time difference between the rising and falling signal transmissions is not always small, but may be rather large. Therefore, even if a differential clock is used, the setup time ts and the hold time th of the input signal cannot be reduced.
  • an object of the present invention is to provide a semiconductor device which can operate stably with a short setup time and a hold time and can input and output a signal at a high frequency even if there is a delay time difference between a rise and a fall of a signal. It is in. Disclosure of the invention
  • the typical configuration of the present invention is as follows. Input signals IN0, INI,... and external clock pairs CLKt, CLKb are input. Input buffers IBUF are provided corresponding to them, and internal signals ⁇ , IN1 I,... and internal clock pairs CKIt, CKIb are obtained. The signals IN0I, II, ... are input to the latch circuit LP, the operation of the latch circuit is controlled by the internal clock pair CKIt, CKIb, and the output signals INOL, IN1L, ... of the latch circuit LP are used for the operation of the internal circuit. Configure the device.
  • the latch circuit includes a first NM ⁇ S transistor Mil and a first NM ⁇ S transistor Mil.
  • a tri-state inverter including a PMOS transistor MP1, a second NMOS transistor MN2, and a second PM ⁇ S transistor MP2, and a gate of the first NMOS transistor and the first PM ⁇ S transistor.
  • the semiconductor device is configured such that a signal Db corresponding to the internal clock pair is input and the internal clock pair is input to the gates of the second NMOS transistor and the second PMOS transistor, respectively.
  • FIG. 1 is a diagram showing an input unit of a semiconductor device according to the present invention.
  • FIG. 2 is a diagram illustrating an example of an input unit of a conventional semiconductor device.
  • FIG. 3 is a diagram showing timing specifications of an input section of a conventional semiconductor device.
  • FIG. 4 is a diagram schematically showing conventional signal transmission.
  • FIG. 5 is a diagram showing another example of the input unit of the conventional semiconductor device.
  • FIG. 6 is a diagram showing a timing specification of the input unit in FIG.
  • FIG. 7 is a diagram schematically showing signal transmission at the input unit in FIG.
  • FIG. 8 is a diagram showing a timing specification of the input unit in FIG.
  • FIG. 9 is a circuit diagram of a latch circuit suitable for the input unit of FIG.
  • FIG. 10 and 11 are diagrams showing the operation of the latch circuit of FIG.
  • FIG. 12 is a circuit diagram of another configuration example of the latch circuit.
  • FIG. 13 is a circuit diagram of still another configuration example of the latch circuit.
  • FIG. 14 is a circuit diagram of a flip-flop circuit suitable for the input unit of FIG.
  • FIG. 15 is a diagram showing the operation of the flip-flop circuit of FIG.
  • FIG. 16 is a circuit diagram of another configuration example of the flip-flop circuit.
  • FIG. 17 is a diagram showing the operation of the flip-flop circuit of FIG. Figure 18 shows a configuration example of the input unit using a phase-locked loop. It is.
  • FIG. 19 is a circuit diagram of a configuration example of a phase / frequency detector used in the phase lock loop in FIG.
  • FIG. 20 is a circuit diagram of a configuration example of a charge pump circuit used in the phase locked loop in FIG.
  • FIG. 21 is a circuit diagram of a configuration example of a voltage controlled oscillator used in the phase lock loop in FIG.
  • FIG. 22 is a diagram illustrating a configuration example of an input unit using a delay locked loop.
  • FIG. 23 is a circuit diagram of a configuration example of a phase comparator used in the delay locked loop in FIG.
  • FIG. 24 is a circuit diagram of a configuration example of a pressure control delay device used in the delay locked loop in FIG.
  • FIG. 25 is a circuit diagram of a configuration example of the input buffer.
  • FIG. 26 is a circuit diagram of another configuration example of the input buffer.
  • FIG. 27 is a circuit diagram of still another configuration example of the input buffer.
  • FIG. 28 is a circuit diagram of still another configuration example of the input buffer.
  • FIG. 29 is a diagram illustrating a configuration example of the output unit.
  • FIG. 30 is a circuit diagram of a configuration example of the output buffer.
  • FIG. 31 is a diagram showing an interface according to the present invention between two semiconductor integrated circuits.
  • FIG. 32 is a diagram illustrating a signal transmission unit at the interface of FIG.
  • FIG. 33 shows the interface according to the invention in the form of a bus.
  • FIG. 34 is a diagram illustrating a signal transmission unit at the interface of FIG.
  • FIG. 35 is a diagram illustrating a configuration example of a synchronous DRAM.
  • FIG. 36 is a diagram showing a configuration example of the memory array in FIG.
  • FIG. 37 is a diagram showing a configuration example of the sense amplifier and the mat in FIG.
  • FIG. 38 is a diagram showing a read operation of the synchronous DRAM of FIG.
  • FIG. 39 is a diagram showing a write operation of the synchronous DRAM of FIG.
  • FIG. 40 is a circuit diagram of a configuration example of a data strobe input circuit in the synchronous DRAM of FIG.
  • FIG. 41 is a circuit diagram of a configuration example of a data input circuit in the synchronous DRAM of FIG.
  • FIG. 42 is a diagram showing operations of the data strobe input circuit of FIG. 40 and the data input circuit of FIG.
  • FIG. 43 shows a read operation at the double data rate.
  • FIG. 44 shows a write operation at the double data rate.
  • FIG. 45 is a circuit diagram of a configuration example of a data strobe input circuit for a double data rate.
  • FIG. 46 is a circuit diagram of a configuration example of a data input circuit for a double data rate.
  • FIG. 47 shows the operation of the data strobe input circuit of FIG. 45 and the data input circuit of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as a single-crystal silicon by a known integrated circuit technology such as a CMOS (Complementary MOS transistor). .
  • CMOS Complementary MOS transistor
  • the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the body.
  • the drawing shows the connection of the substrate potential of the M0S transistor. Is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally. Unless otherwise specified, the low level of the signal is “0”, no, and the low level is “1”.
  • FIG. 1 schematically shows an input section of a semiconductor device according to the present invention.
  • the latch circuit LP for the input signals INO, IN1, ... is controlled by the internal clock pair CKIt, CKIb generated from the external clock pair CLKt, CLKb power of the true and bar.
  • Input buffers IBUF are provided corresponding to the input signals IN0, INI,... and the external clock pair CLKt, CLKb, respectively, and compared with the reference voltage Vref, the internal signals: LN0 I, IN1 I,... and the internal clock pair CKIt, CKIb Get.
  • the latch circuit LP which is a temporary storage circuit, and the operation of the latch circuit is controlled by the internal clock pair CKIt, CKIb.
  • the output signals IN0L, IN1L, ... of the latch circuit LP are used to operate the internal circuit of the semiconductor device.
  • a clock driver is provided for the internal clock pair CKIt and CKIb.
  • the external clock pair CLKt and CLKb of the crew and bar are respectively received by the same input buffer as the other input signals, and the internal clock pair CKI t and CKIb are generated, and both of them are generated.
  • both the rise and fall of the external clock can be used for the timing control of the latch circuit LP.
  • the rising of the input signal can be determined by the rising of the external clock
  • the falling of the input signal can be determined by the falling of the external clock.
  • FIG. 8 shows input timing specifications when using the input unit as shown in FIG.
  • the feature is that the setup time and the hold time of the input signal are defined with respect to the rising edge of the rising edge and to the falling edge of the rising edge.
  • the setup time tsl of the input signal INrl which rises from low level to high level, defines how fast it should rise before the rise of the clock CLKt.
  • the setup time tsl is equal to or longer than the time when the reference voltage Vref is crossed at the rise of the input signal INrl and the time when the reference voltage Vref is crossed at the rise of the clock CLKt, the input signal INrl is determined to be '. Guarantee that On the other hand, the hold time of the input signal INfl, which falls from the high level, which is the state of '1, to the mouth level, is specified by how long after the falling edge of the clock CLKb of the bar.
  • the setup time tsO of the input signal INfO that falls to '0' is defined by how fast it should fall before the fall of the clock CLKb of the bar, while the input signal rising from the '0' state
  • the hold time of INrO is defined by how long after the rising edge of the clock CLKt of the tower can rise.
  • FIG. 9 shows a configuration example of the latch circuit LP in FIG. The feature is that the CKt and CKb pairs of the internal connectors of the Toll and No.
  • INV5 is a well known CMO S inverter, N MO S transistor and PMO S NM_ ⁇ and configured c P MO S transistor MP1, MP2 by one by one transistor S transistors MN1, MN2, the latch It constitutes the first tri-state inverter that determines whether the circuit is in a transparent (or through) state or a latched state.
  • the PMOS transistors MP3 and MP4 and the NMOS transistors MN3 and MN4 form a second tri-state inverter that provides positive feedback to maintain the level in the latched state.
  • the internal clock pair CKt and CKb correspond to the internal clock pair CKIt and CKIb in Figure 1.
  • One of the input signals IN0, INI, ... in Fig. 1 is input to input D, and the output Q is a signal corresponding to one of the output signals IN0L, IN1L, ... in Fig. 1.
  • the PM ⁇ transistor MP2 and the NM ⁇ S transistor MN2 are turned on (conduction state), and the first tri-state inverter operates as an inverter. Then, the PMO transistor MP4 and the NMOS transistor MN4 are turned off (non-conducting state), and the second tri-state inverter is in a high impedance state. As a result, the latch circuit enters a transparent state, and the input D is transmitted to the output Q as it is.
  • the timing at which the latch circuit switches from the transparent state to the latch state will be described. If the rising edge of the internal clock CKt. Of the tower and the falling edge of the internal clock CKb of the bar are substantially simultaneous, the state is switched to the latch state at that timing. However, in the configuration of the input section as shown in Fig. 1, the rise and fall of the internal clock CKt and the internal gap of the bar occur due to the delay time difference between the rise and fall of the external clock versus the CLKt and CLKb paths. There is a time difference from the falling edge of the clock CKb. For example, suppose that the falling of the internal clock CKb of the bar is slower than the rising of the internal clock CKt of the true. In this case, when the internal node Db of the latch circuit changes while both the true internal clock CKt and the bar internal clock CKb are at the high level, it is a problem whether the change is transmitted to the output Q.
  • the internal node Db rises and the NMOS transistor MN1 is turned on, the internal clock CKb of the bar is at a high level, and the NM ⁇ S transistor MN2 is turned on, so that the output Q is at a low level. Due to the inverter INV5, the internal node Qb becomes high level, the NMOS transistor MN3 is turned on, and positive feedback that keeps the output Q low level operates. That is, the falling state of input D is transparent until the falling edge of the internal clock CKb of the bar.
  • the fall of the input D is latched by the fall of the internal clock CKb of the bar. It becomes a state, and it is in a transparent state until the rising edge of the internal clock CKt of the input signal D with respect to the rising edge of the input D. Therefore, when the latch circuit switches from the transparent state to the latch state, the rising edge of the input D is the rising edge of the true internal clock CKt, and the falling edge of the input D is the internal clock CKb of the bar. Is determined by the falling edge of Thus, the rising of the input signal can be determined by the rising of the external clock, and the falling of the input signal can be determined by the falling of the external clock.
  • FIG. 12 shows another example of the configuration of the latch circuit, which is characterized in that it is a dynamic circuit. It consists of an inverter INV0 and PMOS transistors MP1, MP2 and NM ⁇ S transistors MN1 and MN2 that constitute a first 3-state inverter. The second 3-state inverter and the inverter INV5 are removed from the latch circuit of FIG. It has a configuration. Similarly to the latch circuit of Fig. 9, this latch circuit switches from the transparent state to the latch state at the rising edge of the input D at the rising edge of the internal clock CKt, which is the falling edge of the input D.
  • the latch circuit of Fig. 9 maintains the voltage of the output Q by positive feedback, but in this circuit, the tri-state inverter becomes high impedance and maintains the voltage by the capacity of the output Q. Due to the dynamic circuit, there is an upper limit to the period during which the output can be maintained in the latched state. However, there is no problem unless the cycle time of the internal clock CKt and CKb is particularly long. Compared to the latch circuit in Fig. 9, the number of elements is half, and the layout area can be reduced. In addition, since the internal clock pair CKt and CKb forces are each input to only one transistor, the load capacity of the internal clock pair CKt and CKb is small, distribution at high frequencies is easy, and power consumption is small.
  • FIG. 13 shows still another configuration example of the latch circuit, which is characterized in that positive feedback is applied even in a transparent state.
  • an inverter INV3 is provided instead of the second tri-state inverter of the latch circuit shown in FIG.
  • the driving capability of the MOS transistor constituting this inverter is set small by reducing the gate width and, in some cases, increasing the gate length.
  • this latch circuit is switched from the transparent state to the latch state at the rising edge of the input D at the rising edge of the internal clock CKt of the input.
  • the fall of D is determined by the fall of the internal clock CKb of the bar.
  • the positive feedback of the inverters INV5 and INV3 works, and the output Q is driven by the drive capability of the tristate inverter exceeding the inverter INV3.
  • the output is in a floating state due to the time difference between the rise of the internal clock CKt of the tower 1 and the rise of the internal clock CKb of the bar.
  • the internal clock pair CKt and CKb are only input to each transistor, so the load capacitance of the internal clock pair CKt and CKb is small and high frequency. Distribution is easy and power consumption is small.
  • FIG. 14 shows a configuration example of a master-slave type flip-flop circuit suitable in that case.
  • the master has the same configuration as the latch circuit shown in FIG. 9, and includes two inverters INV0 and INV5, a first three-state inverter including PMOS transistors MP1 and MP2 and NMOS transistors MN1 and MN2, PMO transistors MP3, MP4 and NMO It consists of a second tri-state inverter consisting of an S transistor image 3 and MN4.
  • the input D is transmitted to the intermediate node Nt by two stages of the inverter INV0 and the first tristate inverter.
  • the slave (SLA) includes a third tri-state inverter including PMOS transistors MP6 and MP7 and NMOS transistors MN6 and MN7, a fourth tri-state inverter including PMOS transistors MP8 and MP9 and NM S transistors MN8 and MN9, It consists of inverter INV10.
  • the connection of the internal clock pair CKt and CKb is the reverse of the third tri-state inverter with the first tri-state inverter, and the reverse of the fourth tri-state inverter with the second tri-state inverter .
  • the signal at the intermediate node Nt is transmitted to the output Q via two stages, the third 3-state inverter and the inverter INV10.
  • the operation of the flip-flop circuit of FIG. 14 will be described with reference to FIG.
  • the case is shown where the delay time of the fall is longer than the rise of the mouth, and there is an overlap period in which both the internal clock CKt of the tower and the internal clock CKb of the bar are at a high level.
  • the master enters the transparent state (TRA) while the true internal clock CKt is low and the bar internal clock CKb is high, and the true internal clock CKt is high and the bar internal clock CKb is high. Is in the latch state (LAT).
  • the overlap period in which the internal clock pair CKt and CKb are both high depends on the input Q, and is in a latching state on the rising edge and in a transparent state on the falling edge.
  • the slave since the connection relationship between the internal clock pair CKt and CKb is opposite to that of the master, the slave enters the latch state while the internal clock CKt of the first clock is at the low level and the internal clock CKb of the bar is at the high level.
  • the internal clock CKt is high and the internal clock CKb of the bar is The period is in a transparent state. In the overlap period in which the internal clock pair CKt and CKb are both at high level, it depends on the signal of the intermediate node Nt, and is in the transparent state for the rising edge and the latched state for the falling edge.
  • this flip-flop circuit captures the input D at the rising edge of the internal clock CKt at the rising edge of the clock, and captures the falling edge at the falling edge of the internal clock CKb of the bar at the rising edge.
  • the output Q is held from the late falling edge of CKb to the early falling edge of the next cycle.
  • the delay time of the rise is larger than the fall of the clock, and there is an overlap period in which both the internal clock CKt of the clock and the internal clock CKb of the bar are at the high level. Operates similarly. That is, the period during which the output Q is in the valid state (VAL) is the period obtained by subtracting the overlap period between the internal clock pair CKt and CKb from the cycle time between the internal clock pair CKt and CKb. Compared with the latch circuits in Figs. 9, 12, and 13, the validity period of the output Q is longer and it is easier to match the timing with the internal circuit.
  • FIG. 16 shows another configuration example of the flip-flop circuit suitable for the input unit according to the present invention.
  • the feature is that it takes the logic of the internal clock pair CKt and CKb and generates the slave control clock pair CKSt CKSb.
  • the master (MAS) is composed of three inverters INV0, INV5, INV11, a first transistor inverter composed of PMOS transistors MP1, MP2 and NM ⁇ S transistors MN1, MN2, and PMO transistors MP3, MP4, and NMOS It consists of a second tri-state inverter consisting of transistors MN3 and N4.
  • the slave (SLA) has a third tri-state inverter composed of PMOS transistors MP6, MP7 and NM ⁇ S transistors MN6 and MN7, and PMOS transistors MP8, MP9 and NMOS. It consists of a fourth tri-state inverter consisting of transistors MN8 and MN9, and inverter # 0.
  • the third and fourth tri-state inverters are controlled not by the internal clock pair CKt and CKb but by the slave control clock pair CKSt and CKSb.
  • the slave control clock pair CKSt and CKSb is generated by taking the logic of the internal clock pair CKt and CKb by two inverters INV12 and V13, NAND gate NA14 and NOR gate N014. It should be noted that the slave control clock generation logic circuit can be shared by a plurality of flip-flop circuits instead of being provided for each flip-flop circuit, thereby reducing the number of elements and the layout area. Can be reduced.
  • the flip-flop circuit of FIG. 16 will be described with reference to FIG.
  • FIG. 15 there is shown a case where there is an overlap period in which both the internal clock CKt of the tower and the internal clock CKb of the bar are at the high level.
  • the master operates between the transparent state (TRA) and the latch state (LAT) during the overlap period in which the internal clock pair CKt and CKb are both at high level.
  • the rising state is a latching state
  • the falling state is a transparent state.
  • the slave is in the latch state while the true slave control clock CKSt is at the high level and the bar slave control clock CKSb is at the high level.
  • the true slave control clock CKt is at the high level and the bar slave control is performed. While the clock for use CKSb is at low level, it is in the transparent state.
  • the clock for slave control is Only when the internal clock CKt of the clock is high and the internal clock CKb of the bar is low, the CKSt of the clock is high and the CKSb of the bar is low. During the other periods, the true CKSt is low and the no CKSb is high.
  • the slave control clock pair CKSt, CKSb switches at the same timing and does not overlap. As a result, the slave is in the transparent state only when the master is in the latch state, and is in the latch state in other periods.
  • the output Q is held from the slowest rising of the internal clock CKt and the slowing of the internal clock CKb of the bar to the slower in the next cycle.
  • the period during which the output Q is in the valid state (VAL) is the cycle time of the internal clocks CKt and CKb.
  • FIG. 18 schematically shows another example of the configuration of the input unit according to the present invention. It is characterized by the use of a clock recovery circuit PLL to generate internal cracks CKRt and CKRb.
  • input buffers IBUF are provided corresponding to the input signals IN0, INI,... And the external clock pair CLKt, CLKb, respectively, and the internal signals ⁇ , IN1 I are compared with the reference voltage Vref. , ... and the internal clock pair signals CLKIt, CLKIb.
  • the latch circuit LP are input to the latch circuit LP, and the output signals IN0L, IN1L, ... are used for the operation of the internal circuit of the semiconductor device.
  • the operation of the latch circuit is controlled by internal clock pairs CKRt and CKRb generated by two phase-locked loop PLLs that are clock recovery circuits.
  • the phase-locked loop PLL compares the internal clock signal CLKIt or CLKIb with the internal clock CKRt or CKRb.
  • Phase-frequency comparator PFD phase-frequency detector Charge pump that generates control voltage Vet or Vcb according to the output of PFD It consists of a circuit CP, a voltage controlled oscillator VC0 controlled by the control voltage Vet or Vcb, and a clock driver CKD that drives the output of the voltage controlled oscillator VCO as an internal clock CKRt or CKRb.
  • the clock driver CKD can be realized by a well-known cascode driver or the like in which even-numbered stages of CMOS inverters are connected to gradually increase the driving capability.
  • the main parts of the other circuit blocks will be briefly described.
  • FIG. 19 is a circuit diagram of a configuration example of the phase ′ frequency detector PFD. It consists of eight inverters INV00 to INV07, six two-input NAND gates NA100 to NA105, two three-input NAND gates NA106, NA107, and a four-input NAND gate NA108, and is composed of a combination of CM ⁇ S logic gates. . Control signals UP1 and DN1 are generated according to the phase and frequency of the internal clock signal CLKI and internal clock CKR.
  • FIG. 20 is a circuit diagram of a configuration example of the charge pump circuit CP.
  • Inverter INV108, two PM ⁇ S transistors MN100, MP101, and two NM It consists of OS transistors MN100 and N101, two capacitors C100 and C101, and a resistor R100.
  • the bias voltages Vbpl and Vbnl are applied to the gates of the PMOS transistor MP100 and the NMOS transistor MN100, respectively, and the current flowing from the power supply voltage VCC to the control voltage Vc node or the current drawn to VSS is limited.
  • FIG. 21 shows a configuration example of the voltage control transmitter VC0. It consists of six fully differential delay circuits DDE0 to DDE5 and two inverters INV116 and INV117. Fully differential delay circuit DDE0 ⁇ ! ) DE5 is a delay circuit whose input and output are both differential signals and whose delay time is controlled by the control voltage Vc.
  • the number is six, but an appropriate number is set so as to obtain a desired variable frequency region. Note that although the number is 6 and an even number here, oscillation occurs because the DDE5 true output is returned to the DDE0 bar input, and the DDE5 bar output is returned to the DDE0 toul input.
  • the inverter INV116 is provided for taking out the internal clock CKR as an output. Further, an inverter INV117 is provided to equalize the load of the output of the fully differential delay circuit DDE5.
  • the rising edge of the input signal can be determined at the timing corresponding to the rising edge of the external clock, and the falling edge of the input signal can be determined at the timing corresponding to the falling edge of the external clock.
  • the input signal path and the clock signal path are aligned, they are compensated, and the setup and hold times are reduced to reduce the clock cycle. You can save time.
  • a method that enables a high-speed interface using a clock recovery circuit for generating an internal clock is described in Reference 3.
  • a higher-speed operation can be performed by compensating for the delay time difference between the rising edge and the falling edge.
  • FIG. 22 schematically shows still another example of the configuration of the input unit according to the present invention.
  • the feature is that the mouth regeneration circuit used to generate internal cracks CKRt and CKRb is partially shared.
  • the internal clock CKRb of the bar is generated by the delay locked loop DLL.
  • the delay lock loop DLL is a phase comparator PC that compares the internal clock signal CLKIb and the internal clock CKRb, a charge pump circuit CP that generates the control voltage Vc2 according to the output of the phase comparator PC, and a control. It includes a voltage-controlled delay VCD controlled by the voltage Vc, and a clock driver CKD that drives the output of the voltage-controlled delay VCD as an internal clock CKRb.
  • Toru's internal clock CKRt is obtained by delaying the internal clock signal CLKIt with the voltage control delay VCD controlled by the control voltage Vc2 of the delay lock loop DLL and driving it with the clock driver CKD. appear.
  • the internal clock CKRt of the Tonore is delay locked.
  • the internal clock CKRb of the bar generated by the loop DLL can be generated only by the voltage control delay unit VCD and the clock driver CKD.
  • the configuration of the phase comparator PC and the voltage control delay VCD which are circuit blocks different from the configuration shown in FIG. 18, will be briefly described.
  • FIG. 23 is a circuit diagram of a configuration example of the phase comparator PC. It consists of four 3-input NAD gates NA140 to NA143 and four inverters INV140 to: [NV143. While the enable signal LEN0 is at the high level, control signals UP0 and DNO are generated according to the phases of the internal clock signal CLKI and the internal clock CKR. Unlike phase-locked loops, delay-locked loops do not need to detect frequency differences, so a phase comparator with a simpler configuration than the phase-frequency detector PFD shown in Figure 19 is used. be able to.
  • FIG. 24 shows a configuration example of the voltage control delay device. It consists of five inverter type delay circuits IDE0 to IDE4 and an inverter INV116.
  • the inverter type delay circuits IDE0 to IDE4 are inverters whose delay time is controlled by the control voltage Vc.
  • the number is five, but an appropriate number is set so as to obtain a desired variable frequency region.
  • the phase should not be inverted, including the inverter INV116 that extracts the output.
  • the configuration shown in FIG. 22 has a smaller number of circuit blocks than the configuration shown in FIG. 18, and each circuit block has a simple configuration and can compensate for a delay time caused by a clock driver CKD or the like.
  • the clock recovery circuit uses a delay-locked loop instead of a phase-locked loop.
  • the voltage-controlled oscillator used in the phase-locked loop has the same output oscillation frequency when the control voltage is the same, but the phase is different.Therefore, in Figure 18, loops are provided for each of the true and bar internal clocks. .
  • the power used in the delay lock The pressure control delay can share the same delay time when the control voltage is the same, so that a part of the loop can be shared between the tower and the internal connection of the bar.
  • FIG. 25 is a circuit diagram of a configuration example of an input buffer using a current mirror type differential amplifier.
  • the three NMOS transistors MN200 to MN202 and the two PMOS transistors MP201 and MP202 form an NMOS input current mirror differential amplifier, and differentially amplify the input signal IN with respect to the reference voltage Vref.
  • the sources of the PMOS transistors MP201 and MP202 are connected to the input / output power supply voltage VDDQ.
  • the output of the differential amplifier is received by the 2-input NAND gate NA203, and the internal signal INI is output.
  • the power down signal PTOIb of the bar is input to the NAND gate NA203 and the NMO transistor MN200. When the power down of PTOIb is low, the current of the differential amplifier is cut off and the internal signal INI is fixed.
  • the input buffer IBUF is generally used in a small-width interface such as an STLS interface.
  • a small-width interface such as an STLS interface.
  • FIG. 26 is a circuit diagram of another configuration example of the input buffer. It features a complementary differential amplifier that combines an NMOS input differential amplifier and a PMOS input differential amplifier. Such an input buffer is described in Ref.
  • the NMOS input differential amplifier DAN includes three NM ⁇ S transistors MN210 to MN212 and three PMO transistors MP210 to MP212.
  • the PMOS input differential amplifier DAP is also composed of three NMOS transistors MN213 to MN215 and three PMOS transistors MP213 to MP215.
  • the output of the NMO S input differential amplifier DAN and PMO S input differential amplifier DAP is short-circuited, and the input signal IN is referenced to the reference voltage Vref Is differentially amplified.
  • the output INI0 of the differential amplifier is provided with a PMOS transistor MP210, which is connected to the input / output ground voltage VSSQ in the NMOS input differential amplifier DAN and the PMOS input differential amplifier MP.
  • the power down signal PTOIb of the bar is input to the gate, and during power down, the current of the differential amplifier is cut off and its output is fixed.
  • the MPMOS transistor in the NMOS input differential amplifier DAN MP210 is provided to balance the NMOS transistor MN213 in the PMOS input differential amplifier DAP.
  • the output of the differential amplifier is composed of a PMOS transistor MP217 and an NMOS transistor MN217.An inverter driven by the input / output power supply voltage VDDQ and the input / output ground voltage VSSQ is connected to the output, and the inverter INV218 is connected to the output. Drive the internal signal INI.
  • the differential amplifier with the NMOS input and the differential amplifier with the PMOS input operate at the same time, and the influence of the common-mode component of the input is small, and the delay time difference between the rise and fall can be reduced.
  • the input unit according to the present invention as shown in FIG. 1 the time difference between the clock and the bar of the internal clock pair is reduced, and stable operation is facilitated.
  • FIG. 27 shows another example of the configuration of the input buffer. Similar to the input buffer shown in FIG. 26, the feature is that the NMOS input differential amplifier and the PMOS input differential amplifier are combined and operated alternately. Such an input buffer is also described in Ref.
  • the NMO S input differential amplifier MN and the PMO S input differential amplifier DAP are composed of three NM ⁇ S transistors and three PMO S transistors, as shown in Fig. 26, and the input signal IN is referenced to the reference voltage Vref. Is differentially amplified.
  • a PMOS transistor MP210 for controlling power down, an inverter composed of a PMOS transistor MP217 and an NMO transistor MN217, and an inverter Data is provided.
  • feedback is applied from the input node INIOb of the inverter layer 212 to the gates of the NMO transistor MN21Q in the NMO S input differential amplifier DAN and the PM0S transistor MP213 in the PM ⁇ S input differential amplifier DAP.
  • the node INIOb is at the high level, the current path of the PMOS input differential amplifier DAP is cut off, and when the node INIOb is at the high level, the current path of the NMOS input differential amplifier DAN is cut off.
  • the smaller of the through current is automatically selected from the NMOS input differential amplifier DAN and PMOS input differential amplifier DAP, and they operate alternately.
  • the power down signal PTOIb of the bar is connected to the PM ⁇ S transistor MP210 and the NMOS transistor ⁇ 213 in the PMOS input differential amplifier DAP, and is not input to the NMOS input differential amplifier DAN.
  • This input buffer is capable of differential amplification with the reference signal Vref with relatively small current consumption.
  • the amplitude of the input signal IN is such that the high level is close to the input / output power supply voltage VDDQ and the low level is close to the input / output ground voltage VSSQ, the through current in the differential amplifier is small. Compared with the input buffer as shown in FIG.
  • FIG. 28 is a circuit diagram of still another input buffer configuration example.
  • the two NMOS transistors MN220 and MN221 and the two PMOS transistors MP220 and MP221 form a NOR gate powered by the input / output power supply voltage VDDQ and the input / output ground voltage VSSQ.
  • Down signal PTOI is input.
  • the inverter INV222 is connected to the output of this NOR gate and drives the internal signal INI.
  • this input buffer is commonly used for large amplitude interfaces such as LVTTL. Since the judgment is made based on the logic threshold of the logic gate without using the reference voltage Vref, the effect of the process and voltage fluctuation is large, and the delay time difference between the rise and fall is large. Therefore, the effect of the present invention that can compensate for the delay time difference is great.
  • FIG. 29 schematically shows an output section of the semiconductor device according to the present invention.
  • Output buffers 0BUF are provided corresponding to the output signals 0UT0, 0UT1, ... and the external clock pair CLK0t, CLKOb ', respectively, and are controlled by the enable signals Q0E, CK0E by the output control circuit 0C.
  • the internal signals 0UT0P, 0UT1P, ... are input to the flip-flop circuit FF0, controlled by the internal clock CK0, and the outputs 0UT0Q, 0UT1Q, ... are input to the output buffer 0BUF.
  • the output timing generator 0TG and complementary clock pair signals CLKPt and CLKPb are output together with the internal clock CK0.
  • FIG. 30 is a circuit diagram of a configuration example of the output buffer 0BUF. It consists of an inverter INV230, NAND gate NA231, NOR gate N0231, two level conversion circuits LC23P and LC23N, and an output stage PMOS transistor MP233 and NMOS transistor MN233.
  • each of the level conversion circuits LC23P and LC23N is composed of three PMOS transistors and three NMOS transistors, and converts the signal amplitude from the internal circuit power supply voltage VDD to the input / output power supply voltage VDDQ.
  • This output buffer 0BUF is enabled by the enable signal Q0E. It becomes high impedance state at the time of lip leakage vss. When the enable signal Q0E is at the high level VDD, it drives the output OUT according to the internal signal 0UTQ.
  • FIG. 31 shows an interface according to the present invention between two semiconductor integrated circuits CHPL and CHPR.
  • a reference clock CK0 as an operation reference is sent to the semiconductor integrated circuits CHPL and CHPR.
  • the clock pair CKLt and CKLb are sent together with data DATAL from the semiconductor integrated circuit CHPL to CHPR.
  • the clock pair CKRt and CKRb are sent together with the data DATAR from the semiconductor integrated circuit CHPL to CHPR.
  • Such a configuration is suitable, for example, for an interface between the CPU and the cache memory.
  • FIG. 32 schematically shows the signal transmission unit in FIG.
  • Each of the semiconductor integrated circuits CHPL and CHPR has an output buffer 0BUF and an input buffer IBUF.
  • the output buffer 0BUF is connected to one end of the transmission line TL via the terminating resistor RPL or RPR.
  • the other end of the transmission line is connected to the input buffer IBUF of the other semiconductor integrated circuit.
  • the so-called transmission termination in which a terminating resistor is provided in series, is suitable for a point-to-point interface as shown in FIG. 31 because a through current does not flow when the signal does not change.
  • the reference voltage Vref is not shown here, it is input to the semiconductor integrated circuits CHPL and CHPR if necessary according to the specifications of the interface voltage level.
  • FIG. 33 shows an example in which the present invention is applied to a memory system.
  • the memory controller MCTL and the n memories MCHPl to MCHPn are connected by a clock pair CLKt, CLKb, a command bus CMD, an address bus ADD, a data bus DQL, and a data strobe pair DQSt, DQSb.
  • the clock pair CLKt, CLKb, the command bus CMD and the address bus ADD are driven by the memory controller MCTL and sent to the memories MCHPl to MCHPn.
  • the data bus DQL and the data strobe pair DQSt and DQSb are bidirectional, and are sent from the memory controller to the memory during a write operation and from the memory controller to the memory controller during a read operation.
  • both can realize an interface at a high frequency. If the frequency of either the one-way bus or the two-way bus can be low, the number of transmission lines can be reduced without pairing the signals that determine that timing.
  • FIG. 34 schematically shows the signal transmission unit in FIG. For simplicity, only one unidirectional signal and one bidirectional signal are shown here.
  • the output 0UTC of the output buffer 0BUF in the memory controller MCTL is completed via the transmission line TL.
  • the input buffer IBL1F in the memories MCHPl to MCHPn is input. 1 ⁇ 1 ⁇ 1 ⁇ 1].
  • I0C which is the output of the output buffer 0BUF in the controller MCTL and the input of the input buffer IBUF
  • IOMn is the input of the input buffer IBUF and the output of the output buffer 0BUF in the memories MCHPl to MCHPn via the transmission line TL.
  • termination resistors RTL and RTR are provided at both ends of the transmission line, and are connected to the termination voltage VTT.
  • the signal transmission timing varies depending on the position on the node, but as shown in Fig. 33, the delay time is made uniform by sending the timing signal pair from the same semiconductor integrated circuit together with the signal sent to the bus. be able to. Even if the input impedance of the memories MCHPl to MCHPn differs depending on the presence or absence of the output buffer 0BUF between the one-way bus and the two-way bus, the effects can be eliminated by providing a timing signal pair for each of the memories MCHPl to MCHPn.
  • FIG. 35 shows a main block diagram of a synchronous DRAM which can be used as the semiconductor memories MCHPl to MCHPn in FIG.
  • Indirect peripheral circuits include clock buffer CKB, control signal buffer CB, command decoder CD, end address buffer AB, column address counter YCT, data strobe input circuit DSB, data strobe output circuit QSB, data input circuit DIB, data output circuit Including DOB.
  • a row defect repair circuit XR, a row predecoder XPD, a column repair decision circuit YR, a column predecoder YPD, a write buffer TO, a main amplifier MA, etc. are provided corresponding to the memory array MAR, and a memory core sector is provided.
  • SCT0, SCT1, ... are configured.
  • the memory core sector corresponds to the number of memory arrays according to the specifications such as the memory capacity and the number of banks, but here only two are shown for simplicity.
  • the clock buffer CKB distributes the internal clock pair CKIt, CKIb to the control signal buffer CB, address buffer AB, etc. according to the external clock pair CLKt, CLKb. command
  • the decoder CD generates a control signal for controlling the address buffer AB, the column address counter YCT, the data input circuit DIB, the data output circuit DOB, etc. in response to an external control signal CMD.
  • the address buffer AB fetches an external address ADR at a desired timing according to the external clock CLK, and distributes the low address BX to the sectors SCT0 and SCT1.
  • the address buffer AB also takes in the column address and sends it to the column address counter YCT, and the column address counter YCT generates a column address BY for performing a burst operation using the input column address as an initial value, Distribute to sectors SCTO and SCT1.
  • the data strobe data input circuit DSB generates an internal data strobe pair DSIt, DSIb and the like in accordance with the data strobe pair DQSt, DQSb, and controls the data input circuit DIB.
  • the data input circuit DIB takes in the data of the input / output data DQ with the outside at a desired timing and outputs the write data GI.
  • the data output circuit DOB outputs the read data GO to the input / output data DQ at a desired timing.
  • the data strobe output circuit drives the QSB force data strobe pair DQSt and DQSb.
  • the oral defect repair circuit XR determines the presence / absence of replacement for the row address BX, and outputs the row repair determination result RXH to the row predecoder XPD.
  • the row predecoder XPD receives the row address BX and the row-related rescue judgment result RXH, and outputs a desired mat selection signal MS and a port predecode address CX to the memory array MAR.
  • the column-based repair determination circuit YR determines the presence / absence of replacement for the address BX and the column address BY, and outputs a column-based repair determination result RYH to the column predecoder YPD.
  • the column predecoder YPD receives the column address BY and the column-based rescue judgment result RYH, pre-decodes the column address BY, and outputs the column predecode address CY to the memory array MAR. I do.
  • the write buffer WB outputs the write data GI to the main input / output line MI0.
  • the main amplifier MA amplifies the signal of the main input / output line MI0 and outputs read data GO.
  • FIG. 36 shows a configuration example of the memory array MAR in FIG.
  • a memory cell array in which memory cells are arranged in a matrix form is divided into 16 mats MCA0 to MCA15.
  • Sense amplifier sections SAB0 to SAB16 are provided on both sides of each mat.
  • decoders XDEC0 to XDEC15 corresponding to the mats MCA0 to MCA15 and sense amplifier control circuits SAC0 to SAC16 corresponding to the sense amplifiers SAB0 to SAB16.
  • the column decoder YDEC and the redundant column driver RYD2 are common to the divided mats MCA0 to MCA7, and the 256 column select lines YS0 to YS255 and the two redundant column select lines RYS0 and RYS1 are selectively used. Drive. Needless to say, the present invention is not limited to the number of mats and the number of column selection lines.
  • FIG. 37 shows a configuration example of the sense amplifier section SAB1 and the mat MCA1 in FIG.
  • the mat MCA1 is a well-known folded bit in which a memory cell MC is arranged at the intersection of the bit line pair 'BLOt and BL0b, or one of BLOt and BL0b,..., And the word lines WL0, WL1,. Line configuration.
  • the memory cell MC is a one-transistor, one-capacitor memory cell including one NMOS transistor and one storage capacitor.
  • the sense amplifier section SAB1 is shared by the two mats MCA0 and MCA1, and the shared gates SHL0, SHL1,... and SHR0, SHR1, ' ⁇ ', precharge circuits PCO, PC1, ⁇ ' SA0, SA1, ..., input / output gates; [0G0, I0G1, ...].
  • the precharge circuits PC0, PCI, ... precharge the bit line pairs in the mats MCAO, MCA1 on both sides to the precharge voltage HVC.
  • Shared gates SHL0, SHL1,... and SHR0, SHR1,... are either mat MCAO, MCA1
  • the bit line pair in one is connected to the sense amplifier, and the bit line pair in the other is separated.
  • a signal is read from the memory cell MC to each bit line pair BLOt and BL0b, BLOt and BLOb,.... , And amplified by the sense amplifiers SA0, SA1,.
  • the I / O gates IOG0, I0G1, ... are selected by column selection lines YS0, YS1, ..., and connect the desired sense amplifier to the I / O line pairs IOOt and I00b, IOlt and IOlb.
  • column selection lines are arranged for every two sense amplifiers in the sense amplifier section, that is, for every four pairs of bit lines in the mat.
  • FIG. 38 shows an example of the timing of the read operation in the configuration example of the synchronous DRAM shown in FIG.
  • the command decoder CD determines the control signal CMD, and when the activating command A is given, the low address X is taken from the address ADR into the address buffer AB. Outputs the lower address BX.
  • a desired mat selection signal MS and a port predecode address CX are output in the sector SCT0 or SCT1.
  • the word line WL is selected in the memory array MAR, and the sense amplifier operates.
  • the column address Y is fetched from the address ADR into the address buffer AB, the column address counter YCT operates every clock cycle, and the column address BY is read. Output.
  • the column-based rescue judging circuit YR operates, and outputs a column predecoded address CY or a redundant column address signal RCY according to the result.
  • the column selection line YS or the redundant column selection line RYS is selected in the memory array MAR.
  • a signal is read to the main input / output line MI0, and the main amplifier MA reads the data.
  • the data output circuit DOB outputs data to the input / output data DQ at the timing according to the external clock pair CLi and CLKb.
  • the data strobe output circuit QSB drives the data strobe pair DQSt and DQSb.
  • the data strobe pair DQSt and DQSb are used on the memory controller side to control the input / output data DQ capture timing.
  • the switching timing of the input / output data DQ is determined by the rising edge of the external clock CLKt and the falling edge of CLKb, while the data strobe pair DQSt and DQSb can be switched by the falling edge of the external clock CLKt and the rising edge of CLKb.
  • Figure 39 shows an example of the write operation timing.
  • the row operation is performed.
  • a write command W is given to the control signal CMD, a column operation is performed.
  • the column address Y is fetched from the address ADR into the address buffer AB.
  • the input / output data DQ is taken in by the data input circuit DIB at the rise of the data strobe DQSt and the fall of DQSb.
  • the data input circuit DIB outputs write data GI at the next rising edge of the external clock CLKt and falling edge of CLKb, and a signal is sent from the write buffer to the main input / output line MI0.
  • the column address counter YCT operates every clock cycle, outputs the column address BY, outputs the column predecode address CY or the redundant column address signal RCY, and selects the column selection line YS or the redundant column selection line RYS. You. As a result, the signal on the main input / output line MI0 is sent to the sense amplifier, and the write operation is performed.
  • FIG. 40 shows a configuration example of the data strobe input circuit DSB. Consists of two input buffers DStB, DSbB, three inverters INV300, INV308, INV309, NOR gate N0301, two inverter-type delay circuits IDE302, IDE303, and four NAND gates NA304 to NA307 Is performed.
  • the input buffers DStB and DSbB compare the data strobe pair DQSt and DQSb with the reference voltage Vref and output the internal data strobe pair DSIt and DSIb.
  • the inverter INV300 and the NOR gate N0301 set the internal node DS0 to low level during the period of the data strobe DQSt power S noise level of the transistor, and to the high level during the other period of the DQSb power level of the bar.
  • NAND gates NA306 and NA307 constitute an SR latch. For example, at the rising edge of the internal clock CKDI supplied by the command decoder CD in FIG.
  • the reset signal Rb of the bar of the SR latch is set to the low level by the desired pulse width determined by the delay circuit IDE302.
  • the set signal Sb of the bar of the SR latch is set to a low level for a desired pulse width determined by the delay circuit IDE303.
  • Inverter 2-stage INV308 and INV309 amplify the output of SR latch and output as timing control signal DSCK.
  • FIG. 41 shows a configuration example of one bit of the data input circuit DIB.
  • the circuit of Fig. 41 is provided for the number of bits to configure the data input circuit DIB.
  • One bit consists of an input buffer DIB and first to third latch circuits L301 to L303.
  • the input buffer DIB compares the input DQi with the reference voltage Vref and outputs an internal signal DOi.
  • the first latch circuit L301 has the same configuration as that of FIG. 9, and is controlled by the internal data slope pair DSIt and DSIb.
  • the second latch circuit L302 is a normal latch circuit, comprising two inverters INVOC, INV5C, four PMOS transistors MP1C to MP4C, and four NMOS transistors MN1C to MN4C, It is controlled by the timing control signal DSCK.
  • the third latch circuit L303 is also a normal latch circuit, can be configured in the same manner as the second latch circuit L302, and is controlled by the internal clock CKDI.
  • the operation of the data strobe input circuit DSB shown in FIG. 40 and the operation of the data input circuit DIB partially shown in FIG. 41 will be described with reference to the timing chart shown in FIG.
  • a case is shown in which the delay time of the fall is longer than the rise of the data strobe, and there is an overlap period in which both the true internal data strobe DSIt and the bar internal data strobe DSIb are at a high level.
  • the first latch circuit L301 in Fig. 41 is in the transparent state (TRA) while the internal data strobe DS It is low and the internal data strobe DSIb of the bar is at the high level.
  • the timing control signal DSCK for controlling the second latch circuit L302 is generated by the data strobe input circuit DSB shown in FIG. 40 as follows. The lower of the true internal data strobe DSIt rising and the internal data strobe DSIb falling of the bar, the slower of the falling of the internal data strobe DSIb in Fig. 42, the low level pulse is generated in the bar set signal Sb and the timing The control signal DSCK rises.
  • the timing control signal DSCK falls.
  • the second latch circuit L302 enters a latch state when the DSCK is at a high level and a transparent state when the DSCK is at a low level.
  • the third latch circuit L303 is controlled by the internal clock CKDI. Becomes transparent at the time of the bell. As a result, the internal signal Di output from the third latch circuit L303 becomes a valid state (VAL) in a cycle time corresponding to the fall of the internal clock CKDI.
  • a latch circuit controlled by a timing control signal generated by the logic of the internal data strobe and the internal clock is inserted between the latch circuit controlled by the internal data strobe pair and the latch circuit controlled by the internal clock.
  • This allows flexibility in the timing relationship between the data strobe pair and the clock.
  • it is difficult to match transmission lines s, which enables stable operation even if a delay time difference occurs .
  • the output DOi of the input buffer end DIB is captured by the first latch circuit L301 having the same configuration as in Fig. 9, so that the input DQi rises at the rise of the data strobe and the input DQi rises. The fall can be determined by the fall of the data strobe, and a high frequency interface is possible.
  • FIGS. 38 and 39 show the operation at the same clock and data frequencies, that is, at the so-called single data rate.
  • the present invention is applicable not only to single data rates but also to double data rate synchronous memories.
  • FIG. 43 shows an example of the timing of the read operation at the double data rate in the configuration example of the synchronous DRAM shown in FIG. Similarly to Fig. 38, row operation is performed when Activate command A is given. When a read command R is given to the control signal CMD, a column operation is performed in each clock cycle. At this time, read data is output from the mat to the data output circuit DOB with twice as many bits as the input / output data DQ. The so-called 2-bit prefetch 'operation is performed.
  • the data output circuit DOB is connected to the external clock and the timing according to CLKt and CLKb. Data to the input / output data DQ. Here, the input / output data DQ is switched at the intersection of the external clock pair CLKt and CLKb. Although not shown in FIG. 35, this can be realized by using a quick recovery circuit for controlling the output timing. By switching between the rising edge of the external clock CLKt and the falling edge of CLKb, as well as the falling edge of the external clock CLKt and the rising edge of CLKb, the data frequency is twice that of the external clock pair CLKt and CLKb.
  • the data strobe output circuit QSB drives the data strobe pair DQSt and DQSb according to the input / output data DQ.
  • the data strobe pair DQSt and DQSb are driven one cycle before the drive of the first data of the input / output data DQ.
  • the data strobe pair DQSt and DQSb are used on the memory controller side to control the input / output data DQ capture timing.
  • FIG. 44 shows an example of the timing of the write operation at the double data rate.
  • activate command A When activate command A is given, row-related operations are performed.
  • a write command W is given to the control signal CMD, a column operation is performed.
  • the column address Y is fetched from the address ADR into the address buffer AB.
  • the data input circuit DIB takes in the input / output data DQ by the rising edge of the data strobe DQSt and the falling edge of DQSb.
  • the input / output data DQ is taken in by the data input circuit DIB even at the falling edge of the data strobe DQSt and the rising edge of DQSb.
  • the data input circuit DIB outputs the write data GI of twice the number of bits of the input / output data DQ, and the write buffer WB outputs the main input / output lines.
  • a signal is sent to MI0.
  • the column address counter YCT operates at each clock cycle, outputs the column address BY, and outputs the column predecode address.
  • CY or redundant column address signal KCY is output, and column select line YS or redundant column select line RYS is selected.
  • the signal on the main input / output line MI0 is sent to the sense amplifier, and the write operation is performed.
  • a so-called 2-bit prefetch operation is performed.
  • the data rate can be doubled at the same clock frequency as the single data rate.
  • the interface of the present invention is preferable because the setup time and the hold time specification of the input / output data can be shortened.
  • FIG. 45 shows a configuration example of the data strobe input circuit DSB. It consists of two input buffers DStB, DSbB, three inverters INV310, INV308, INV309, NOR gate N0301, two inverter type delay circuits IDE302, IDE303, and four NAND gates NA304 to NA307. You. The difference from the configuration in FIG. 40 is that the inverter INV300 in FIG. 40 is removed and the inverter INV310 is inserted.
  • the inverter INV310 and the NOR gate N0301 set the internal node DSB0 to the high level during the period when the data strobe DQSt of the Tonore is at the high level and the DQSb of the bar is at the high level, and at the high level during the other periods.
  • the set signal Sb of the bar of the SR latch is set to low level.
  • the two-stage inverter INV308 and INV309 amplify the output of the SR latch and output it as a timing control signal DSBCK.
  • Fig. 46 shows a configuration example of one bit of the data input circuit DIB. If the input / output data DQ is multi-bit, the circuit of Fig. 41 is provided for the number of bits and the data input circuit DIB is Constitute. One bit consists of the input buffer DIB, the first flip-flop circuit FF301e, and the first to fifth latch circuits.
  • the circuit FF301e has the same configuration as that in Fig. 14, and is controlled by the internal data strobe pair DSIt and DSIb.
  • the first latch circuit L301o has the same configuration as that of FIG. 9 as the first latch circuit L301 in FIG. 41, and is controlled by the internal data strobe pair DSIt and DSIb, but the first latch circuit L301o in FIG. The connection of the internal data strobe pair DSIt and DSIb to the circuit L301 is reversed.
  • the second to fifth latch circuits L302o, L303o, L302e, and L303e are ordinary latch circuits, and can be configured in the same manner as the second latch circuit L302 in FIG.
  • the second latch circuit L302o and the fourth latch circuit L302e are controlled by the timing control signal DSBCK, and the third latch circuit L303o and the fifth latch circuit L303e are controlled by the internal clock CKDI.
  • the operation of the data strobe input circuit DSB shown in FIG. 45 and the operation of the data input circuit DIB partially shown in FIG. 46 will be described in accordance with the timing chart shown in FIG.
  • the falling delay time is longer than the rising edge of the data strobe, and both the internal data strobe DSIt and the internal data strobe DSIb of the bar become high level. This shows a case where there is an overlap period.
  • the first flip-flop circuit FF301e in FIG. 46 operates as described with reference to FIG. 15, and the true internal data strobe DSIt rises slowly and the internal data strobe DSIb falls slowly.
  • the transparent internal data strobe (TRA) during the period when the internal data strobe DSIt is high and the internal data strobe DSIb of the bar is low level, and the true internal data strobe
  • the latch state (LAT) is set.
  • the overlap period during which the internal data strobe pair DSIt and DSIb are both high depends on the input DOi.
  • the timing control signal DSBCK for controlling the second latch circuit L302o and the fourth latch circuit L302e is generated by the data strobe input circuit DSB shown in FIG.
  • the third latch circuit L303o and the fifth latch circuit L303e are controlled by an internal clock CKDI, and are in a latch state when CKDI is at a high level and in a transparent state when CKDI is at an open level. As a result, the internal signals Me and Dio output from the third latch circuit L303o and the fifth latch circuit L303e enter a valid state (VAL) in a cycle time corresponding to the falling edge of the internal clock CKDI. .
  • the timing of taking in both the double data rate is obtained.
  • the rising edge of the input DQi is the rising edge of the data strobe, and the falling edge of the input DQi is Can be determined by the falling edge of the data strobe.
  • double data rate interface can be stably realized.
  • the rising edge of the input signal is determined by the rising edge of the external clock
  • the falling edge of the input signal is determined by the rising edge of the external clock. It can be judged by going down. Even if there is a difference in the delay time between the rise and fall, it is compensated if the input signal path and the clock signal path are the same. As a result, the setup time and hold time specifications can be shortened, and the clock cycle time can be shortened. That is, an interface at a high frequency can be realized.
  • the present invention is suitable for general semiconductor devices that transmit and receive signals at a high frequency.
  • the present invention can be applied to a single data rate / double data rate synchronous DRAM.

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Abstract

La présente invention se rapporte à un dispositif semi-conducteur qui est capable de se comporter de manière stable au cours de courtes périodes d'établissement et de maintien même dans le cas où existe une différence de temps de retard entre les montées et les descentes du signal, et qui est capable d'accepter en entrée ou de délivrer en sortie des signaux à des fréquences élevées. Une unité de résolution représentative met en oeuvre un dispositif semi-conducteur comportant des tampons d'entrée (IBUF) correspondant respectivement à des signaux d'entrée (INO, IN1, ..., etc.) et des paires de signaux d'horloge externe entrés (CLKt, CLKb) de manière à produire des signaux internes (IN0I, IN1I, ..., etc.) et des paires de signaux d'horloge interne (CKIt, CKIb), ainsi que des circuits de verrouillage (LP) conçus pour recevoir les signaux internes (IN0I, IN1I, ..., etc.) de manière à commander leur fonctionnement au moyen des paires de signaux d'horloge interne (CKIt, CKIb) afin que leurs signaux de sortie (IN0L, IN1L, ..., etc) puissent être utilisés pour le fonctionnement des circuits internes. Il est ainsi possible de décider de la montée des signaux internes en fonction de la montée des signaux d'horloge externe et de la chute des signaux d'entrée en fonction de la chute des signaux d'horloge externe.
PCT/JP2001/004553 2001-05-30 2001-05-30 Dispositif semi-conducteur Ceased WO2002099810A1 (fr)

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JP2001195884A (ja) * 1999-11-05 2001-07-19 Mitsubishi Electric Corp 半導体装置
JP2008510387A (ja) * 2004-08-12 2008-04-03 マイクロン テクノロジー，インコーポレイテッド 高速入力サンプリングのための方法及び装置
JP2010518547A (ja) * 2007-02-16 2010-05-27 モスエイド テクノロジーズ インコーポレイテッド メモリシステムのクロックモード決定
WO2011021357A1 (fr) * 2009-08-17 2011-02-24 パナソニック株式会社 Circuit de réception de données
JP2019008859A (ja) * 2017-06-28 2019-01-17 東芝メモリ株式会社 半導体装置
CN109584917A (zh) * 2013-11-07 2019-04-05 瑞萨电子株式会社 半导体器件
JP2022066040A (ja) * 2020-10-16 2022-04-28 ローム株式会社 オシレータ回路
CN116469429A (zh) * 2023-03-31 2023-07-21 福建省晋华集成电路有限公司 用于半导体存储器的输入数据预对齐电路

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JP7385419B2 (ja) * 2019-10-15 2023-11-22 ルネサスエレクトロニクス株式会社 半導体装置

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JPH10322175A (ja) * 1997-05-16 1998-12-04 Fujitsu Ltd スキュー低減回路と半導体装置
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JP2001195884A (ja) * 1999-11-05 2001-07-19 Mitsubishi Electric Corp 半導体装置
JP2008510387A (ja) * 2004-08-12 2008-04-03 マイクロン テクノロジー，インコーポレイテッド 高速入力サンプリングのための方法及び装置
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JP2010518547A (ja) * 2007-02-16 2010-05-27 モスエイド テクノロジーズ インコーポレイテッド メモリシステムのクロックモード決定
US8432767B2 (en) 2007-02-16 2013-04-30 Mosaid Technologies Incorporated Clock mode determination in a memory system
US8644108B2 (en) 2007-02-16 2014-02-04 Mosaid Technologies Incorporated Clock mode determination in a memory system
US12321600B2 (en) 2007-02-16 2025-06-03 Mosaid Technologies Incorporated Clock mode determination in a memory system
US11880569B2 (en) 2007-02-16 2024-01-23 Mosaid Technologies Incorporated Clock mode determination in a memory system
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WO2011021357A1 (fr) * 2009-08-17 2011-02-24 パナソニック株式会社 Circuit de réception de données
CN109584917B (zh) * 2013-11-07 2023-04-28 瑞萨电子株式会社 半导体器件
CN109584917A (zh) * 2013-11-07 2019-04-05 瑞萨电子株式会社 半导体器件
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US11121710B2 (en) 2017-06-28 2021-09-14 Kioxia Corporation Semiconductor device
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JP2019008859A (ja) * 2017-06-28 2019-01-17 東芝メモリ株式会社 半導体装置
JP2022066040A (ja) * 2020-10-16 2022-04-28 ローム株式会社 オシレータ回路
JP7482745B2 (ja) 2020-10-16 2024-05-14 ローム株式会社 オシレータ回路
CN116469429A (zh) * 2023-03-31 2023-07-21 福建省晋华集成电路有限公司 用于半导体存储器的输入数据预对齐电路

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