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WO2011095099A1 - 栅极驱动电路单元、栅极驱动电路及显示装置 - Google Patents

栅极驱动电路单元、栅极驱动电路及显示装置 Download PDF

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Publication number
WO2011095099A1
WO2011095099A1 PCT/CN2011/070658 CN2011070658W WO2011095099A1 WO 2011095099 A1 WO2011095099 A1 WO 2011095099A1 CN 2011070658 W CN2011070658 W CN 2011070658W WO 2011095099 A1 WO2011095099 A1 WO 2011095099A1
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WIPO (PCT)
Prior art keywords
signal
clock signal
transistor
clock
control
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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PCT/CN2011/070658
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English (en)
French (fr)
Inventor
张盛东
廖聪维
何常德
戴文君
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Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
Original Assignee
Peking University Shenzhen Graduate School
InfoVision Optoelectronics Kunshan Co Ltd
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Priority to US13/386,030 priority Critical patent/US8766958B2/en
Publication of WO2011095099A1 publication Critical patent/WO2011095099A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present invention relates to a display device, and more particularly to a gate drive circuit of a display device.
  • the amorphous silicon TFT process has the characteristics of low processing temperature, uniform device performance, low cost, and is suitable for large-area display, so amorphous silicon TFT LCD technology has become the mainstream of modern flat panel display technology.
  • the gate drive circuit is an important component of the amorphous silicon TFT LCD in order to further improve the amorphous silicon TFT The performance of LCD and its cost have been reduced.
  • the gate driving method adopted by most flat panel displays is to connect the peripheral IC chip to the display panel by pressure sealing.
  • the method of integrating the amorphous silicon TFT gate driving circuit on the glass substrate can not only reduce the number of peripheral driving chips and the sealing process thereof, but also can be made light in weight, thin in thickness and symmetrical in appearance.
  • the narrow bezel panel reduces the overall cost of the liquid crystal panel, making the liquid crystal module more compact and mechanically more reliable.
  • amorphous silicon TFTs The fabrication of integrated circuits using amorphous silicon TFTs generally faces two difficulties: First, the carrier mobility of amorphous silicon is low, so that amorphous silicon TFTs are difficult to provide large driving currents, which leads to slow circuit speeds of integrated amorphous silicon TFTs. Second, under the action of long-term electrical stress, the threshold voltage of the amorphous silicon TFT will drift, and the drift of the threshold voltage will bring instability of the circuit performance or even failure of the circuit.
  • the main technical problem to be solved by the present invention is to provide a gate driving circuit unit, a gate driving circuit and a display device, which reduce the complexity of the circuit, reduce power consumption and improve the stability of the circuit.
  • the present invention discloses a gate driving circuit unit comprising: a signal input interface for receiving an input pulse signal; a signal output interface for outputting a driving signal; and a first clock signal control module including a driving unit and a clock a feedthrough suppression unit, the drive unit includes a control end, the control terminal of the drive unit receives a driving voltage, and transmits a first clock signal to the signal output interface; the clock feedthrough suppression unit is used at the first The control terminal is coupled to the signal output interface under control of a clock signal; the first clock signal is delayed by one phase from the input pulse signal; and the input signal control module is configured to receive an input pulse signal from the signal input interface, And providing a driving voltage to the control terminal of the driving unit under the control of the input pulse signal; and a third clock signal control module, configured to provide a shutdown voltage to the control terminal of the driving unit under the control of the third clock signal, The third clock signal is delayed by two phases from the first clock signal; the fourth clock signal control module is used Under the control of the fourth clock signal
  • the first clock signal, the third clock signal, and the fourth clock signal have the same N-phase clock signals of three periods, where N is an integer greater than or equal to 4.
  • the value of the one phase is equal to 2 ⁇ /N.
  • the input signal control module is configured to charge a control end of the driving unit under control of an input pulse signal; the driving unit is configured to input the first clock signal, Transmitting the first clock signal to the signal output interface after the driving voltage is turned on; the third clock signal control module is configured to respond to the third clock signal, and the driving unit is controlled under the control of the third clock signal The voltage at the control terminal.
  • Another gate driving circuit unit disclosed by the present invention comprises: a signal input interface for receiving an input pulse signal; a signal output interface for outputting a driving signal; and a first clock signal control module including a driving unit and clock feedthrough suppression a unit, the driving unit includes a control end, the control end of the driving unit receives a driving voltage, and transmits a first clock signal to the signal output interface; the clock feedthrough suppression unit is used in the first clock signal Controlling the control terminal to the signal output interface; the first clock signal is delayed by one phase from the input pulse signal; and the input signal control module is configured to receive an input pulse signal from the signal input interface and input a control signal of the driving unit is provided with a driving voltage, and a second clock signal control module is configured to pull down the voltage of the signal output interface under the control of the second clock signal, the second The clock signal is delayed by one phase from the first clock signal; the third clock signal control module is configured to be at the third clock signal Providing a shutdown voltage to the control terminal of the driving unit, the third clock signal is delayed by
  • the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are M-phase clock signals of the same four periods, where M is an integer greater than or equal to 4.
  • the value of the one phase is equal to 2 ⁇ /M.
  • the present invention also discloses a gate driving circuit including any one of the above gate driving circuit units, the gate driving circuit comprising a multi-stage serially connected gate driving circuit unit, the first stage gate driving The signal output interface of the circuit unit is coupled to the signal input interface of the gate driving circuit unit of the subsequent stage, the at least one gate driving circuit unit is the gate driving circuit unit of any one of the above, and the gate driving circuit unit of the first stage The clock signal is delayed by one phase from the corresponding clock signal of the previous stage gate drive circuit unit.
  • the present invention also discloses a display device comprising: a panel comprising a two-dimensional pixel array composed of a plurality of pixels, and a plurality of data lines and a first direction connected to each pixel array a plurality of gate scan lines in two directions; a data driving circuit for providing an image signal to the data lines; and the gate driving circuit for providing a driving signal to the gate scan lines.
  • the invention adopts the circuit design of the multi-phase clock, completes the function of the gate driving circuit with few transistors, reduces the complexity of the circuit design, reduces the area of the gate driving circuit, reduces the power consumption thereof, and Improve its stability.
  • FIG. 1 exemplarily depicts a structural block diagram of a display device
  • FIG. 2 exemplarily depicts a structural block diagram of a gate driving circuit of the present invention
  • FIG. 3 exemplarily depicts a circuit diagram of a gate driving circuit unit of the present invention
  • FIG. 4 exemplarily depicts a signal diagram of a gate driving circuit unit of the present invention
  • FIG. 5 exemplarily shows a circuit diagram when the gate driving circuit of the present invention adopts a gate driving circuit unit is driven by a four-phase clock;
  • FIG. 6 exemplarily illustrates a signal diagram when the gate driving circuit of the present invention employs a gate driving circuit unit is driven by a four-phase clock;
  • FIG. 7 exemplarily shows a circuit diagram when the gate driving circuit of the present invention employs a gate driving circuit unit is driven by a six-phase clock;
  • FIG. 8 exemplarily shows a signal diagram when the gate driving circuit of the present invention adopts a gate driving circuit unit is driven by a six-phase clock
  • FIG. 9 exemplarily shows a circuit diagram when the gate driving circuit of the present invention employs a gate driving circuit unit is driven by an eight-phase clock;
  • FIG. 10 exemplarily shows a signal diagram when the gate driving circuit of the present invention adopts a gate driving circuit unit is driven by an eight-phase clock;
  • FIG. 11 exemplarily depicts a circuit diagram of another gate driving circuit unit of the present invention.
  • FIG. 12 exemplarily depicts a signal diagram of another gate driving circuit unit of the present invention.
  • FIG. 13 exemplarily shows a circuit diagram when the gate driving circuit of another gate driving circuit unit of the present invention is driven by a four-phase clock;
  • FIG. 14 exemplarily shows a signal diagram when the gate driving circuit of another gate driving circuit unit of the present invention is driven by a four-phase clock;
  • FIG. 15 exemplarily shows a circuit diagram when the gate driving circuit of another gate driving circuit unit of the present invention is driven by a six-phase clock;
  • Fig. 16 exemplarily shows a signal diagram when the gate drive circuit of another gate drive circuit unit of the present invention is driven by a six-phase clock.
  • the display device 1 includes a panel 4, a data driving circuit 3, and a gate driving circuit 2.
  • the panel 4 includes a two-dimensional pixel array composed of a plurality of pixels 41, 42, 43, 44, 45, 46, and a plurality of data lines and a second direction (for example, a longitudinal direction) connected to each pixel array A plurality of gate scan lines in a direction (eg, lateral).
  • the pixels 41, 42, 43, 44, 45, and 46 are taken as an example, and those skilled in the art should understand that the number of pixels included in each row or column is determined according to the specific conditions of the panel.
  • each gate scan line corresponds to a row in the pixel array
  • each data line corresponds to a column in the pixel array.
  • the data driving circuit 3 is for outputting an image signal to the data line; the gate driving circuit 2 is for outputting a driving signal to the gate scanning line to complete line scanning of the pixel array.
  • the gate drive circuit may be connected to the panel by soldering or integrated on the panel.
  • the display device 1 may be a liquid crystal display, an organic light emitting display, an electronic paper display, or the like.
  • FIG. 2 is a block diagram showing the structure of the gate driving circuit 2.
  • the gate driving circuit 2 includes a multi-level gate driving circuit unit connected in series, and the signal output interface Vout of the previous-stage gate driving circuit unit is coupled to the signal input interface Vin of the subsequent-stage gate driving circuit unit, and the first-level driving circuit unit
  • the input signal is provided by the signal generator, and the signal output interface Vout of each stage of the driving circuit unit is connected to a corresponding one of the gate scanning lines on the load panel.
  • the signal generator is also used to provide a low level signal Vss to each stage of the gate drive circuit unit.
  • the clock generator provides clock signals to the gate drive circuit units of each stage.
  • FIG. 3 is a circuit diagram of a specific embodiment of a gate drive circuit unit. First, some terms are explained.
  • the transistor can be a bipolar transistor or a field effect transistor.
  • the control electrode refers to the base of the bipolar transistor, and the first and second main current conducting electrodes respectively refer to the collector and the emitter of the bipolar transistor.
  • the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, and the first and second main current conducting electrodes respectively refer to the drain and source of the field effect transistor.
  • the transistor in the display device is usually a thin film transistor (TFT).
  • TFT thin film transistor
  • the gate of the transistor refers to the gate of the thin film transistor, and the first and second main current conducting electrodes respectively refer to the drain and the source of the thin film transistor.
  • the structure and operation of the gate driving circuit unit shown in FIG. 3 will be described below by taking a transistor as a TFT as an example.
  • the gate driving circuit unit includes: The signal input interface Vin, the signal output interface Vout, the input signal control module 111, the first clock signal control module 32, the third clock signal control module 33, and the fourth clock signal control module 34.
  • the signal input interface Vin is used to receive an input pulse signal.
  • the signal output interface Vout is used to output a drive signal.
  • the first clock signal control module 32 includes a driving unit and a clock feedthrough suppression unit, the driving unit includes a control end, and the control terminal of the driving unit receives the driving voltage, and transmits the first clock signal to the signal output interface;
  • the clock feedthrough suppression unit is configured to couple the control terminal to the signal output interface under control of a first clock signal; the first clock signal is delayed by one phase from the input pulse signal.
  • the input signal control module 31 is configured to receive an input pulse signal from the signal input interface and provide a driving voltage to the control terminal of the driving unit.
  • the third clock signal control module 33 is configured to provide a shutdown voltage to the control terminal of the driving unit under the control of the third clock signal, the third clock signal being delayed by two phases from the first clock signal.
  • the fourth clock signal control module 34 is configured to pull down the voltage of the signal output interface under the control of the fourth clock signal, the fourth clock signal being ahead of the first clock signal by one phase.
  • the input signal control module 31 includes a first transistor T1, and the gate and the drain of the first transistor T1 receive an input signal Vin.
  • the source of the first transistor T1 is used to output a driving voltage signal;
  • the first clock signal control module 32 includes a driving unit and a clock feedthrough suppression unit, the driving unit includes a second transistor T2, and the gate of the second transistor T2 a pole is connected to a source of the first transistor T1,
  • the gate of the second transistor T2 is the control terminal of the driving unit, and the connection node defining the source of the first transistor T1 and the gate of the second transistor T2 is the node Q, and the drain of the second transistor T2 is input first.
  • a source of the second transistor T2 is coupled to the signal output interface Vout for controlling a high voltage of the first clock signal CLKA under control of a gate voltage of the second transistor T2
  • the signal output interface is charged when it arrives, and the potential of the signal output interface Vout is pulled down when the low level of the first clock signal CLKA comes.
  • the clock feedthrough suppression unit includes a fifth transistor T5, the gate of the fifth transistor T5 is responsive to the first clock signal CLKA, the drain thereof is connected to the gate of the second transistor T2, and the source is connected to the signal output interface Vout,
  • the five transistor T5 is for coupling the gate of the second transistor T2 to the signal output interface Vout when the high level of the first clock signal CLKA comes when the signal output is low, thereby stabilizing the gate of the second transistor T2 Potential.
  • the third clock signal control module 33 includes a third transistor T3 whose gate is responsive to a third clock signal CLKC, and a drain of the third transistor T3 is coupled to a gate of the second transistor T2.
  • the source of the third transistor T3 is connected to the first voltage source Vss, the first voltage source Vss is used to provide a low level, and the third transistor T3 is used to be the second when the high level of the third clock signal CLKC comes
  • the gate of transistor T2 is coupled to a first voltage source Vss, thereby pulling the potential of the gate of the second transistor T2 low.
  • the fourth clock signal control module 34 includes a fourth transistor T4, the gate of the fourth transistor T4 is responsive to the fourth clock signal CLKD, the drain is connected to the signal output interface Vout, and the source is connected to the A voltage source Vss, the fourth transistor T4 is configured to connect the output interface Vout to the first voltage source Vss when the high level of the fourth clock signal CLKD comes, thereby pulling down the voltage of the signal output interface Vout.
  • the three clock signals of the gate driving circuit unit satisfy the following conditions:
  • the first clock signal, the third clock signal, and the fourth clock signal are three-phase clock signals of the same period.
  • the duty ratio of these three clock signals is 1/N.
  • the value of each phase is equal to 2 ⁇ /N. Where N is an integer greater than or equal to 4.
  • the third clock signal CLKC is delayed by two phases from the first clock signal CLKA, and the fourth clock signal CLKD is advanced by one phase than the first clock signal CLKA.
  • the high level of each clock signal is Vdd, and the low level is Vss.
  • the operation process of the gate driving circuit is divided into four stages: a pre-charging phase, a pull-up phase, a pull-down phase, and a low-level sustaining phase, which are described in detail below.
  • the input pulse signal applied to the signal input interface Vin is charged to the node Q through the first transistor T1, and the second transistor T2 is fully opened before participating in the charging of the load. It is called the precharge phase.
  • the clock signals CLKA and CLKC are both low level, the clock signal CLKD is at a high level, the input signal Vin is at a high level, the first transistor T1 is turned on, and the potential of the node Q is gradually raised.
  • the potential of the node Q is higher than the threshold voltage Vth of the second transistor T2, the second transistor T2 is turned on. Since the clock signal CLKA is at a low level, the output signal Vout is kept at a low potential.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are both in an off state.
  • the potential of the node Q reaches Vdd-Vth.
  • the drain voltage of the second transistor T2 becomes a high level, and the process in which the transistor T2 charges the load terminal in the on state and the potential of the signal output interface Vout is finally pulled up to Vdd is referred to as a pull-up phase.
  • the clock signal CLKA goes high, the clock signal CLKC And CLKD is low, the input signal Vin is low, the first transistor T1 is turned off, and the third transistor T3 and the fourth transistor T4 are also in an off state. Therefore, the node Q is suspended, the second transistor T2 is kept on, and the clock signal CLKA supplies a charging current to the load through the second transistor T2.
  • the potential of node Q increases as the output interface Vout is charged, which is referred to as bootstrap.
  • the second transistor T2 operates in a state of saturation conduction, and the fifth transistor T5 is also in a state of saturation conduction; when the output voltage reaches 2Vth, the second transistor T2 enters a linear conduction state; After the output voltage reaches Vdd-Vth, the fifth transistor T5 is turned off.
  • the process in which the second transistor T2, the third transistor T3, and the fourth transistor T4 discharge the output interface Vout and the node Q, respectively, and finally pulls the potentials of the node Q and the output interface Vout to Vss is referred to as a pull-down phase.
  • the pull-down phase consists of two consecutive processes, the first being the discharge of the output interface Vout.
  • Clock signal CLKA, CLKC And CLKD is low. Therefore, the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all in an off state.
  • the second transistor T2 maintains the on state and the drain level of the second transistor is Vss, the potential of the signal output interface Vout is pulled down to Vss through the second transistor T2.
  • the second process in the pull down phase is to discharge the node Q.
  • the clock signal CLKC goes high, and the clock signals CLKA and CLKD go low.
  • the third transistor T3 is turned on, and the stored charge of the node Q is discharged through the third transistor T3. Therefore, the potential of the node Q is lowered.
  • the second transistor T2 is turned off.
  • the charge stored on the node Q must be completely released during the high period of the clock signal CLKC. Otherwise, the second transistor T2 is still in the on state, so that the low state of the signal output interface Vout is in the next cycle of the first clock signal CLKA. It is destroyed by the high level.
  • the gate drive circuit unit When the potential of the output interface is pulled down to Vss, the gate drive circuit unit enters a non-strobe state. At this stage, the potential of the output interface Vout must be stably maintained at the low level Vss, so this phase is referred to as the low level sustain phase.
  • the row selection transistor of the panel connected thereto is turned on by mistake, thereby causing an error in the image information in the panel.
  • the first transistor T1 In the low-level sustain phase, the first transistor T1 is in the off state, and the gate of the second transistor T2 becomes low due to the release of the charge when the clock signal CLKC is at the high level, so the output signal Vout should also be maintained at Low level.
  • the gate potential VQ of the second transistor T2 also increases due to the connection of the gate-drain parasitic capacitance Cgd of the second transistor T2.
  • VQ is greater than the threshold voltage Vth of the transistor T2
  • the transistor T2 is turned on, the load capacitance is charged, and the output signal Vout exhibits a noise voltage. In this case, some measures need to be taken to maintain the low state of the output signal Vout.
  • This embodiment solves this problem from both the prevention of the occurrence of a noise voltage on the output drive signal and the elimination of the noise voltage on the output drive signal.
  • the fifth transistor T5 is added in the present embodiment.
  • the magnitude of the gate potential VQ of the second transistor T2 depends on the ratio of the parasitic capacitance Cgd of the second transistor T2 to the magnitude of the load capacitance of the output interface Vout.
  • the value of the load capacitance of the output interface Vout is much larger than the capacitance of the node Q, so the VQ is significantly reduced, reducing the probability that the second transistor T2 is turned on, thereby reducing the possibility of occurrence of noise voltage.
  • the fifth transistor T5 is added, when the clock signal CLKA transitions from a low level to a high level, the node Q appears at a high level due to the coupling of the gate-drain parasitic capacitance Cgd of the second transistor T2.
  • the fifth transistor T5 is turned on under the control of the clock signal CLKA, the node Q is shorted to the output interface Vout, and the coupled charge on the node Q is released to the output interface Vout through the fifth transistor T5, and the voltage of the node Q drops.
  • the second transistor T2 is kept in the off state, and the output signal Vout is also maintained in the low state.
  • the fifth transistor T5 when the clock signal CLKA transitions from a high level to a low level, likewise, due to the coupling of the gate-drain parasitic capacitance Cgd of the pulled up second transistor T2, the node Q appears more than Vss. Low one low level.
  • the third transistor T3 and the fifth transistor T5 connected to the node Q are both in an off state, and the second transistor T2 is also in an off state, and therefore, the output signal Vout remains in a low state until the clock
  • the transistor of the third transistor T3 is turned on, and the potential of the node Q is restored to Vss.
  • the fourth transistor T4 is added in this embodiment.
  • the fourth transistor T4 is turned on when the clock signal CLKD is at a high level, and the signal output interface is connected to the ground, thereby releasing the noise charge at the signal output interface Vout point, thereby avoiding accumulation of the noise charge for a long time at the signal output interface Vout, thereby eliminating the output.
  • the noise voltage in the drive signal is Moreover, the clock signal CLKD leads the clock signal CLKA by one phase, that is, the falling edge of the clock signal CLKD overlaps with the rising edge of the clock signal CLKA. When the clock signal CLKA is at the rising edge, the clock signal CLKD is at the falling edge, and the fourth transistor The T4 has not been completely turned off, so the noise voltage at the Vout point of the signal output interface can be reduced.
  • the third transistor T3 is turned on when the clock signal CLKC is at a high level, connects the node Q to the ground, releases the noise charge at the Q point, avoids the accumulation of the long-term noise charge at the Q point, and ensures that the second transistor T2 is low.
  • the reliable shutdown of the flat sustain phase prevents the second transistor T2 from pulling up the voltage at the signal output interface Vout point.
  • the clock feedthrough suppression unit further includes a storage capacitor Cs coupled between the gate and the source of the second transistor T2.
  • a storage capacitor Cs coupled between the gate and the source of the second transistor T2.
  • the transistor T5 and the storage capacitor Cs together constitute a clock feedthrough suppression unit, which can reduce the noise of the output signal of the low level sustain phase and make the output signal more stable.
  • the gate driving circuit of the embodiment is designed by using a multi-phase clock and using a very small number of transistors, compared with the two-phase clock driving scheme in which more than 10 transistors are required in the prior art.
  • the function of the gate driving circuit reduces the complexity of the circuit design, reduces the circuit design area, reduces the power consumption, is more suitable for high-quality display devices, and improves the yield of circuit manufacturing.
  • the power consumption of the gate driving circuit is mainly dynamic power consumption, which is proportional to the frequency of the clock.
  • three clock signals are designed, and a clock signal greater than or equal to four phases is used to reduce the frequency of the clock transition. Thereby reducing power consumption.
  • the stability of the output driving signal is maintained from the prevention of the occurrence of the noise voltage on the output driving signal and the elimination of the noise voltage on the output driving signal, and the stable driving signal is provided to the pixel array, and the next step is
  • the stage gate drive circuit unit provides a stable input signal, thereby improving the stability of the entire gate drive circuit and the image display quality of the display device.
  • the duty ratio of the gate voltage signal of the pull-down transistor subjected to the voltage stress in the circuit is small, so the threshold voltage drift of the transistor is small, the electrical characteristic degradation is reduced, and the circuit stability is good. Thereby the lifetime of the gate drive circuit is extended.
  • clock phases used by the gate driving circuit are four, six, and eight.
  • the clock signal of the second-stage gate driving circuit unit is higher than the corresponding clock signal of the previous-stage gate driving circuit unit. To lag a phase.
  • the connection of the clock interface of the k*N+1th gate drive circuit unit is the same as that of the first stage gate drive circuit unit, and the k*N+2 stage gate drive
  • the clock interface of the circuit unit is connected to the second-stage gate driving circuit unit.
  • the clock interface of the k*N+i-th gate driving circuit unit is connected to the same as the i-th gate driving circuit unit.
  • the clock signal provided by the clock generator is a four-phase clock signal, which is CLK1, CLK2, CLK3, and CLK4, respectively, and the pulse duty ratio is 25%.
  • the clocks of the gate drive circuit units of each stage are specifically connected. The way is:
  • the clock interface CLKA of the first stage gate driving circuit unit 51 is connected to the signal CLK1, the clock interface CLKC is connected to the signal CLK3, the clock interface CLKD is connected to the signal CLK4, and the clock interface CLKA of the second stage gate driving circuit unit 52 is connected to the signal CLK2, and the clock interface CLKC is connected to signal CLK4, clock interface CLKD is connected to signal CLK1; clock interface CLKA of third stage gate drive circuit unit 53 is connected to signal CLK3, clock interface CLKC is connected to signal CLK1, clock interface CLKD is connected to signal CLK2; fourth stage gate drive circuit The clock interface CLKA of the unit 54 is connected to the signal CLK4, the clock interface CLKC is connected to the signal CLK2, and the clock interface CLKD is connected to the signal CLK3...
  • connection of the remaining stages when the number of stages is divided by 4, the connection of the clock interface of the gate driving circuit unit is the same as that of the first stage gate driving circuit unit; if the number of stages is divided by 4 by 2, then The clock interface of the gate driving circuit unit is connected to the second-stage gate driving circuit unit; if the number of stages is divided by 4 by 3, the connection of the clock interface of the gate driving circuit unit and the third-level gate The pole drive circuit unit is the same; if the number of stages is divisible by 4, the connection of the clock interface of the gate drive circuit unit is the same as that of the fourth stage gate drive circuit unit.
  • the operation signal diagram when driving with a four-phase clock is as shown in FIG. 6.
  • the gate driving circuit provides a driving signal for each row of the load panel shown in FIG. 1 under the action of the four-phase clock signal and the start pulse signal. .
  • the six-phase clock signal used by the gate driving circuit is as shown in FIG. 7.
  • the clock signal provided by the clock generator is a six-phase clock signal, which is CLK1, CLK2, CLK3, CLK4, CLK5, and CLK6, respectively.
  • the space ratio is 1/6
  • the specific connection method of the clocks of the gate drive circuit units of each level is:
  • the clock interface CLKA of the first stage gate driving circuit unit 71 is connected to the signal CLK1
  • the clock interface CLKC is connected to the signal CLK3
  • the clock interface CLKD is connected to the signal CLK4
  • the clock interface CLKA of the second stage gate driving circuit unit 72 is connected to the signal CLK2, the clock interface.
  • CLKC is connected to signal CLK4, clock interface CLKD is connected to signal CLK5; clock interface CLKA of third stage gate drive circuit unit 73 is connected to signal CLK3, clock interface CLKC is connected to signal CLK5, clock interface CLKD is connected to signal CLK6; fourth stage gate drive circuit
  • the clock interface CLKA of the unit 74 is connected to the signal CLK4, the clock interface CLKC is connected to the signal CLK6, the clock interface CLKD is connected to the signal CLK1, and the clock interface CLKA of the fifth-stage gate driving circuit unit (not shown) is connected to the signal CLK5, the clock interface CLKC Connected to the signal CLK1, the clock interface CLKD is connected to the signal CLK2; the clock interface CLKA of the sixth-stage gate driving circuit unit (not shown) is connected to the signal CLK6, the clock interface CLKC is connected to the signal CLK2, and the clock interface CLKD is connected to the signal CLK3...
  • connection of the remaining stages when the number of stages is divided by 6 by 1, the connection of the clock interface of the gate driving circuit unit is the same as that of the first stage gate driving circuit unit; if the number of stages is divided by 6 by 2, then The clock interface of the gate driving circuit unit is connected to the second-stage gate driving circuit unit; if the number of stages is divided by 6 by 3, the connection of the clock interface of the gate driving circuit unit and the third-level gate The pole drive circuit unit is the same; if the number of stages is divided by 6 by 4, the connection of the clock interface of the gate drive circuit unit is the same as that of the fourth stage gate drive circuit unit; if the number of stages is divided by 6 by 5, then the The connection of the clock interface of the gate driving circuit unit is the same as that of the fifth-level gate driving circuit unit; if the number of stages is divisible by 6, the connection of the clock interface of the gate driving circuit unit and the sixth-level gate driving circuit The units are the same.
  • the operation signal diagram when driving with a six-phase clock is as shown in FIG. 8.
  • the gate driving circuit provides a driving signal for each row of the panel 4 shown in FIG. 1 under the action of the above-described six-phase clock signal and the start pulse signal. .
  • the eight-phase clock signal used by the gate driving circuit is as shown in FIG. 9.
  • the clock signal provided by the clock generator is an eight-phase clock signal, which is CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, and CLK8, the pulse duty ratio is 1/8, and the clock connection mode of each level of gate drive circuit unit is:
  • the clock interface CLKA of the first stage gate driving circuit unit 91 is connected to the signal CLK1, the clock interface CLKC is connected to the signal CLK3, the clock interface CLKD is connected to the signal CLK4, and the clock interface CLKA of the second stage gate driving circuit unit 92 is connected to the signal CLK2, and the clock interface CLKC is connected to signal CLK4, clock interface CLKD is connected to signal CLK5; clock interface CLKA of third-stage gate drive circuit unit 93 is connected to signal CLK3, clock interface CLKC is connected to signal CLK5, clock interface CLKD is connected to signal CLK6; fourth stage gate drive circuit
  • the clock interface CLKA of the unit 94 is connected to the signal CLK4, the clock interface CLKC is connected to the signal CLK6, the clock interface CLKD is connected to the signal CLK7, and the clock interface CLKA of the fifth-stage gate driving circuit unit (not shown) is connected to the signal CLK5, the clock interface CLKC Connected to the signal CLK7, the clock interface CLKD is connected to the signal CLK8
  • connection of the remaining stages when the number of stages is divided by 8 by 1, the connection of the clock interface of the gate driving circuit unit is the same as that of the first stage gate driving circuit unit; if the number of stages is divided by 8 by 2, then The clock interface of the gate driving circuit unit is connected to the second-stage gate driving circuit unit; if the number of stages is divided by 8 by 3, the connection of the clock interface of the gate driving circuit unit and the third-level gate The pole drive circuit unit is the same; if the number of stages is divided by 8 by 4, the connection of the clock interface of the gate drive circuit unit is the same as that of the fourth stage gate drive circuit unit; if the number of stages is divided by 8 by 5, then The connection of the clock interface of the gate driving circuit unit is the same as that of the fifth-level gate driving circuit unit; if the number of stages is divided by 8 by 6, the connection of the clock interface of the gate driving circuit unit and the sixth-level gate The driving circuit unit is the same; if the number of stages is divided by 7, the clock interface of the gate driving circuit unit is connected
  • the signal diagram of the operation when the eight-phase clock is driven is as shown in FIG. 10.
  • the gate driving circuit provides driving for each row of the panel 4 shown in FIG. 1 under the action of the above eight-phase clock signal and the start pulse signal. signal.
  • the circuit structure of the gate driving circuit unit is as shown in FIG. 11.
  • the gate driving circuit unit includes a signal input interface Vin, a signal output interface Vout, an input signal control module 111, and a first clock signal control module 112.
  • the signal input interface Vin is used for receiving the input pulse signal. If the gate driving circuit unit of the current stage is the first stage, the input pulse signal is provided by the signal generator. If the gate driving circuit unit of the current stage is not the first stage, the input pulse is input.
  • the signal is provided by the previous stage gate driving circuit unit, that is, the signal input interface of the gate driving circuit unit of the present stage is coupled to the signal output interface of the previous stage gate driving circuit unit.
  • the signal output interface Vout is for outputting a drive signal to a corresponding scan line and a signal input interface of the next stage gate drive circuit unit.
  • the first clock signal control module 112 includes a driving unit and a clock feedthrough suppression unit, the driving unit includes a control terminal for inputting a driving voltage, and the driving unit is in the first clock signal after being turned on by the driving voltage Controlling, outputting a driving signal to the signal output interface Vout; the clock feedthrough suppression unit is configured to connect the control terminal to the signal output interface under control of a first clock signal; the first clock signal One phase is delayed from the input pulse signal.
  • the input signal control module 111 is configured to receive an input pulse signal from the signal input interface, and provide a driving voltage to the control terminal of the driving unit under the control of the input pulse signal.
  • the second clock signal control module 115 is configured to pull down the voltage of the signal output interface under control of the second clock signal, the second clock signal being delayed by one phase from the first clock signal.
  • the third clock signal control module 113 is configured to provide a shutdown voltage to the control terminal of the driving unit under the control of the third clock signal, the third clock signal being delayed by two phases from the first clock signal.
  • the fourth clock signal control module 114 is configured to pull down the voltage of the signal output interface under the control of the fourth clock signal, the fourth clock signal being ahead of the first clock signal by one phase.
  • This embodiment adds a second clock signal control module based on the above embodiment, having four clock signals, working of the first clock signal CLKA, the second clock signal CLKB, the third clock signal CLKC, and the fourth clock signal CLKD.
  • N An N-phase clock signal having the same period, wherein N is an integer greater than or equal to 4.
  • the second clock signal CLKB is delayed by one phase from the first clock signal CLKA
  • the third clock signal CLKC is delayed by two phases from the first clock signal CLKA
  • the fourth clock signal CLKD is advanced by one phase than the first clock signal CLKA.
  • FIG. 11 shows a specific circuit structure of the gate driving circuit unit in another embodiment.
  • the second clock signal control module 115 is added.
  • the second clock signal control module 115 includes a sixth transistor T6, the gate of the sixth transistor T6 is responsive to the second clock signal CLKB, the drain thereof is connected to the signal output interface Vout, and the source is connected to the first voltage source Vss for When the high level of the second clock signal CLKB comes, the potential of the signal output interface Vout is pulled down to Vss.
  • the second transistor T2 pulls down the voltage of the signal output interface Vout to a low level of the first clock signal CLKA. Meanwhile, when the high level of the second clock signal CLKB comes, the sixth transistor T6 is turned on, the signal output interface Vout is connected to the voltage source Vss, and the second transistor T2 and the sixth transistor T6 are simultaneously pulled down to make the signal output.
  • the voltage of the interface Vout is quickly pulled down to a low level, so that the falling edge time of the output driving signal is shorter, and the driving effect on the pixel array is better.
  • the sixth transistor T6 adds a discharge path to the output interface Vout, which ensures that the output interface Vout has no accumulation of noise voltage during the low level maintenance phase, which helps to improve the low level stability of the output signal Vout.
  • the signal diagram of the working of this embodiment is as shown in FIG. Clock signal CLKA
  • the high potentials of CLKB, CLKC, and CLKD are both Vdd, the low potential is Vss, and the duty cycle is 25%.
  • the input signal Vin of the circuit is the output signal of the upper gate drive circuit unit.
  • the output signal of the gate drive circuit unit of this stage is Vout.
  • the basic operation principle of the gate driving circuit unit of the embodiment is the same as that of the gate driving circuit unit of the above embodiment, and the working process also includes a pre-charging phase, a pull-up phase, a pull-down phase, and a low-level sustaining phase, which are not described herein. .
  • the clock signal of the latter-stage gate driving circuit unit is higher than that of the previous-stage gate.
  • the corresponding clock signal of the drive circuit unit is delayed by one phase.
  • the clock signal provided by the clock generator is a four-phase clock signal, which is CLK1, CLK2, CLK3, and CLK4, respectively, and the pulse duty ratio is 25%, and the clocks of the gate drive circuit units of each stage are specifically connected.
  • CLK1, CLK2, CLK3, and CLK4 respectively
  • the pulse duty ratio is 25%
  • the clocks of the gate drive circuit units of each stage are specifically connected.
  • the clock interface CLKA of the first stage gate driving circuit unit 131 is connected to the signal CLK1, the clock interface CLKB is connected to the signal CLK2, the clock interface CLKC is connected to the signal CLK3, the clock interface CLKD is connected to the signal CLK4, and the clock interface of the second stage gate driving circuit unit 132 is connected.
  • CLKA is connected to signal CLK2
  • clock interface CLKB is connected to signal CLK3
  • clock interface CLKC is connected to signal CLK4
  • clock interface CLKD is connected to signal CLK1
  • clock interface CLKA of third-stage gate drive circuit unit 133 is connected to signal CLK3, and clock interface CLKB is connected to signal CLK4.
  • the clock interface CLKC is connected to the signal CLK1, the clock interface CLKD is connected to the signal CLK2; the clock interface CLKA of the fourth stage gate driving circuit unit 134 is connected to the signal CLK4, the clock interface CLKB is connected to the signal CLK1, the clock interface CLKB is connected to the signal CLK2, and the clock interface CLKD is connected to the signal CLK2.
  • CLK3 The clock interface CLKC is connected to the signal CLK1, the clock interface CLKD is connected to the signal CLK2;
  • the clock interface CLKA of the fourth stage gate driving circuit unit 134 is connected to the signal CLK4
  • the clock interface CLKB is connected to the signal CLK1
  • the clock interface CLKB is connected to the signal CLK2
  • the clock interface CLKD is connected to the signal CLK2.
  • connection of the clock interface of the gate drive circuit unit is the same as that of the first stage; if the number of stages is divided by 4, the gate drive The connection of the clock interface of the circuit unit is the same as that of the second stage; if the number of stages is divided by 4 by 3, the connection of the clock interface of the gate drive circuit unit is the same as that of the third stage; if the number of stages is divisible by 4 Then, the connection of the clock interface of the gate driving circuit unit is the same as that of the fourth stage.
  • the signal diagram when the four-phase clock is driven in this embodiment is as shown in FIG.
  • the circuit diagram when the six-phase clock is driven in this embodiment is as shown in FIG.
  • the signal diagram when the six-phase clock is driven in this embodiment is as shown in FIG. 16.
  • the input signal control module, the driving unit, the third clock signal control module, the second clock signal control module, the fourth clock signal control module, and the clock feedthrough suppression unit are in addition to the single transistor in the above embodiment, in another In an embodiment, at least one of them may also employ a plurality of transistors, which are connected to complete the function of the module.
  • the present invention has the following advantages:
  • the pull-up and pull-down of the output potential are performed by the same transistor.
  • the pull-up and pull-down are performed by two different transistors, respectively. Therefore, this circuit occupies a small layout area.
  • the output signal of the next-stage gate drive circuit is required to be pulled down to the current stage.
  • the circuit does not need to use the output signal of the next-stage gate driving circuit, which reduces the load of the next-stage unit circuit, and reduces the level of the next-stage unit circuit pull-up delay. The increase in pull-down delay time.
  • the number of transistors constituting the gate driving circuit unit of the present invention is only five or six. In the case of a conventional two-phase clock drive, typically more than 10 transistors are required. Therefore, the gate driving circuit according to the present invention requires a small number of transistors, a simple circuit, a small footprint, and a higher manufacturing yield.
  • the voltage stress of the pull-down transistor in the gate driving circuit according to the present invention is smaller than that of the conventional circuit, so that the threshold voltage drift of the transistor in the circuit is small, and the electrical characteristic degradation is reduced, so that the gate driving circuit has Better stability.
  • the gate drive circuit uses multi-phase clock control, so its power consumption is less than that of the conventional two-phase clock-controlled gate drive circuit.
  • the gate driving circuit may be composed of an amorphous silicon thin film transistor and may be integrated on a panel of a display device, which is completed together with the pixel array.

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Description

栅极驱动电路单元、栅极驱动电路及显示装置 技术领域
本发明涉及一种显示装置，特别涉及显示装置的栅极驱动电路。
背景技术
非晶硅TFT工艺具有加工温度低、器件性能均匀、成本低、适用于大面积显示的特点，因此非晶硅TFT LCD工艺已经成为现代平板显示技术的主流。
栅极驱动电路是非晶硅TFT LCD的重要组成部分，为了进一步地提高非晶硅TFT LCD的性能以及降低其成本，近年来，集成非晶硅TFT栅极驱动电路的研究受到了广泛的重视。目前大多数平板显示器所采用的栅极驱动方式是通过压封的办法将外围的IC芯片连接到显示面板。与这种常规方式相比，将非晶硅TFT栅极驱动电路集成于玻璃基板上的方式不仅能够减少外围驱动芯片的数量及其压封工序，而且能够制作成质量轻、厚度薄且外观对称的窄边框面板，使液晶面板的总体费用降低，使液晶模组更加紧凑，机械可靠性更强。
应用非晶硅TFT制作集成电路通常面临两个难题：一是非晶硅的载流子迁移率低，从而非晶硅TFT难于提供大的驱动电流，这导致了集成非晶硅TFT的电路速度慢；二是在长时间的电应力作用下，非晶硅TFT的阈值电压会发生漂移，这种阈值电压的漂移会带来电路性能的不稳定甚至电路的失效。
迄今为止，已经有多篇报道提出了几种集成非晶硅TFT栅极驱动电路方案来解决这两个难题，这些报道中提到的电路一般采用栅极电压自举技术提高上拉TFT的驱动能力，采用半周期开启的驱动方式抑制下拉TFT管的阈值电压漂移，采用占空比为50%的两相时钟信号作为时钟信号，通常一个栅极驱动电路单元为达到上述功能需要包含十多个晶体管。然而这种两相时钟的栅极驱动电路存在明显的不足：电路的功耗大，稳定性差，器件的数量多导致电路复杂、版图面积大等。这些不足使得两相时钟的集成栅极驱动电路在低功耗、高性能以及高分辨率显示领域中的应用受到了限制。因此，如何降低集成栅极驱动电路的功耗、提高其稳定性，降低电路的复杂程度仍为亟待研究的问题。
 技术问题
本发明要解决的主要技术问题是，提供了一种栅极驱动电路单元、栅极驱动电路及显示装置，降低电路的复杂程度、减少功耗并提高电路的稳定性。
技术解决方案
一方面，本发明公开了一种栅极驱动电路单元，包括：信号输入接口，用于接收输入脉冲信号；信号输出接口，用于输出驱动信号；第一时钟信号控制模块，包括驱动单元和时钟馈通抑制单元，所述驱动单元包括控制端，所述驱动单元的控制端接受驱动电压后，将第一时钟信号传送至所述信号输出接口；所述时钟馈通抑制单元用于在第一时钟信号的控制下将所述控制端耦合到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位；输入信号控制模块，用于从信号输入接口接收输入脉冲信号，并在输入脉冲信号的控制下，给所述驱动单元的控制端提供驱动电压；第三时钟信号控制模块，用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位；第四时钟信号控制模块，用于在第四时钟信号的控制下，拉下所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。
其中，所述第一时钟信号、第三时钟信号和第四时钟信号三个周期相同的N相时钟信号，其中，N为大于或等于4的整数。所述一个相位的值等于2π/N。
在一种实施例中，所述输入信号控制模块用于在输入脉冲信号的控制下，给所述驱动单元的控制端充电；所述驱动单元用于输入所述第一时钟信号，在被所述驱动电压开启后将所述第一时钟信号传递到所述信号输出接口；所述第三时钟信号控制模块用于响应第三时钟信号，且在第三时钟信号的控制下拉下所述驱动单元的控制端的电压。
本发明公开的另一种栅极驱动电路单元包括：信号输入接口，用于接收输入脉冲信号；信号输出接口，用于输出驱动信号；第一时钟信号控制模块，包括驱动单元和时钟馈通抑制单元，所述驱动单元包括控制端，所述驱动单元的控制端接受驱动电压后，将第一时钟信号传送至所述信号输出接口；所述时钟馈通抑制单元用于在第一时钟信号的控制下将所述控制端耦合到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位；输入信号控制模块，用于从信号输入接口接收输入脉冲信号，并在输入脉冲信号的控制下，给所述驱动单元的控制端提供驱动电压；第二时钟信号控制模块，用于在第二时钟信号的控制下，拉下所述信号输出接口的电压，所述第二时钟信号比第一时钟信号滞后一个相位;第三时钟信号控制模块，用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位；第四时钟信号控制模块，用于在第四时钟信号的控制下，拉下所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。
所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号是四个周期相同的M相时钟信号，其中，M为大于或等于4的整数。所述一个相位的值等于2π/M。
另一方面，本发明还公开了一种包括以上任一种栅极驱动电路单元的栅极驱动电路，该栅极驱动电路包括多级串接的栅极驱动电路单元，前一级栅极驱动电路单元的信号输出接口耦合到后一级栅极驱动电路单元的信号输入接口，至少一个栅极驱动电路单元为上述任一个所述的栅极驱动电路单元，且后一级栅极驱动电路单元的时钟信号比前一级栅极驱动电路单元的相应的时钟信号滞后一个相位。
又一方面，本发明还公开一种显示装置，包括：面板，所述面板包括由多个像素构成的二维像素阵列，以及与每个像素阵列相连的第一方向的多条数据线和第二方向的多条栅极扫描线；数据驱动电路，用于给所述数据线提供图像信号；上述所述的栅极驱动电路，用于给所述栅极扫描线提供驱动信号。
本发明通过多相时钟的电路设计，采用极少的晶体管即完成了栅极驱动电路的功能，降低了电路设计的复杂程度，减小了栅极驱动电路的面积，减少了其功耗，并且提高了其稳定性。
 附图说明
图1示例性地描述了显示装置的结构框图；
图2示例性地描述了本发明的栅极驱动电路的结构框图；
图3示例性地描述了本发明的一种栅极驱动电路单元的电路图；
图4示例性地描述了本发明一种栅极驱动电路单元的信号图；
图5示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由四相时钟驱动时的电路图；
图6示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由四相时钟驱动时的信号图；
图7示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由六相时钟驱动时的电路图；
图8示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由六相时钟驱动时的信号图；
图9示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由八相时钟驱动时的电路图；
图10示例性地描述了本发明采用一种栅极驱动电路单元的栅极驱动电路由八相时钟驱动时的信号图；
图11示例性地描述了本发明的另一种栅极驱动电路单元的电路图；
图12示例性地描述了本发明的另一种栅极驱动电路单元的信号图；
图13示例性地描述了本发明采用另一种栅极驱动电路单元的栅极驱动电路由四相时钟驱动时的电路图；
图14示例性地描述了本发明采用另一种栅极驱动电路单元的栅极驱动电路由四相时钟驱动时的信号图；
图15示例性地描述了本发明采用另一种栅极驱动电路单元的栅极驱动电路由六相时钟驱动时的电路图；
图16示例性地描述了本发明采用另一种栅极驱动电路单元的栅极驱动电路由六相时钟驱动时的信号图。
 本发明的实施方式
下面对照附图并结合具体实施方式对本发明进行进一步详细说明。
如图1所示，显示装置1包括面板4、数据驱动电路3和栅极驱动电路2。所述面板4包括由多个像素41、42、43、44、45、46构成的二维像素阵列，以及与每个像素阵列相连的第一方向（例如纵向）的多条数据线和第二方向（例如横向）的多条栅极扫描线。图1中以像素41、42、43、44、45、46为例进行表示，本领域技术人员应当理解，每一行或每一列所包括的像素数量根据面板的具体情况确定。通常，每条栅极扫描线对应于像素阵列中的一行，每条数据线对应像素阵列中的一列。数据驱动电路3用于输出图像信号到所述数据线；栅极驱动电路2用于输出驱动信号到所述栅极扫描线，以完成对像素阵列的行扫描。所述栅极驱动电路可以通过焊接与面板相连或者将栅极驱动电路集成在面板上。显示装置1可以是液晶显示器、有机发光显示器、电子纸显示器等。
如图2所示为栅极驱动电路2的结构框图。栅极驱动电路2包括串联的多级栅极驱动电路单元，前一级栅极驱动电路单元的信号输出接口Vout耦合到后一级栅极驱动电路单元的信号输入接口Vin，首级驱动电路单元的输入信号由信号发生器提供，每一级驱动电路单元的信号输出接口Vout都连接着负载面板上相对应的一条栅极扫描线。
信号发生器还用于给各级栅极驱动电路单元提供低电平信号Vss。
时钟发生器给各级栅极驱动电路单元提供时钟信号。
如图3所示为栅极驱动电路单元的一种具体实施例的电路图。首先对一些术语进行说明。
晶体管可以为双极型晶体管或场效应晶体管。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一、二主电流导通极分别指双极型晶体管的集电极和发射极。当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一、二主电流导通极分别指场效应晶体管的漏极和源极。显示装置中的晶体管通常为薄膜晶体管(TFT)，此种情况下晶体管的控制极是指薄膜晶体管的栅极，第一、二主电流导通极分别指薄膜晶体管的漏极和源极。
下面以晶体管为TFT为例说明图3所示栅极驱动电路单元的结构和工作过程。
如图3所示的实施例中，栅极驱动电路单元包括: 信号输入接口Vin、信号输出接口Vout、输入信号控制模块111、第一时钟信号控制模块32、第三时钟信号控制模块33和第四时钟信号控制模块34。信号输入接口Vin用于接收输入脉冲信号。信号输出接口Vout用于输出驱动信号。第一时钟信号控制模块32包括驱动单元和时钟馈通抑制单元，所述驱动单元包括控制端，所述驱动单元的控制端接受驱动电压后，将第一时钟信号传送至所述信号输出接口；所述时钟馈通抑制单元用于在第一时钟信号的控制下将所述控制端耦合到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位。输入信号控制模块31用于从信号输入接口接收输入脉冲信号，给所述驱动单元的控制端提供驱动电压。第三时钟信号控制模块33用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位。第四时钟信号控制模块34用于在第四时钟信号的控制下，拉下所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。
图3示出了栅极驱动电路单元在一种实施例中的具体电路结构，输入信号控制模块31包括第一晶体管T1，所述第一晶体管T1的栅极和漏极接收输入信号Vin，所述第一晶体管T1的源极用于输出驱动电压信号；第一时钟信号控制模块32包括驱动单元和时钟馈通抑制单元，所述驱动单元包括第二晶体管T2，所述第二晶体管T2的栅极连接到所述第一晶体管T1的源极, 第二晶体管T2的栅极即为驱动单元的控制端，定义第一晶体管T1的源极和第二晶体管T2的栅极的连接节点为节点Q，所述第二晶体管T2的漏极输入第一时钟信号CLKA，所述第二晶体管T2的源极连接到所述信号输出接口Vout，用于在所述第二晶体管T2的栅极电压的控制下，当所述第一时钟信号CLKA的高电平到来时对所述信号输出接口充电，当所述第一时钟信号CLKA的低电平到来时拉下所述信号输出接口Vout的电位。时钟馈通抑制单元包括第五晶体管T5，所述第五晶体管T5的栅极响应第一时钟信号CLKA，其漏极连接到第二晶体管T2的栅极，源极连接到信号输出接口Vout，第五晶体管T5用于当信号输出为低电平时在第一时钟信号CLKA的高电平到来时将第二晶体管T2的栅极耦合到所述信号输出接口Vout,从而稳定第二晶体管T2的栅极电位。所述第三时钟信号控制模块33包括第三晶体管T3，所述第三晶体管T3的栅极响应第三时钟信号CLKC，第三晶体管T3的漏极连接到所述第二晶体管T2的栅极，第三晶体管T3的源极连接到第一电压源Vss，第一电压源Vss用于提供低电平，第三晶体管T3用于在所述第三时钟信号CLKC的高电平到来时将第二晶体管T2的栅极耦合到第一电压源Vss，从而拉低所述第二晶体管T2的栅极的电位。本实施例中，第四时钟信号控制模块34包括第四晶体管T4，所述第四晶体管T4的栅极响应第四时钟信号CLKD，漏极连接到所述信号输出接口Vout，源极连接到第一电压源Vss，第四晶体管T4用于在第四时钟信号CLKD的高电平到来时将输出接口Vout连接到第一电压源Vss，从而拉低所述信号输出接口Vout的电压。
本实施例中，栅极驱动电路单元的三个时钟信号满足以下条件：
第一时钟信号、第三时钟信号和第四时钟信号是三个周期相同的N相时钟信号。这三个时钟信号的占空比均为1/N, 每个相位的值等于2π/N。其中，N为大于或等于4的整数。第三时钟信号CLKC比第一时钟信号CLKA滞后两个相位，第四时钟信号CLKD比第一时钟信号CLKA超前一个相位。各时钟信号的高电平为Vdd，低电平为Vss。
如图4所示，栅极驱动电路的工作过程分为四个阶段：预充电阶段、上拉阶段、下拉阶段以及低电平维持阶段，下面详细说明这四个阶段。
（1）预充电阶段
在第二晶体管T2的漏极成为高电平之前，加在信号输入接口Vin的输入脉冲信号通过第一晶体管T1给节点Q充电，第二晶体管T2在参与给负载的充电之前被充分打开的过程称为预充电阶段。
预充电阶段，时钟信号CLKA、CLKC均为低电平，时钟信号CLKD为高电平，输入信号Vin为高电平，第一晶体管T1开启，节点Q的电位逐渐抬高。当节点Q的电位高于第二晶体管T2的阈值电压Vth的时候，第二晶体管T2被打开。因为时钟信号CLKA为低电平，所以输出信号Vout保持为低电位。此时，第三晶体管T3、第四晶体管T4和第五晶体管T5均处于关断状态。预充电结束时刻，节点Q的电位达到Vdd-Vth。
（2）上拉阶段
第二晶体管T2的漏极电压变成高电平，处于开启状态晶体管T2给负载端充电，并将信号输出接口Vout的电位最终上拉到Vdd的过程称为上拉阶段。
上拉阶段时，时钟信号CLKA变为高电平，时钟信号CLKC 和CLKD为低电平，输入信号Vin为低电平，第一晶体管T1关断，第三晶体管T3、第四晶体管T4也处于关断状态。因此，节点Q悬浮，第二晶体管T2保持为开启，时钟信号CLKA通过第二晶体管T2给负载提供充电电流。节点Q的电位随着输出接口Vout的充电而提高，这被称为自举。
在上拉阶段之初，第二晶体管T2工作于饱和导通的状态，第五晶体管T5也处于饱和导通的状态；当输出电压达到2Vth后，第二晶体管T2进入线性导通的状态；当输出电压达到Vdd-Vth后，第五晶体管T5被关断。
（3）下拉阶段
第二晶体管T2、第三晶体管T3和第四晶体管T4分别对输出接口Vout和节点Q放电，并且将节点Q和输出接口Vout的电位最终拉到Vss的过程，称为下拉阶段。
下拉阶段包含两个连续的过程，第一个过程是给输出接口Vout的放电。时钟信号CLKA、CLKC 和CLKD为低电平。因此，第一晶体管T1、第三晶体管T3、第四晶体管T4和第五晶体管T5均处于关断状态。此时，因为第二晶体管T2保持着开启的状态，而第二晶体管的漏极电平为Vss，所以信号输出接口Vout的电位通过第二晶体管T2管下拉到Vss。
下拉阶段的第二个过程是给节点Q的放电。时钟信号CLKC成为高电平，时钟信号CLKA和CLKD为低电平。此时，第三晶体管T3开启，节点Q的存储电荷通过第三晶体管T3释放。因此，节点Q的电位降低。当节点Q的电位降低到Vth之下后，第二晶体管T2管关断。
节点Q上存储的电荷必须在时钟信号CLKC的高电平期间彻底释放，否则，第二晶体管T2仍然处于开启状态，从而信号输出接口Vout的低电平状态在第一时钟信号CLKA下一个周期的高电平作用下被破坏。
（4）低电平维持阶段
当输出接口的电位被拉低到Vss以后，该栅极驱动电路单元进入非选通状态。在此阶段，输出接口Vout的电位须稳定地维持于低电平Vss，故称该阶段为低电平维持阶段。
若在低电平维持阶段，栅极驱动电路的信号输出端口Vout出现噪声电压，则与之相连接的面板的行选择晶体管误开启，从而造成面板中图像信息的错误。
在低电平维持阶段，第一晶体管T1管处于关态，第二晶体管T2的栅极因电荷在时钟信号CLKC为高电平时的释放而变成低电平，因此输出信号Vout理应也维持在低电平。
但是，当时钟信号CLKA从低电平跳变到高电平时，由于第二晶体管T2的栅-漏寄生电容Cgd的连接，第二晶体管T2的栅电位VQ也相应增加。当VQ大于晶体管T2的阈值电压Vth的时候，晶体管T2开启，负载电容被充电，输出信号Vout出现噪声电压。这种情况下，需要采取一些措施维持输出信号Vout的低电平状态。
本实施例从防止输出驱动信号出现噪声电压和消除输出驱动信号上的噪声电压两方面解决该问题。
为防止输出驱动信号出现噪声电压，在本实施例中增加了第五晶体管T5。增加了第五晶体管T5后，第二晶体管T2的栅电位VQ的大小取决于第二晶体管T2的寄生电容Cgd与输出接口Vout的负载电容的大小之比。输出接口Vout的负载电容的值要远远大于节点Q的电容，因此VQ被显著减小，减少第二晶体管T2被开启的几率，从而降低噪声电压出现的可能性。
增加了第五晶体管T5之后，当时钟信号CLKA从低电平跳变到高电平时，由于第二晶体管T2的栅-漏寄生电容Cgd的耦合，节点Q出现高电平。此时，第五晶体管T5管在时钟信号CLKA的控制下打开，节点Q与输出接口Vout短接，节点Q上的耦合电荷通过第五晶体管T5释放到输出接口Vout，节点Q的电压下降，第二晶体管T2得以保持关断状态，同时输出信号Vout也得以维持于低电平状态。
增加了第五晶体管T5之后，当时钟信号CLKA从高电平跳变到低电平时，同样地，由于上拉的第二晶体管T2的栅-漏寄生电容Cgd的耦合，节点Q出现比Vss更低的一个低电平。此时，与节点Q连接着的第三晶体管T3和第五晶体管T5均处于关断状态，第二晶体管T2也处于关断的状态，因此，输出信号Vout仍然保持为低电平状态，直到时钟信号CLKC的高电平来临，第三晶体管T3管被开启，节点Q的电位得以恢复到Vss。
另一方面，为消除输出驱动信号中出现的噪声电压，本实施例中增加了第四晶体管T4。第四晶体管T4在时钟信号CLKD为高电平时打开，将信号输出接口连接到地，从而将信号输出接口Vout点的噪声电荷释放，避免信号输出接口Vout点长时间噪声电荷的累积，从而消除输出驱动信号中的噪声电压。而且时钟信号CLKD超前时钟信号CLKA一个相位，即时钟信号CLKD的下降沿和时钟信号CLKA的上升沿有一定的交叠，当时钟信号CLKA处于上升沿时，时钟信号CLKD处于下降沿，第四晶体管T4还没有完全关断，所以可减少信号输出接口Vout点的噪声电压。
另外，第三晶体管T3在时钟信号CLKC为高电平时打开，将节点Q连接到地，将Q点的噪声电荷释放，避免Q点的长时间噪声电荷的累积，保证第二晶体管T2在低电平维持阶段的可靠关断，防止第二晶体管T2将信号输出接口Vout点的电压上拉。
在另外的实施例中，时钟馈通抑制单元还包括存储电容Cs，所述存储电容Cs连接在所述第二晶体管T2的栅极和源极之间。通过增加存储电容Cs，可减少晶体管T2的寄生电容Cgd与节点Q的电容之比，因此增加存储电容Cs的值能够减少VQ，从而抑制输出接口Vout的噪声电压。但是，存储电容Cs也不宜太大，过大的存储电容Cs会导致过大的电路面积。
晶体管T5和存储电容Cs共同构成时钟馈通抑制单元，可以减少低电平维持阶段输出信号的噪声，使输出信号更加平稳。
由以上工作过程可知，与现有技术中需要10个以上的晶体管的两相时钟驱动的方案相比，本实施例的栅极驱动电路通过多相时钟的设计，采用极少数量的晶体管即完成了栅极驱动电路的功能，降低了电路设计的复杂程度，一方面减小了电路设计面积，降低了功耗，更适用于高品质的显示装置，另一方面提高了电路制造的成品率。
另外，栅极驱动电路的功耗主要是动态功耗，其与时钟的频率成正比，本实施例设计了三个时钟信号，采用大于或等于四相的时钟信号，减少时钟跳变的频率，从而减少了功耗。
本实施例从防止输出驱动信号出现噪声电压和消除输出驱动信号上的噪声电压两方面保持低电平维持阶段输出驱动信号的稳定性，既向像素阵列提供了稳定的驱动信号，又向下一级栅极驱动电路单元提供了稳定的输入信号，从而提高了整个栅极驱动电路的稳定性和显示装置的图像显示质量。
由于采用了多相时钟驱动，电路中承受电压应力的下拉晶体管的栅极电压信号的占空比较小，所以晶体管阈值电压漂移量少，电特性退化减小，电路稳定性好。从而栅极驱动电路的寿命被延长。
下面以栅极驱动电路采用的时钟相位为四、六和八为例进行说明。
为满足显示装置对栅极驱动信号的要求，当多级栅极驱动电路单元串接时，后一级栅极驱动电路单元的时钟信号比前一级栅极驱动电路单元的相对应的时钟信号要滞后一个相位。
当时钟信号的相数等于N的时候，第k*N+1级栅极驱动电路单元的时钟接口的接法与第1级栅极驱动电路单元相同，第k*N+2级栅极驱动电路单元的时钟接口的接法与第2级栅极驱动电路单元相同……第k*N+i级栅极驱动电路单元的时钟接口的接法与第i级栅极驱动电路单元相同。其中，k为大于或者等于1的整数，i为大于或者等于0并且小于或者等于N-1的整数。
如图5所示，时钟发生器提供的时钟信号为四相时钟信号,分别为CLK1、CLK2、CLK3和CLK4，脉冲占空比为25%，此时各级栅极驱动电路单元的时钟具体连接方式为：
第一级栅极驱动电路单元51的时钟接口CLKA接信号CLK1，时钟接口CLKC接信号CLK3，时钟接口CLKD接信号CLK4；第二级栅极驱动电路单元52的时钟接口CLKA接信号CLK2，时钟接口CLKC接信号CLK4，时钟接口CLKD接信号CLK1；第三级栅极驱动电路单元53的时钟接口CLKA接信号CLK3，时钟接口CLKC接信号CLK1，时钟接口CLKD接信号CLK2；第四级栅极驱动电路单元54的时钟接口CLKA接信号CLK4，时钟接口CLKC接信号CLK2，时钟接口CLKD接信号CLK3……
其余各级的接法：当级数被4除余1，则该栅极驱动电路单元的时钟接口的接法与第一级栅极驱动电路单元相同；如果级数被4除余2，则该栅极驱动电路单元的时钟接口的接法与第二级栅极驱动电路单元相同；如果级数被4除余3，则该栅极驱动电路单元的时钟接口的接法与第三级栅极驱动电路单元相同；如果级数被4整除，则该栅极驱动电路单元的时钟接口的接法与第四级栅极驱动电路单元相同。
采用四相时钟驱动时的工作信号图如图6所示，该栅极驱动电路在上述四相时钟信号和起始脉冲信号的作用下，为图1中所示的负载面板的各行提供驱动信号。
本实施例中，栅极驱动电路采用的六相时钟信号如图7所示，时钟发生器提供的时钟信号为六相时钟信号,分别为CLK1、CLK2、CLK3、CLK4、CLK5和CLK6，脉冲占空比为1/6，各级栅极驱动电路单元的时钟具体连接方式为：
第一级栅极驱动电路单元71的时钟接口CLKA接信号CLK1，时钟接口CLKC接信号CLK3，时钟接口CLKD接信号CLK4；第二级栅极驱动电路单元72的时钟接口CLKA接信号CLK2，时钟接口CLKC接信号CLK4，时钟接口CLKD接信号CLK5；第三级栅极驱动电路单元73的时钟接口CLKA接信号CLK3，时钟接口CLKC接信号CLK5，时钟接口CLKD接信号CLK6；第四级栅极驱动电路单元74的时钟接口CLKA接信号CLK4，时钟接口CLKC接信号CLK6，时钟接口CLKD接信号CLK1；第五级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK5，时钟接口CLKC接信号CLK1，时钟接口CLKD接信号CLK2；第六级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK6，时钟接口CLKC接信号CLK2，时钟接口CLKD接信号CLK3……
其余各级的接法：当级数被6除余1，则该栅极驱动电路单元的时钟接口的接法与第一级栅极驱动电路单元相同；如果级数被6除余2，则该栅极驱动电路单元的时钟接口的接法与第二级栅极驱动电路单元相同；如果级数被6除余3，则该栅极驱动电路单元的时钟接口的接法与第三级栅极驱动电路单元相同；如果级数被6除余4，则该栅极驱动电路单元的时钟接口的接法与第四级栅极驱动电路单元相同；如果级数被6除余5，则该栅极驱动电路单元的时钟接口的接法与第五级栅极驱动电路单元相同；如果级数被6整除，则该栅极驱动电路单元的时钟接口的接法与第六级栅极驱动电路单元相同。
采用六相时钟驱动时的工作信号图如图8所示，该栅极驱动电路在上述六相时钟信号和起始脉冲信号的作用下，为图1中所示的面板4的各行提供驱动信号。
本实施例中，栅极驱动电路采用的八相时钟信号如图9所示，时钟发生器提供的时钟信号为八相时钟信号,分别为CLK1、CLK2、CLK3、CLK4、CLK5、CLK6、CLK7和CLK8，脉冲占空比为1/8，各级栅极驱动电路单元的时钟具体连接方式为：
第一级栅极驱动电路单元91的时钟接口CLKA接信号CLK1，时钟接口CLKC接信号CLK3，时钟接口CLKD接信号CLK4；第二级栅极驱动电路单元92的时钟接口CLKA接信号CLK2，时钟接口CLKC接信号CLK4，时钟接口CLKD接信号CLK5；第三级栅极驱动电路单元93的时钟接口CLKA接信号CLK3，时钟接口CLKC接信号CLK5，时钟接口CLKD接信号CLK6；第四级栅极驱动电路单元94的时钟接口CLKA接信号CLK4，时钟接口CLKC接信号CLK6，时钟接口CLKD接信号CLK7；第五级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK5，时钟接口CLKC接信号CLK7，时钟接口CLKD接信号CLK8；第六级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK6，时钟接口CLKC接信号CLK8，时钟接口CLKD接信号CLK1；第七级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK7，时钟接口CLKC接信号CLK1，时钟接口CLKD接信号CLK2；第八级栅极驱动电路单元（图中未示出）的时钟接口CLKA接信号CLK8，时钟接口CLKC接信号CLK2，时钟接口CLKD接信号CLK3……
其余各级的接法：当级数被8除余1，则该栅极驱动电路单元的时钟接口的接法与第一级栅极驱动电路单元相同；如果级数被8除余2，则该栅极驱动电路单元的时钟接口的接法与第二级栅极驱动电路单元相同；如果级数被8除余3，则该栅极驱动电路单元的时钟接口的接法与第三级栅极驱动电路单元相同；如果级数被8除余4，则该栅极驱动电路单元的时钟接口的接法与第四级栅极驱动电路单元相同；如果级数被8除余5，则该栅极驱动电路单元的时钟接口的接法与第五级栅极驱动电路单元相同；如果级数被8除余6，则该栅极驱动电路单元的时钟接口的接法与第六级栅极驱动电路单元相同；如果级数被8除余7，则该栅极驱动电路单元的时钟接口的接法与第七级栅极驱动电路单元相同；如果级数被8整除，则该栅极驱动电路单元的时钟接口的接法与第八级栅极驱动电路单元相同。
采用八相时钟驱动时的工作的信号图如图10所示，该栅极驱动电路在上述八相时钟信号和起始脉冲信号的作用下，为图1中所示的面板4的各行提供驱动信号。
在另一种实施例中栅极驱动电路单元的电路结构如图11所示，栅极驱动电路单元包括信号输入接口Vin、信号输出接口Vout、输入信号控制模块111、第一时钟信号控制模块112、第二时钟信号控制模块115、第三时钟信号控制模块113和第四时钟信号控制模块114。信号输入接口Vin用于接收输入脉冲信号，如果本级栅极驱动电路单元是第一级，则输入脉冲信号由信号发生器提供，如果本级栅极驱动电路单元不是第一级，则输入脉冲信号由前一级栅极驱动电路单元提供，即本级栅极驱动电路单元的信号输入接口耦合到前一级栅极驱动电路单元的信号输出接口。信号输出接口Vout用于输出驱动信号分别至相对应的扫描线和下一级栅极驱动电路单元的信号输入接口。第一时钟信号控制模块112包括驱动单元和时钟馈通抑制单元，所述驱动单元包括用于输入驱动电压的控制端，所述驱动单元在被所述驱动电压开启后，在第一时钟信号的控制下，输出驱动信号至所述信号输出接口Vout；所述时钟馈通抑制单元用于在第一时钟信号的控制下将所述控制端连接到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位。输入信号控制模块111用于从信号输入接口接收输入脉冲信号，并在输入脉冲信号的控制下，给所述驱动单元的控制端提供驱动电压。第二时钟信号控制模块115用于在第二时钟信号的控制下拉下所述信号输出接口的电压，所述第二时钟信号比第一时钟信号滞后一个相位。第三时钟信号控制模块113用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位。第四时钟信号控制模块114用于在第四时钟信号的控制下，拉下所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。本实施例在上述实施例的基础上增加了第二时钟信号控制模块，具有四个时钟信号，第一时钟信号CLKA、第二时钟信号CLKB、第三时钟信号CLKC和第四时钟信号CLKD的工作周期相同的N相时钟信号，其中，N为大于或等于4的整数。其中第二时钟信号CLKB比第一时钟信号CLKA滞后一个相位，第三时钟信号CLKC比第一时钟信号CLKA滞后两个相位，第四时钟信号CLKD比第一时钟信号CLKA超前一个相位。
如图11示出了栅极驱动电路单元在另一种实施例中的具体电路结构，与图3所示实施例不同的是增加了第二时钟信号控制模块115，在一种具体实例中，第二时钟信号控制模块115包括第六晶体管T6，第六晶体管T6的栅极响应第二时钟信号CLKB，其漏极连接到信号输出接口Vout，源极连接到第一电压源Vss，用于在所述第二时钟信号CLKB的高电平到来时将所述信号输出接口Vout的电位下拉到Vss。
在下拉阶段，第二晶体管T2将信号输出接口Vout的电压下拉到第一时钟信号CLKA的低电平。同时，当第二时钟信号CLKB的高电平到来时，第六晶体管T6开启，将信号输出接口Vout连接到电压源Vss，在第二晶体管T2和第六晶体管T6的同时下拉下，使信号输出接口Vout的电压迅速下拉到低电平，从而使输出驱动信号的下降沿时间更短，对像素阵列的驱动效果更好。
另外，第六晶体管T6增加了一条给输出接口Vout的放电通路，保证输出接口Vout在低电平维持阶段没有噪声电压的积累，有助于提高输出信号Vout的低电平稳定能力。
本实施例工作时的信号图如图12所示。时钟信号CLKA 、CLKB、CLKC和CLKD的高电位均为Vdd，低电位均为Vss，占空比为25%。该电路的输入信号Vin是上一级栅驱动电路单元的输出信号。本级的栅驱动电路单元的输出信号是Vout。本实施例的栅极驱动电路单元和上述实施例栅极驱动电路单元的基本工作原理相同，其工作过程也包含预充电阶段、上拉阶段、下拉阶段和低电平维持阶段，在此不在赘述。
为满足显示装置对栅极驱动信号的要求，当多级栅极驱动电路单元串接，且分别与N相时钟信号相连时，后一级栅极驱动电路单元的时钟信号比前一级栅极驱动电路单元的相对应的时钟信号滞后一个相位。
如图13中所示，时钟发生器提供的时钟信号为四相时钟信号,其分别为CLK1、CLK2、CLK3和CLK4，脉冲占空比为25%，各级栅极驱动电路单元的时钟具体连接方式为：
第一级栅极驱动电路单元131的时钟接口CLKA接信号CLK1，时钟接口CLKB接信号CLK2，时钟接口CLKC接信号CLK3，时钟接口CLKD接信号CLK4；第二级栅极驱动电路单元132的时钟接口CLKA接信号CLK2，时钟接口CLKB接信号CLK3，时钟接口CLKC接信号CLK4，时钟接口CLKD接信号CLK1；第三级栅极驱动电路单元133的时钟接口CLKA接信号CLK3，时钟接口CLKB接信号CLK4，时钟接口CLKC接信号CLK1，时钟接口CLKD接信号CLK2；第四级栅极驱动电路单元134的时钟接口CLKA接信号CLK4，时钟接口CLKB接信号CLK1，时钟接口CLKC接信号CLK2，时钟接口CLKD接信号CLK3。
其余各级的接法：当级数被4除余1，则该栅极驱动电路单元的时钟接口的接法与第一级的相同；如果级数被4除余2，则该栅极驱动电路单元的时钟接口的接法与第二级的相同；如果级数被4除余3，则该栅极驱动电路单元的时钟接口的接法与第三级的相同；如果级数被4整除，则该栅极驱动电路单元的时钟接口的接法与第四级的相同。
本实施例采用四相时钟驱动时的信号图如图14所示。
当时钟发生器提供的时钟信号的相位大于四时，各级栅极驱动电路单元的时钟接口的接法需要满足时钟接口CLKA、CLKB、CLKC和CLKD的相位要求，其具体接法和不同时钟驱动时的信号图见图15-图16。
本实施例采用六相时钟驱动时的电路图如图15所示。
本实施例采用六相时钟驱动时的信号图如图16所示。
另外，输入信号控制模块、驱动单元、第三时钟信号控制模块、第二时钟信号控制模块、第四时钟信号控制模块和时钟馈通抑制单元除了采用上述实施例中的单晶体管外，在另外的实施例中，它们中的至少一个还可以采用多个晶体管，通过连接以完成该模块的功能。
综上所述，本发明具有以下优点：
其一，在该栅极驱动电路中，输出电位的上拉和下拉由同一个晶体管来完成。两相时钟情况下，上拉和下拉分别由两个不同的晶体管来完成。所以本电路占用的版图面积较小。
其二，常规的集成栅极驱动电路设计中均需要用到下一级栅极驱动电路的输出信号给本级下拉。而该电路不需要用到下一级栅极驱动电路的输出信号，这一方面减少了下一级单元电路的负载量，另一方面减少了下一级单元电路上拉延迟带来的本级下拉延迟时间的增加。
其三，本发明构成栅极驱动电路单元的晶体管数目仅为5个或者6个。而在常规的两相时钟驱动的情况下，通常需要10个以上的晶体管。所以根据本发明的栅极驱动电路需要的晶体管数量少，其电路简单、占用面积少，并且其制造成品率更高。
其四，根据本发明的栅极驱动电路中下拉晶体管所承受电压应力相比于常规电路更小，故本电路中的晶体管阈值电压漂移量少，电特性退化减少，从而该栅极驱动电路具有更好的稳定性。
其五，该栅极驱动电路采用多相时钟控制，因此其功耗比常规的两相时钟控制的栅极驱动电路的功耗更少。
在本发明中，栅极驱动电路可由非晶硅薄膜晶体管构成，并且可被集成在显示装置的面板上，与像素阵列一起完成。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，但这只是为便于理解而举的实例，不应认为本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，可以做出各种可能的等同改变或替换，这些改变或替换都应属于本发明的保护范围。

Claims (12)

  1. 一种栅极驱动电路单元，其特征在于包括：
    信号输入接口，用于接收输入脉冲信号；
    信号输出接口，用于输出驱动信号；
    第一时钟信号控制模块，包括驱动单元和时钟馈通抑制单元，所述驱动单元包括控制端，所述驱动单元的控制端获得驱动电压后，将第一时钟信号传送至所述信号输出接口；所述时钟馈通抑制单元在第一时钟信号的控制下将所述控制端耦合到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位；
    输入信号控制模块，用于从信号输入接口接收输入脉冲信号，给所述驱动单元的控制端提供驱动电压；
    第三时钟信号控制模块，用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位；
    第四时钟信号控制模块，用于在第四时钟信号的控制下，下拉所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。
  2. 如权利要求1所述的栅极驱动电路单元，其特征在于，所述第一时钟信号、第三时钟信号和第四时钟信号是三个周期相同的N相时钟信号，其中，N为大于或等于4的整数；所述一个相位的值等于2π/N。
  3. 如权利要求1或2所述的栅极驱动电路单元，其特征在于，所述输入信号控制模块的输出端耦合到所述驱动单元的控制端，用于在输入脉冲信号的控制下，给所述驱动单元的控制端充电；所述第三时钟信号控制模块的第一端用于响应第三时钟信号，第二端耦合到所述驱动单元的控制端，第三端耦合到第一电压源，所述第三时钟信号控制模块在第三时钟信号的控制下拉低所述驱动单元的控制端的电压。
  4. 如权利要求3所述的栅极驱动电路单元，其特征在于，所述输入信号控制模块包括第一晶体管，所述第一晶体管的控制极和第一主电流导通极接收输入信号，所述第一晶体管的第二主电流导通极用于提供驱动电压；所述驱动单元包括第二晶体管，所述第二晶体管的控制极耦合到所述第一晶体管的第二主电流导通极，所述第二晶体管的第一主电流导通极输入第一时钟信号，所述第二晶体管的第二主电流导通极耦合到所述信号输出接口，用于在被所述驱动电压开启后，当所述第一时钟信号的高电平到来时对所述信号输出接口充电，当所述第一时钟信号的低电平到来时拉下所述信号输出接口的电位；所述时钟馈通抑制单元包括第五晶体管，所述第五晶体管的控制极响应第一时钟信号，其第一主电流导通极耦合到所述第二晶体管的控制极，第二主电流导通极耦合到所述信号输出接口，用于在第一时钟信号的高电平到来时将所述第二晶体管的控制极耦合到所述信号输出接口；所述第三时钟信号控制模块包括第三晶体管，所述第三晶体管的控制极响应第三时钟信号，第三晶体管的第一主电流导通极耦合到所述第二晶体管的控制极，第三晶体管的第二主电流导通极耦合到第一电压源，用于在所述第三时钟信号的高电平到来时将所述第二晶体管的控制极的电位下拉到第一电压源的电压；所述第四时钟信号控制模块包括第四晶体管，所述第四晶体管的控制极响应第四时钟信号，其第一主电流导通极耦合到所述信号输出接口，第二主电流导通极耦合到第一电压源，用于在第四时钟信号的高电平到来时将所述信号输出接口的电压下拉到第一电压源的电压。
  5. 如权利要求4所述的栅极驱动电路单元，其特征在于，所述时钟馈通抑制单元还包括存储电容，所述存储电容连接在所述第二晶体管的控制极和第二主电流导通极之间。
  6. 一种栅极驱动电路单元，其特征在于包括：
    信号输入接口，用于接收输入脉冲信号；
    信号输出接口，用于输出驱动信号；
    第一时钟信号控制模块，包括驱动单元和时钟馈通抑制单元，所述驱动单元包括控制端，所述驱动单元的控制端获得驱动电压后，将第一时钟信号传送至所述信号输出接口；所述时钟馈通抑制单元用于在第一时钟信号的控制下将所述控制端耦合到所述信号输出接口；所述第一时钟信号比所述输入脉冲信号滞后一个相位；
    输入信号控制模块，用于从信号输入接口接收输入脉冲信号，并在输入脉冲信号的控制下，给所述驱动单元的控制端提供驱动电压；
    第二时钟信号控制模块，用于在第二时钟信号的控制下拉下所述信号输出接口的电压，所述第二时钟信号比第一时钟信号滞后一个相位;
    第三时钟信号控制模块，用于在第三时钟信号的控制下给所述驱动单元的控制端提供关闭电压，所述第三时钟信号比第一时钟信号滞后两个相位；
    第四时钟信号控制模块，用于在第四时钟信号的控制下，拉下所述信号输出接口的电压，所述第四时钟信号比第一时钟信号超前一个相位。
  7. 如权利要求5所述的栅极驱动电路单元，其特征在于，所述第一时钟信号、第二时钟信号、第三时钟信号和第四时钟信号是四个周期相同的M相时钟信号，其中，M为大于或等于4的整数；所述一个相位的值等于2π/M。
  8. 如权利要求6或7所述的栅极驱动电路单元，其特征在于，所述输入信号控制模块的输出端耦合到所述驱动单元的控制端，用于在输入脉冲信号的控制下，给所述驱动单元的控制端充电；所述第三时钟信号控制模块的第一端用于响应第三时钟信号，第二端耦合到所述驱动单元的控制端，第三端耦合到第一电压源，所述第三时钟信号控制模块在第三时钟信号的控制下拉低所述驱动单元的控制端的电压。
  9. 如权利要求8所述的栅极驱动电路单元，其特征在于，所述输入信号控制模块包括第一晶体管，所述第一晶体管的控制极和第一主电流导通极接收输入信号，所述第一晶体管的第二主电流导通极用于提供驱动电压；所述驱动单元包括第二晶体管，所述第二晶体管的控制极耦合到所述第一晶体管的第二主电流导通极，所述第二晶体管的第一主电流导通极输入第一时钟信号，所述第二晶体管的第二主电流导通极耦合到所述信号输出接口，用于在被所述驱动电压开启后，当所述第一时钟信号的高电平到来时对所述信号输出接口充电，当所述第一时钟信号的低电平到来时拉下所述信号输出接口的电位；所述时钟馈通抑制单元包括第五晶体管，所述第五晶体管的控制极响应第一时钟信号，其第一主电流导通极耦合到所述第二晶体管的控制极，第二主电流导通极耦合到所述信号输出接口，用于在第一时钟信号的高电平到来时将所述第二晶体管的控制极耦合到所述信号输出接口；所述第二时钟信号控制模块包括第六晶体管，所述第六晶体管的控制极响应第二时钟信号，其第一主电流导通极耦合到信号输出接口，第二主电流导通极耦合到第一电压源，用于在所述第二时钟信号的高电平到来时将所述信号输出接口的电位下拉到第一电压源的电压；所述第三时钟信号控制模块包括第三晶体管，所述第三晶体管的控制极响应第三时钟信号，第三晶体管的第一主电流导通极耦合到所述第二晶体管的控制极，第三晶体管的第二主电流导通极耦合到第一电压源，用于在所述第三时钟信号的高电平到来时将所述第二晶体管的控制极的电位下拉到第一电压源的电压；所述第四时钟信号控制模块包括第四晶体管，所述第四晶体管的控制极响应第四时钟信号，其第一主电流导通极耦合到所述信号输出接口，第二主电流导通极耦合到第一电压源，用于在第四时钟信号的高电平到来时将所述信号输出接口的电压下拉到第一电压源的电压。
  10. 如权利要求9所述的栅极驱动电路单元，其特征在于，所述时钟馈通抑制单元还包括存储电容，所述存储电容连接在所述第二晶体管的控制极和第二主电流导通极之间。
  11. 一种栅极驱动电路，包括多级串接的栅极驱动电路单元，前一级栅极驱动电路单元的信号输出接口耦合到后一级栅极驱动电路单元的信号输入接口，其特征在于，至少一个栅极驱动电路单元为权利要求1至权利要求10中任一项所述的栅极驱动电路单元，且后一级栅极驱动电路单元的时钟信号比前一级栅极驱动电路单元的相应的时钟信号滞后一个相位。
  12. 一种显示装置，包括：面板，所述面板包括由多个像素构成的二维像素阵列，以及与每个像素阵列相连的第一方向的多条数据线和第二方向的多条栅极扫描线；数据驱动电路，用于给所述数据线提供图像信号；其特征在于还包括：如权利要求11所述的栅极驱动电路，用于给所述栅极扫描线提供驱动信号。
PCT/CN2011/070658 2010-02-08 2011-01-26 栅极驱动电路单元、栅极驱动电路及显示装置 Ceased WO2011095099A1 (zh)

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