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WO2010118101A1 - Modulation de diffusion de dopant dans des couches tampons gan - Google Patents

Modulation de diffusion de dopant dans des couches tampons gan Download PDF

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Publication number
WO2010118101A1
WO2010118101A1 PCT/US2010/030194 US2010030194W WO2010118101A1 WO 2010118101 A1 WO2010118101 A1 WO 2010118101A1 US 2010030194 W US2010030194 W US 2010030194W WO 2010118101 A1 WO2010118101 A1 WO 2010118101A1
Authority
WO
WIPO (PCT)
Prior art keywords
gan
layer
layers
growth
dopant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2010/030194
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English (en)
Inventor
Robert Beach
Guang Yuan Zhao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Efficient Power Conversion Corp
Original Assignee
Efficient Power Conversion Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Efficient Power Conversion Corp filed Critical Efficient Power Conversion Corp
Priority to HK12106290.0A priority Critical patent/HK1165614B/xx
Priority to JP2012504808A priority patent/JP5670427B2/ja
Priority to CN201080014928.5A priority patent/CN102365763B/zh
Priority to DE112010001557T priority patent/DE112010001557T5/de
Publication of WO2010118101A1 publication Critical patent/WO2010118101A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H10P14/3444—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
    • H10P14/24—
    • H10P14/2901—
    • H10P14/3202—
    • H10P14/3216—
    • H10P14/3416—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor

Definitions

  • the present invention relates to the field of gallium nitride (GaN) transistors.
  • the invention relates to a method and apparatus to trap excess dopants.
  • Gallium nitride (GaN) semiconductor devices are increasingly desirable for power semiconductor devices because of their ability to carry large current and support high voltages. Development of these devices has generally been aimed at high power/high frequency applications. Devices fabricated for these types of applications are based on general device structures that exhibit high electron mobility and are referred to variously as heteroj unction field effect transistors (HFET), high electron mobility transistors (HEMT), or modulation doped field effect transistors (MODFET). These types of devices can typically withstand high voltages, e.g., 100 Volts, while operating at high frequencies, e.g., 100 kHz- 10 GHz.
  • HFET heteroj unction field effect transistors
  • HEMT high electron mobility transistors
  • MODFET modulation doped field effect transistors
  • a GaN HEMT device includes a nitride semiconductor with at least two nitride layers. Different materials formed on the semiconductor or on a buffer layer causes the layers to have different band gaps. The different material in the adjacent nitride layers also causes polarization, which contributes to a conductive two dimensional electron gas (2DEG) region near the junction of the two layers, specifically in the layer with the narrower band gap.
  • 2DEG conductive two dimensional electron gas
  • the nitride layers that cause polarization typically include a barrier layer of AlGaN adjacent to a layer of GaN to include the 2DEG, which allows charge to flow through the device. This barrier layer may be doped or undoped. Because of the 2DEG region existing under the gate at zero gate bias, most nitride devices are normally on, or depletion mode devices. If the 2DEG region is depleted, i.e. removed, below the gate at zero applied gate bias, the device can be an enhancement mode device. Enhancement mode devices are normally off and are desirable because of the added safety they provide. An enhancement mode device requires a positive bias applied at the gate in order to conduct current.
  • FIG. 1 illustrates a conventional GaN transistor device 100.
  • Device 100 includes substrate 11 composed of silicon (Si), silicon carbide (SiC), sapphire, or other material, transition layers 12 typically composed of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) that is about 0.1 to about 1.0 ⁇ m in thickness, Mg doped GaN layer 10, buffer layer 13 typically composed of GaN that is about 0.5 to about 3 ⁇ m in thickness, current conducting region 14 composed of GaN or indium gallium nitride (InGaN) typically about 0.01 to about 0.5 ⁇ m in thickness, contact region 15 typically composed of AlGaN, Al and titanium (Ti) that may have Si, typically about 0.01 to about 0.03 ⁇ m in thickness, barrier layer 16 typically composed of AlGaN where the Al to Ga ratio is about 0.1 to about 0.5 with a thickness of about 0.01 to about 0.03 ⁇ m, gate structure 17 composed of a nickel (Ni) and gold (A
  • Mg doped GaN material in a conventional GaN transistor device (e.g., FIG. 1), magnesium (Mg) is added to the growth environment. This Mg accumulates on the surface of the GaN and becomes part of the crystal. In addition, Mg coats the walls of the growth chamber during this part of the growth. Growth of undoped GaN, with the intention of having material without Mg present, following the growth of Mg doped material is difficult due to the presence of Mg still residing on the surface of the GaN and other Mg on the walls of the chamber. This residual Mg will continue to contaminate the crystal for extended lengths of time as Mg moves easily about the growth chamber.
  • FIG. 1 illustrates a cross-sectional view of a conventional GaN transistor device.
  • FIG. 2 illustrates a cross-sectional view of an enhancement mode GaN transistor device formed according to a first embodiment of the present invention.
  • FIG. 3 is a graph of Mg concentration in a buffer layer for single and multiple row interrupts in comparison to non-interrupted or standard growth.
  • FIG. 4 illustrates a cross-sectional view of an enhancement mode GaN transistor device formed according to a second embodiment of the present invention.
  • the present invention is a GaN transistor device with a Mg growth interruption layer to trap excess or residual dopants, and a method for making such a device.
  • the invention is designed to force reaction of Mg with nitrogen, for example, to form a less volatile material, i.e., magnesium nitride. This material is then covered by a layer of either GaN or AlGaN.
  • the coating step can be done at lower temperatures as well to assist the coating. By lowering the temperature, less reaction between the MgN and Al or Ga will occur.
  • the reaction of Al and MgN is such that AlN is formed and MgN is reduced to Mg. This reaction is in competition with the desired coating and entrapment of MgN. Thus, Mg will more readily remain in the MgN form if the reaction can be suppressed by reducing the temperature.
  • FIG. 2 illustrates a cross-sectional view of the device 200.
  • Device 200 includes, from bottom up, substrate 31 , transition layers 32, Mg doped layer 33, growth interrupt layers 39, buffer layer 34, barrier layer 35, ohmic contact metals 36, 37, and gate structure 38.
  • the growth interrupt layers (Mg diffusion barrier) 39 may be composed of one or more layers of highly Mg doped GaN. They are formed by interruption of growth and exposing the surface to ammonia.
  • Other suitable dopants beside Mg may be used, including iron (Fe), nickel (Ni), manganese (Mn), calcium (Ca), vanadium (V), or other transition metals.
  • the transition layers 32 are formed by nucleation and growth on the substrate 31.
  • Substrate 31 may be composed of silicon (Si), silicon carbide (SiC), sapphire, lithium gallium oxide (LiGaO 2 ), gallium nitride (GaN), or other suitable material.
  • Transition layers 32 may be composed of AlN, AlGaN, InAlGaN, SiO 2 , SiN, MgO, Al 2 O 3 , or combinations of these, preferably about 0.1 to about 1.0 ⁇ m in thickness.
  • the transition layers 32 are typically less than about 1000 A in thickness.
  • the Mg doped layer 33 is grown.
  • the Mg doped layer 33 may be composed of GaN that is about 0.1 to about 1. 0 ⁇ m in thickness with a Mg concentration between 10 16 atoms per cm 3 and 10 19 atoms per cm 3 .
  • the Mg blocking growth interrupt layers 39 are grown.
  • the formation of the growth interrupt layers 39 consists of growing GaN without Mg- containing material, stopping a supply of Ga-containing materials while maintaining a supply of ammonia or other activated nitrogen source (e.g., plasma N 2 ) to form a layer of magnesium nitride, beginning a supply of Ga to seal in the magnesium nitride layer by growing a layer of GaN, and interrupting growth again and repeating the above sequence until a target level of Mg in the final layer is reached.
  • ammonia or other activated nitrogen source e.g., plasma N 2
  • Buffer layer 34 may be composed of GaN, preferably with a thickness of about 0.5 to about 3.0 ⁇ m.
  • Barrier layer 35 may be composed of AlGaN where the Al fraction is about 0.1 to about 0.5, preferably with a thickness between about 0.01 and about 0.03 ⁇ m.
  • the Al fraction is the content of Al such that Al fraction plus Ga fraction equals 1.
  • Gate structure 38 may be composed of p-type GaN with a refractory metal contact such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), tungsten (W), or tungsten suicide (WSi 2 ).
  • the gate structure can be simple metal, such as Ni under Au, or a semiconductor with metal such as GaN under TiN, or a semiconductor under insulator under metal such as GaN under SiN under TiN.
  • Other semiconductors could be Si, GaAs, or InAlGaN.
  • Other insulators could be AlGaN, InAlGaN, SiO 2 , SiN, MgO, Al 2 O 3 .
  • Other metals could be Al, Ni, Au, Pt, etc.
  • polysilicon could be used.
  • the metal and gate layer are each preferably about 0.01 to about 1.0 ⁇ m in thickness. Total thickness for the gate structure would preferably be under 1 ⁇ m.
  • Ohmic contact metals 36, 37 may be composed of titanium (Ti) and aluminum (Al) with a capping metal such as nickel (Ni) and gold (Au) or titanium (Ti) and titanium nitride (TiN). There can also be an implanted highly doped region associate d with the contact region.
  • the primary channel region can be n-type doped GaN, or undoped or intrinsic InAlGaN.
  • the addition of a p-type GaN layer 33 below the gate and a series of growth interrupt layers 39 reduces the level of Mg in the GaN buffer layer 34.
  • the Mg doping of layer 33, in FIG. 2 increases the breakdown voltage of the device.
  • the gate length of the device can be greatly reduced without reducing the breakdown voltage of the device.
  • Gate capacitance of the device is reduced due to smaller gate length. Switching speed of the device is improved due to smaller gate capacitance.
  • Growth interrupt layers 39 reduce Mg concentration in layer 34 and near the barrier layer 35.
  • FIG. 3 is a graph comparing the Mg concentration in a buffer layer without growth interrupt layers, a buffer layer with a single growth interrupt layer, and a buffer layer with six growth interrupt layers.
  • each growth interrupt produces a higher level of Mg at the position of the interrupt, followed by a lower level of Mg in the following layer.
  • Each growth interrupt layer decreases the Mg, and by application of multiple layers, a low level of Mg can be obtained in a smaller distance.
  • Reduced Mg in layer 34 increases device conductivity. Reduced Mg in layer 34 also allows placement of layer 33 in close proximity to layer 35 without reduction in device conductivity. In addition, close proximity of layer 33 to 35 results in improved device breakdown and lower gate leakage currents.
  • the structure of FIG. 2, however, has some drawbacks. The time required to produce growth interrupt layers 39 can be large, leading to increased cost of fabrication. Additionally, some Mg is still present in layer 34 due to contamination from reactor parts.
  • FIG. 4 illustrates a cross-sectional view of the device 300 formed by the method described below.
  • This embodiment of the invention differs from the first embodiment in that the growth interrupt layers 39 of FIG. 2 are now replaced by AlGaN layers 49.
  • the AlGaN layers (doped diffusion barrier) 49 may be composed of one or more layers of AlGaN. They are formed by interruption of growth and exposing the GaN surface to ammonia, similar to the first embodiment, followed by deposition of AlGaN and then GaN.
  • the Al fraction of the AlGaN layers is between about 0.3 and about 1.
  • the thickness of the AlGaN layers is preferably about 0.005 to about 0.03 ⁇ m.
  • Formation of the structure of FIG. 4 is similar to that described above with respect to the first embodiment (FIG. 2), with Mg as the dopant, as an example.
  • the dimensions and compositions of the various layers are similar to that of the first embodiment as well.
  • growth interrupt layers 39 instead of forming growth interrupt layers 39 (FIG. T), AlGaN layers 49 are formed.
  • AlGaN layers 49 consists of growing GaN without Mg-containing material, stopping a supply of Ga-containing materials while maintaining a supply of ammonia or other activated nitrogen source (e.g., plasma N 2 ) to form a layer of magnesium nitride, reducing growth temperature, beginning a supply of Al and/or Ga to seal in the magnesium nitride layer by growing a layer of GaN, returning growth temperature to the initial temperature to grow GaN 3 and interrupting growth again and repeating the above sequence until a target level of Mg in the final layer is reached.
  • the step of reducing the growth temperature and returning to the initial growth temperature is optional.
  • the addition of a p-type GaN layer 43 below the gate and a series of growth interrupt and AlGaN layers 49 reduce the level of Mg in the GaN buffer layer 44.
  • the second embodiment shares the same advantages of the first embodiment.
  • the addition of the AlGaN layers to the diffusion barrier 49 improves the efficiency of each growth interrupt step, reducing the number of steps to achieve a desired level of Mg doping in the buffer layer 44.

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  • Junction Field-Effect Transistors (AREA)

Abstract

L'invention porte sur un cristal semi-conducteur et sur son procédé de formation. Le procédé consiste à fournir un flux de gaz contenant un dopant et un élément de la colonne III, puis arrêter le flux de gaz contenant un dopant et un élément de la colonne III, réduire la température, redémarrer le flux de gaz contenant un élément de la colonne III et élever ensuite la température.
PCT/US2010/030194 2009-04-08 2010-04-07 Modulation de diffusion de dopant dans des couches tampons gan Ceased WO2010118101A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
HK12106290.0A HK1165614B (en) 2009-04-08 2010-04-07 Dopant diffusion modulation in gan buffer layers
JP2012504808A JP5670427B2 (ja) 2009-04-08 2010-04-07 ＧａＮバッファ層におけるドーパント拡散変調
CN201080014928.5A CN102365763B (zh) 2009-04-08 2010-04-07 GaN缓冲层中的掺杂剂扩散调制
DE112010001557T DE112010001557T5 (de) 2009-04-08 2010-04-07 Dotierungsdiffusionsverfahren an GaN-Pufferschichten

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16782009P 2009-04-08 2009-04-08
US61/167,820 2009-04-08

Publications (1)

Publication Number Publication Date
WO2010118101A1 true WO2010118101A1 (fr) 2010-10-14

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PCT/US2010/030194 Ceased WO2010118101A1 (fr) 2009-04-08 2010-04-07 Modulation de diffusion de dopant dans des couches tampons gan

Country Status (7)

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US (1) US8431960B2 (fr)
JP (1) JP5670427B2 (fr)
KR (1) KR101620987B1 (fr)
CN (1) CN102365763B (fr)
DE (1) DE112010001557T5 (fr)
TW (1) TWI409859B (fr)
WO (1) WO2010118101A1 (fr)

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US8431960B2 (en) 2013-04-30
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US20100258912A1 (en) 2010-10-14
KR20120002985A (ko) 2012-01-09
TW201103077A (en) 2011-01-16
HK1165614A1 (en) 2012-10-05
DE112010001557T5 (de) 2012-09-13
TWI409859B (zh) 2013-09-21
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KR101620987B1 (ko) 2016-05-13
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