HK1142996B - Cascode circuit employing a depletion-mode, gan-based fet - Google Patents

Description

Cascode circuit using depletion mode GaN-based FETs

Cross Reference to Related Applications

This application is related to co-pending U.S. patent application Ser. No.11/725,823 entitled "Termination and Contact Structures For A High Voltage GaN-based heterojunction Transistor" filed on the same day as the same, and the contents of which are incorporated herein by reference.

This application is also related to co-pending U.S. patent application Ser. No.11/725,820 entitled "High-Voltage GaN-Based Transistor Structure and method of Forming Same", filed on even date herewith, and the contents of which are incorporated herein by reference.

Technical Field

The present invention relates generally to group III nitride compound semiconductor FETs such as GaN-based FETs, and more particularly to circuits employing depletion-mode GaN-based FETs and serving as enhancement-mode FETs.

Background

GaN-based FETs using wide bandgap semiconductors such as GaN, AlGaN, InGaN, AlGaN, AlInGaN have been attracting attention as power devices for high power applications because their on-resistance is one or more orders of magnitude smaller than FETs using Si or GaAs, and thus can operate at higher temperatures with larger currents and can withstand high voltage applications.

An example of a conventional GaN-based FET is shown in fig. 1. As shown, a heterojunction structure is formed on a semi-insulating substrate 91 such as a sapphire substrate. The heterojunction structure comprises a GaN buffer layer 92, for example, an undoped GaN layer 93 and an undoped AlGaN layer 94, wherein the undoped AlGaN layer 94 is typically much thinner than the undoped GaN layer 93. The undoped GaN layer 93 serves as a channel layer. Optionally, two n-AlGaN contact layers 95 are provided on the undoped AlGaN layer 94. The source electrode S and the drain electrode D are disposed on their respective contact layers 95. The gate electrode G is formed on the undoped AlGaN layer 94, and is located between the source electrode S and the drain electrode D. The contact layer 95 may not be necessary if satisfactory ohmic contact can be established between the source and drain electrodes S and D and the underlying semiconductor layer.

GaN-based FET devices are able to maximize electron mobility by forming quantum wells at the heterojunction interface between an AlGaN layer with a large bandgap and a GaN layer with a narrower bandgap. As a result, charge is trapped in the quantum well. The trapped electrons are represented by the two-dimensional electron gas 96 in the undoped GaN layer. The amount of current is controlled by applying a voltage to a gate electrode, which is in schottky contact with the semiconductor, so that electrons flow along a channel between the source and drain electrodes.

Even when the gate voltage is 0, electrons will be generated in the channel because a piezoelectric field extending from the substrate toward the device surface is formed. Thus, the GaN-based FET functions as a depletion mode (i.e., normally-on) device. It is desirable to provide enhancement mode (i.e., normally off) GaN-based FETs for a variety of reasons. For example, when a depletion mode FET is employed as the switching device for the power source, a bias voltage at least equal to the gate threshold must be continuously applied to the gate electrode to keep the switch in the off state. Such an arrangement may consume excessive power. On the other hand, if an enhancement mode FET is employed, the switch can be kept in an off state even in the case where no voltage is applied, and thus less power is consumed. Unfortunately, although attempts have been made to fabricate GaN-based enhancement mode FETs, they are generally unsatisfactory due to problems such as poor on-state conductance and breakdown voltage difference.

Disclosure of Invention

According to the present invention, a circuit includes an input drain node, an input source node, and an input gate node. The circuit also includes a group III-nitride depletion mode FET having a source, a drain, and a gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit includes an enhancement mode FET having a source, a drain, and a gate. The source of the depletion mode FET is coupled in series to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as an input drain node, the source of the enhancement mode FET serves as an input source node, and the gate of the enhancement mode FET serves as an input gate node.

According to one aspect of the invention, the group III nitride may include GaN.

According to another aspect of the invention, the depletion mode FET may be a high voltage FET having a voltage rating greater than about 100V.

According to another aspect of the present invention, a group III-nitride depletion mode FET may include: a substrate; a first active layer disposed over the substrate; and a second active layer disposed on the first active layer. The second active layer has a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer. A flash layer is disposed on the second active layer, and a source contact, a gate contact, and a drain contact are disposed on the flash layer.

According to another aspect of the present invention, the first active layer may include GaN, and the second active layer may include a group III nitride semiconductor material.

According to an aspect of the present invention, the second active layer may include Al_xGa_1-xN, wherein X is more than 0 and less than 1.

According to another aspect of the present invention, the second active layer may be selected from the group consisting of AlGaN, AlInN, and AlInGaN.

According to another aspect of the present invention, a nucleation layer may be further disposed between the substrate and the first active layer.

According to another aspect of the present invention, the flash layer may include metallic Al.

According to another aspect of the present invention, the flash layer may include metal Ga.

According to another aspect of the invention, the flash layer may be an annealed flash layer forming a native oxide layer.

According to another aspect of the present invention, the second active layer and the flash layer may include first and second recesses formed therein, and the source and drain contacts may be disposed in the first and second recesses, respectively.

Drawings

Fig. 1 shows an example of a conventional GaN-based FET.

Figure 2 shows one example of a circuit constructed in accordance with the present invention.

Fig. 3 and 4 show current-voltage characteristics of the circuit shown in fig. 2.

Fig. 5 shows the current versus gate-source voltage for the circuit shown in fig. 2.

Fig. 6 shows an example of a gallium nitride based FET that may be employed in the circuit shown in fig. 2.

Fig. 7 and 8 show alternative examples of gallium nitride (GaN) FETs that may be employed in the circuit shown in fig. 2.

Detailed Description

The inventors of the present invention have recognized that the desired operating characteristics of a semiconductor GaN-based enhancement mode FET semiconductor structure can be readily achieved by using a GaN-based depletion mode structure having similar operating characteristics, instead of fabricating such a structure. That is, as detailed below, the present invention combines a GaN-based depletion mode FET with one or more other components such that the resulting device functions as an enhancement mode FET. For example, in one particular embodiment of the present invention, a GaN-based depletion mode FET is arranged in series with an enhancement mode FET, thereby providing an enhancement mode device that otherwise has the characteristics of a GaN-based depletion mode FET.

The individual FET devices may be connected in various known ways, such as common source, common gate, common drain, source follower, etc., to provide different operating characteristics as desired to meet the requirements of a particular purpose. Two such devices may also be connected together to provide a variety of possible input and output characteristics not available with only one device. One example of this is the commonly used "cascode" configuration, in which the first stage devices are connected in a common source configuration and their outputs go to the inputs of the second devices, which are connected in a common gate configuration. The resulting structure is a device with high input impedance, low noise, and high gain.

Fig. 2 illustrates one example of a circuit 100 constructed in accordance with the present invention. The source of the GaN-based depletion mode FET110 is connected to the drain of the enhancement mode FET 120. The enhancement mode FET 120 may be, for example, a conventional silicon-based or GaAs-based device. The gate of the depletion mode FET 100 is grounded so that the FET110 is always on. In the example of fig. 2, the on state of FET 120 is maintained by grounding the gate of FET 110. The source of the enhancement mode FET 120 is connected to ground. The drain of the depletion mode FET110 serves as the drain D of the circuit 100. The source of the enhancement mode FET 120 serves as the source S of the circuit 100. Likewise, the gate of the enhancement mode FET 120 serves as the gate G of the circuit 100.

The operation of the circuit 100 may be explained with reference to the current-voltage characteristic curves shown in fig. 3 and 4. For purposes of illustration only and not to limit the invention, FETs 110 and 120 are both n-type devices, but alternatively p-type devices may be used. Fig. 3 shows the current-gate-source voltage of the enhancement mode FET 120. The pinch-off voltage of the FET 120 is shown to be 5V in this example. Fig. 4 shows the current versus gate-source voltage for the depletion mode FET 110. The pinch-off voltage of the depletion mode FET110 is shown to be-6V in this example.

Fig. 4 shows that if the gate-source voltage VGS is 0V or more, the depletion mode FET110 will remain in a conductive state. Since the gate of the FET110 is shown to be grounded in this example, the depletion mode FET is always on. Fig. 3 shows that if a gate-source voltage VGS of 5V or more is applied, the enhancement mode FET 120 is always on. Since current needs to flow along the path from the drain D of the depletion mode FET110 to the source S of the enhancement mode FET 120, by changing the gate voltage G to a value of 5V or more, the circuit will be in its on state, thereby acting as an enhancement mode FET. In this way, the gate G of the enhancement mode FET 120 will regulate the current through the circuit 100 in the manner of an enhancement mode FET, while the blocking voltage of the depletion mode FET110 provides the blocking capability for the entire circuit 100. Thus, the circuit 100 functions as a 600V GaN-based enhancement mode FET. Fig. 5 shows the current versus gate-source voltage of the circuit 100.

In the example presented above, the GaN-based depletion mode FET110 has a rated voltage of 600V, and the rated voltage of the FET 120 is 20V. More generally, in some embodiments of the invention, the depletion mode FET is any suitable high voltage (e.g., a voltage above about 100V) FET. The output voltage of the circuit 100 will typically be approximately equal to the nominal voltage difference between the depletion mode FET110 and the enhancement mode FET 120. Therefore, to maximize the voltage rating of the circuit 100, it is preferable to select the voltage rating of the enhancement mode FET 120 as small as possible. The remaining characteristics of the circuit 100, such as its current rating and its drain-source resistance in the on state, will be similar to those of the depletion mode FET 110.

Fig. 6-8 show some specific examples of depletion mode FETs 110 that may be employed in the circuit 100. Of course, the present invention is not limited to these structures, which are shown for exemplary purposes only. In fig. 6, the depletion mode FET 10 includes a substrate 12, a nucleation (transition) layer 18, a GaN buffer layer 22, aluminum gallium nitride (Al)_xGa_1-xN; 0 < x < 1) schottky layer 24 and cap or termination layer 16. In addition, the FET 10 includes a source contact 27, a gate contact 28, and a drain contact 30.

The FET 10 is typically fabricated using an epitaxial growth process. For example, a reactive sputtering process may be used in which a metallic component of a semiconductor, such as gallium, aluminum, and/or indium, is spilled from a metallic target disposed adjacent to a substrate while both the target and the substrate are in an atmosphere including nitrogen and one or more dopants. Alternatively, Metal Organic Chemical Vapor Deposition (MOCVD) may be employed, wherein the substrate is exposed to an atmosphere of organic compounds containing the metal, and reactive nitrogen-containing gases such as ammonia and dopant-containing gases, while the substrate is maintained at an elevated temperature, typically around 700 to 1100 ℃. The gaseous compounds decompose and form a doped semiconductor in the form of a film of crystalline material on the surface of the substrate 302. The substrate and grown film are then cooled. As a further alternative, other epitaxial growth methods such as Molecular Beam Epitaxy (MBE) or atomic layer epitaxy may be used. Additional techniques that may be employed include, but are not limited to, flow modulated organometallic vapor phase epitaxy (FM-OMVPE), organometallic vapor phase epitaxy (OMVPE), hydride epitaxy (HVPE), and Physical Vapor Deposition (PVD).

To initiate growth of the structure, a nucleation layer 18 is deposited on the substrate 12. Substrate 12 may be formed from a variety of materials including, but not limited to, sapphire or silicon carbide (SiC). The nucleation layer 18 may be, for example, such as Al_xGa_1-xAn aluminum rich layer of N, wherein X is in the range of 0 to 1. The nucleation layer 18 operates to correct the lattice mismatch between the GaN buffer layer 22 and the substrate 12. In general, lattice mismatch occurs when the spacing between atoms in one layer does not match the spacing between atoms in an adjacent layer. Due to lattice mismatch, the bonding between atoms in adjacent layers is weak, and the adjacent layers may be broken, separated, or have a large number of crystal defects. Thus, the nucleation layer 18 operates to correct the lattice mismatch between the GaN buffer layer 22 and the substrate 12 by creating an interface between the crystal structure of the substrate 12 and the crystal structure of the GaN buffer layer 22.

After depositing nucleation layer 18, GaN buffer layer 22 is deposited on nucleation layer 18, and Al is deposited on GaN buffer layer 22_xGa_1-xN schottky layer 24. Two-dimensional conductive channel 26, which is a thin high mobility channel, confines carriers to GaN buffer layer 22 and Al_xGa_1-xThe interface region between the N schottky layers 24. In Al_xGa_1-xA cap or termination layer 16 is deposited on the N-schottky layer 24, the cap or termination layer 16 serving to protect Al during fabrication and operation of the FET 10_xGa_1-xThe N-schottky layer 24 protects it from surface reactions such as oxidation. Since the Schottky layer 24 contains aluminum, if Al is present_xGa_1-xOxidation may occur if the N schottky layer 24 is exposed to air and not otherwise protected.

After growth of epitaxial layers 18, 22 and 24 and termination layer 16 on substrate 12, FET 10 is completed by depositing source contact 27, gate contact 28 and drain contact 30 on termination layer 16, respectively. Each of the contacts 27, 28, and 30 is a metal contact. Preferably, the gate contact 28 is a metal material such as, but not limited to, nickel, gold, and the source contact 27 and the drain contact 30 are both a metal material such as, but not limited to, titanium, gold, or aluminum.

In one embodiment of the present invention, the stop layer 16 is formed on Al_xGa_1-xAn InGaN layer on the N schottky layer 24. The InGaN layer 16 serves two purposes,the first purpose is to provide an upper layer that does not contain Al, thereby reducing oxidation. Furthermore, by using InGaN materials instead of materials comprising aluminum, the growth process can be simplified, since aluminum-containing compounds such as InGaAlN typically require higher growth temperatures to provide sufficient uniformity and smoothness. In addition, the InGaN layer 24 slightly lowers the potential barrier at the surface, which can reduce the increase of surface charges and reduce the leakage current on the surface of the structure.

In another embodiment of the present invention, the termination layer 16 is a flash layer (flash layer) comprising Al metal. A very short burst of material is utilized to form the flash layer. This will form a very thin (e.g., 1-2 monolayers of material) but flat coverage over the structure surface. The flash layer is typically performed in-situ. To ensure that metallic Al is formed instead of AlN, there is no reactive nitrogen-containing gas (e.g., ammonia) that would be present when forming AlN. The Al flash layer may be formed at a high temperature or a low temperature. After its formation, the Al may then be annealed to form a thin oxide layer. Since the Al flash layer is very thin, it can be fully oxidized, thereby creating an initial "native" oxide on the material that subsequently protects the schottky layer 24 from any type of degradation typically seen during processing. This can be used as an additional barrier material for reducing leakage current and increasing breakdown voltage, which is important to HEMT performance. Instead of aluminum, the flash layer may contain other metals, such as gallium or even indium. The Ga or In flash layer may also be oxidized to form a uniform "native" oxide on the structure.

In other embodiments of the present invention, the cap or stop layer 16 may be formed of other materials, such as highly Fe-doped GaN, Si-doped GaN, FeN, or SiN. These layers, which may be epitaxial, non-epitaxial or even amorphous, may be used as initial passivation layers or as additional barrier materials for reducing leakage currents and increasing breakdown voltages. For example, the addition of Fe to GaN results in a material that can reduce leakage current because the material is more insulating and reduces electron mobility.

In other embodiments of the present invention, Al may be included_xGa_1-xA thin AlN layer is formed on the N schottky layer 24. This layer provides an additional schottky barrier layer to help more effectively regulate charge, thereby reducing leakage current and increasing the breakdown voltage of the device. The AlN layer may also serve as an initial passivation layer for the structure, since AlN can be easily wet etched to deposit ohmic contacts. Alternatively, the AlN layer may be oxidized to form a passivation layer.

In some embodiments, the thickness of the termination layer 16 is approximately 1 to 5 nanometers. Thus, electrons can easily tunnel through the termination layer 16. As a result, the stop layer 16 does not add gate contact 28 and Al_xGa_1-xSchottky barrier height between the N schottky layers 24, wherein the schottky barrier height defines the gate contact 28 and Al_xGa_1-xA potential energy barrier encountered by electrons at the interface of the N schottky layer 24. In addition, the stop layer 16 does not affect the formation of the source contact 27 and the drain contact 30.

FIG. 7 shows yet another embodiment of the FET 10 in which ohmic contacts 27 and 28 are located at Al_xGa_1-xIn a recess formed in the N schottky layer 24. By etching Al according to conventional techniques_xGa_1-xN schottky layer 24 to form the recess. The recess may extend partially or completely through the Al_xGa_1-xN schottky layer 24. For example, in some cases, the recess may extend to a depth of about 5nm to 15nm deep, thereby making Al_xGa_1-xThe N schottky layer 24 can maintain a sufficient thickness to create the channel layer 26. By recessing the contact in this manner, the contact resistance and smoothness of the surface is reduced, thereby increasing the permeability of the metal deposited to form the ohmic contact. The increase in surface roughness results in better migration of the metal into the semiconductor. For devices requiring low on-resistance, this arrangement can be significant in achieving the lowest possible on-resistance. Although not shown, this embodiment of the invention may also employ a capping layer or termination such as those discussed aboveAnd (3) a layer. In this case, the recesses in which the contacts 27 and 28 are disposed will also extend through the termination layer.

FIG. 8 shows another embodiment of the FET 10 in which the barrier layer 24 is formed of Al instead of Al_xGa_1-xAlInGaN of N. For example, Al is employed as discussed in "straight Energy B and Engineering in AlGaInN/GaNHeterOStruetstructure Field Effect Transistors" by M.AsifKhan et Al in GAAS99_xIn_yGa_(1-x-y)An N-junction having a barrier thickness of less than 50nm and an alloy composition varying over a range of x equal to 0.1 to 0.2 and y equal to 0.00 to 0.02. Furthermore, Khan et Al states that an Al/In ratio of 5 should almost match the GaN lattice based on linear interpolation of the lattice constant. By using AlInGaN, the strain can be controlled independently of the bandgap, thereby enabling the bandgap of the material to vary more freely with respect to the critical thickness. For power devices, it is critical to get the most charge in the channel without unduly stressing the material and shortening the lifetime of the device, which can occur as the material relaxes over time.

Although various embodiments are specifically illustrated and described herein, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the invention. For example, while the depletion mode FET has been described as a GaN-based device, the present invention more generally includes a depletion mode FET formed of any group III nitride compound semiconductor In which the group III element may be gallium (Ga), aluminum (Al), boron (B), or indium (In).

Claims (20)

1. A circuit, comprising:

an input drain node, an input source node, and an input gate node;

a III-nitride depletion mode FET having a source, a drain, and a gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state;

an enhancement-mode FET having a source, a drain, and a gate, wherein the source of the depletion-mode FET is coupled in series to the drain of the enhancement-mode FET, wherein the enhancement-mode FET is a silicon-based device or a GaAs-based device; and is

Wherein the drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node, and the gate of the enhancement mode FET serves as the input gate node.

2. The circuit of claim 1, wherein the group III nitride comprises GaN.

3. The circuit of claim 1, wherein the depletion mode FET is a high voltage FET having a voltage rating greater than about 100V, wherein the depletion mode FET has a two-dimensional high mobility channel that confines carriers to an interface region between a group III-nitride layer and a Schottky layer.

4. The circuit of claim 1, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer;

a flash layer disposed on the second active layer; and

a source contact, a gate contact, and a drain contact disposed on the flash layer.

5. The circuit of claim 4, wherein the first active layer comprises GaN and the second active layer comprises a group III nitride semiconductor material.

6. The semiconductor device according to claim 5, wherein the second active layer contains Al_xGa_1-xN, wherein X is more than 0 and less than 1.

7. The semiconductor device of claim 5, wherein the second active layer is selected from the group consisting of AlGaN, AlInN, and AlInGaN.

8. The semiconductor device of claim 4, further comprising a nucleation layer disposed between the substrate and the first active layer.

9. The semiconductor device according to claim 4, wherein the flash layer comprises metal Al.

10. The semiconductor device of claim 4, wherein the flash layer comprises metal Ga.

11. The semiconductor device of claim 4, wherein the flash layer is an annealed flash layer forming a native oxide layer.

12. The semiconductor device of claim 4, wherein the second active layer and the flash layer include first and second recesses formed therein, and the source and drain contacts are disposed in the first and second recesses, respectively.

13. The circuit of claim 1, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer;

an AlN layer formed over the second active layer; and

a source contact, a gate contact, and a drain contact disposed over the AlN layer.

14. The circuit of claim 1, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer, wherein the second active layer includes a first recess and a second recess formed therein;

a source contact and a drain contact disposed in the first recess and the second recess, respectively;

a gate electrode disposed above the second active layer.

15. A circuit, comprising:

an input drain node, an input source node, and an input gate node;

a group III-nitride depletion mode FET;

an enhancement-mode FET arranged in series with the depletion-mode FET, wherein the enhancement-mode FET is a silicon-based device or a GaAs-based device; and is

Wherein a first terminal of the depletion-mode FET serves as the input drain node and a second terminal and a third terminal of the enhancement-mode FET serve as the source node and gate node, respectively.

16. The circuit of claim 15, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer;

a flash layer disposed on the second active layer; and

a source contact, a gate contact, and a drain contact disposed on the flash layer.

17. The circuit of claim 15, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer;

an AlN layer formed over the second active layer; and

a source contact, a gate contact, and a drain contact disposed over the AlN layer.

18. The circuit of claim 15, wherein the ill-nitride depletion mode FET comprises:

a substrate;

a first active layer disposed over the substrate;

a second active layer disposed on the first active layer, the second active layer having a higher band gap than the first active layer such that a two-dimensional electron gas layer is generated between the first active layer and the second active layer, wherein the second active layer includes a first recess and a second recess formed therein;

a source contact and a drain contact disposed in the first recess and the second recess, respectively;

a gate electrode disposed above the second active layer.

19. The circuit of claim 16, wherein the first active layer comprises GaN and the second active layer comprises a group III nitride semiconductor material.

20. The circuit of claim 16, wherein the flash layer comprises metal Al.