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WO2010064599A1 - Dispositif de conversion photoélectrique à film mince au silicium et son procédé de fabrication - Google Patents

Dispositif de conversion photoélectrique à film mince au silicium et son procédé de fabrication Download PDF

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Publication number
WO2010064599A1
WO2010064599A1 PCT/JP2009/070101 JP2009070101W WO2010064599A1 WO 2010064599 A1 WO2010064599 A1 WO 2010064599A1 JP 2009070101 W JP2009070101 W JP 2009070101W WO 2010064599 A1 WO2010064599 A1 WO 2010064599A1
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photoelectric conversion
silicon
semiconductor layer
type semiconductor
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Japanese (ja)
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克史 岸本
克彦 野元
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/17—Photovoltaic cells having only PIN junction potential barriers
    • H10F10/172—Photovoltaic cells having only PIN junction potential barriers comprising multiple PIN junctions, e.g. tandem cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a silicon-based thin film photoelectric conversion device and a manufacturing method thereof.
  • a major feature of this solar cell is that a semiconductor film or a metal electrode film is stacked on a large-area inexpensive substrate using a film-forming apparatus such as a plasma CVD apparatus or a sputtering apparatus, and then a method such as laser patterning is performed.
  • a film-forming apparatus such as a plasma CVD apparatus or a sputtering apparatus
  • an in-line method in which a plurality of film formation chambers (also referred to as “chambers”, hereinafter the same) corresponding to each layer of a solar cell are linearly connected, or an intermediate chamber is provided in the center.
  • a multi-chamber system in which a plurality of film forming chambers are arranged around is employed.
  • the in-line method since the flow line of substrate transfer is linear, the entire apparatus must be stopped even when maintenance is partially required. For example, since a plurality of film forming chambers for forming an i-type silicon photoelectric conversion layer requiring the most maintenance are included, maintenance is required for one film forming chamber for forming an i-type silicon photoelectric conversion layer. Even in such a case, there is a problem that the entire production line must be stopped.
  • the multi-chamber method is a method in which a substrate to be deposited is moved to each deposition chamber via an intermediate chamber, and a movable partition that can maintain airtightness between each deposition chamber and the intermediate chamber. Therefore, even if a problem occurs in one film forming chamber, the other film forming chamber can be used, and the entire production apparatus does not have to be stopped.
  • this multi-chamber type production apparatus there are a plurality of flow lines of the substrate through the intermediate chamber, and it is inevitable that the mechanical structure of the intermediate chamber becomes complicated. For example, a mechanism for moving the substrate while maintaining airtightness between the intermediate chamber and each film forming chamber is complicated, and as a result, the entire apparatus becomes expensive. There is also a problem that the number of film forming chambers arranged around the intermediate chamber is spatially limited.
  • a p-type semiconductor layer, an i-type microcrystalline silicon-based photoelectric conversion layer, and an n-type semiconductor layer are sequentially formed in the same plasma CVD deposition chamber, and the p-type semiconductor layer
  • the pressure in the film forming chamber is formed under conditions of 667 Pa (5 Torr) or more (for example, Japanese Patent Laid-Open No. 2000-252495 (Patent Document) See 1)).
  • Japanese Patent Laid-Open No. 2000-252495 Patent Document 1 discloses that according to this method, a photoelectric conversion device having good performance and quality can be manufactured with a simple device at low cost and high efficiency.
  • Patent Document 1 a p-type semiconductor layer, an i-type silicon-based photoelectric conversion layer, and an n-type semiconductor layer ( These layers are hereinafter also referred to as “pin layers.” Also, a p-type layer, an i-type layer, and an n-type layer are arranged in this order, or an n-type layer, an i-type layer, and a p-type layer are arranged in this order.
  • This structure is also referred to as “pin structure.”) Is repeatedly performed in the same film forming chamber, and therefore, in the n-type layer in the residual film formed on the cathode and / or on the inner surface of the plasma CVD film forming chamber. In the initial stage of forming the next p-type semiconductor layer and i-type silicon-based photoelectric conversion layer, it is inevitable that the n-type dopant is mixed into the p-type semiconductor layer and the i-type silicon-based photoelectric conversion layer. There is.
  • a p-type layer is also formed on the cathode and / or on the inner surface of the film forming chamber.
  • An i-type layer is formed on the p-type layer when the conversion layer is formed, and an n-type layer is formed on the i-type layer when the n-type semiconductor layer is formed next.
  • a laminated film of a p-type layer, an i-type layer, and an n-type layer is formed as a residual film on the cathode and / or on the interior surface of the plasma CVD film forming chamber.
  • n-type dopant also referred to as an n-type impurity atom, hereinafter the same
  • n-type impurity atom hereinafter the same
  • the n-type dopant weakens the function of the p-type dopant (also referred to as a p-type impurity atom, hereinafter the same).
  • the space charge of the type semiconductor layer cannot be secured.
  • various parameters of the solar cell such as a reduction in open circuit voltage and polarity factor, may be adversely affected.
  • an amorphous photoelectric conversion layer is manufactured using an in-line CVD device, and then the microcrystalline silicon-based photoelectric conversion layer is formed using another CVD device.
  • a manufacturing method has been proposed (Japanese Patent Laid-Open No. 2000-252496 (Patent Document 3)). This is because the amorphous photoelectric conversion layer and the microcrystalline silicon-based photoelectric conversion layer are known to cause deterioration in characteristics when the amorphous photoelectric conversion layer is formed in the same film formation chamber. Is to improve the efficiency of the line. In addition, it is a measure for reducing downtime, which is a problem in an in-line CVD apparatus.
  • An object of the present invention is to provide a method of manufacturing a silicon-based thin film photoelectric conversion device having good quality and high photoelectric conversion efficiency at low cost and with high efficiency using a simple manufacturing apparatus. It is another object of the present invention to provide a manufacturing method capable of manufacturing a silicon-based thin film photoelectric conversion device with a high yield using a plurality of plasma CVD film forming chambers having the same configuration.
  • a first embodiment of a method for producing a silicon-based thin film photoelectric conversion device includes a step of forming a transparent conductive film on a substrate, a first p-type semiconductor layer, and i-type amorphous silicon on the transparent conductive film.
  • a step of forming a crystalline pin structure stack having two n-type semiconductor layers in this order, and the step of forming the amorphous pin structure stack is a first plasma CVD film formation.
  • the step of forming a crystalline pin structure laminate in a room by film formation in a single chamber is the step of forming the amorphous pin structure laminate in a second plasma CVD film formation chamber by film formation in a single chamber.
  • the film formation pressure in the first plasma CVD film formation chamber is 2 A at 0Pa than 3000Pa less, characterized in that the power density per unit electrode area is formed by the 0.01 W / cm 2 or more 0.3 W / cm 2 following conditions.
  • a second embodiment of the method for producing a silicon-based thin film photoelectric conversion device of the present invention includes a step of forming a transparent conductive film on a substrate, a first n-type semiconductor layer, and i-type amorphous silicon on the transparent conductive film.
  • a step of forming a crystalline pin structure stack having two p-type semiconductor layers in this order, and the step of forming the amorphous pin structure stack is a first plasma CVD film formation.
  • the step of forming a crystalline pin structure laminate in a room by film formation in a single chamber is the step of forming the amorphous pin structure laminate in a second plasma CVD film formation chamber by film formation in a single chamber.
  • the film formation pressure in the first plasma CVD film formation chamber is 2 A at 0Pa than 3000Pa less, characterized in that the power density per unit electrode area is formed by the 0.01 W / cm 2 or more 0.3 W / cm 2 following conditions.
  • the step of forming the amorphous pin structure laminate may be a step of repeatedly forming the amorphous pin structure laminate.
  • the first p-type semiconductor layer has a thickness of 2 nm to 50 nm
  • the i-type amorphous silicon-based photoelectric conversion layer has a thickness of 0.1 ⁇ m to 0.5 ⁇ m
  • the first n-type semiconductor The thickness of the layer is preferably 2 nm or more and 50 nm or less.
  • the second p-type semiconductor layer has a thickness of 2 nm to 50 nm
  • the i-type crystalline silicon-based photoelectric conversion layer has a thickness of 0.5 ⁇ m to 20 ⁇ m
  • the second n-type semiconductor layer The thickness is preferably 2 nm or more and 50 nm or less.
  • the substrate temperature of the second p-type semiconductor layer is 250 ° C. or lower
  • the source gas introduced into the second plasma CVD film formation chamber includes a silane-based gas and a dilution gas containing hydrogen gas. It is preferable that the flow rate of the dilution gas with respect to the silane-based gas is formed under the condition of 100 times or more.
  • the conductivity determining impurity atoms of the first p-type semiconductor layer and the second p-type semiconductor layer can be boron atoms or aluminum atoms.
  • the i-type crystalline silicon-based photoelectric conversion layer has a substrate base temperature of 250 ° C. or lower, and a raw material gas introduced into the second plasma CVD deposition chamber includes a silane-based gas and a dilution gas, flow rate of the diluent gas to the gas is formed under the following conditions 100 times 30 times or more, the peak intensity of the peak intensity I 520 at 520 cm -1 to the peak intensity I 480 at 480 cm -1 as measured by Raman spectroscopy ratio I 520 / It is preferable that I480 is 5 or more and 10 or less.
  • the conductivity type-determining impurity atoms in the first n-type semiconductor layer and the second n-type semiconductor layer can be phosphorus atoms.
  • the second n-type semiconductor layer has a substrate base temperature of 250 ° C. or lower, and a phosphorus atom content rate of 0.1 atomic% with respect to silicon atoms in the source gas introduced into the second plasma CVD film formation chamber. It is preferably formed under the condition of 5 atomic% or less.
  • the method for producing a silicon-based thin film photoelectric conversion device includes a step of unloading the silicon-based thin film photoelectric conversion device from the second plasma CVD film forming chamber after the step of forming the crystalline pin structure laminate. And a step of removing a residual film on at least one of the cathode and the chamber surface in the first plasma CVD film forming chamber or the second plasma CVD film forming chamber.
  • the step of removing the residual film is preferably performed by gas plasma obtained by converting at least one gas selected from the group consisting of hydrogen gas, inert gas, and fluorine-based cleaning gas into plasma.
  • the step of removing the residual film includes the step of etching and removing the surface layer of the residual film to the n-type layer closest to at least one of the cathode and the indoor surface, and at least one of the cathode of the residual film and the indoor surface. It is preferable to include a step of etching and removing the i-type layer located at the closest position at a depth in the thickness direction of 10 nm or more and 90% or less of the entire thickness of the i-type layer.
  • the step of removing the residual film is preferably performed when the cumulative film thickness of the residual film on the cathode in the first plasma film formation chamber or the second plasma CVD film formation chamber is 10 ⁇ m or more and 1000 ⁇ m or less.
  • the present invention also relates to a silicon-based thin film photoelectric conversion device manufactured by the method for manufacturing a silicon-based thin film photoelectric conversion device as described above.
  • the present invention it is possible to form a thin film having a pin structure using a plasma CVD film forming chamber having the same electrode configuration, and a silicon-based thin film photoelectric conversion device having good quality and high photoelectric conversion efficiency. Can be provided at low cost and with high efficiency using a simple manufacturing apparatus.
  • FIG. 1 is a schematic cross-sectional view showing a silicon-based thin film photoelectric conversion device according to a first embodiment. It is the schematic of the plasma CVD apparatus used in this invention. It is a flowchart which shows roughly one Embodiment of the manufacturing method of the silicon type thin film photoelectric conversion apparatus concerning this invention. It is a schematic cross section which shows the silicon type thin film photoelectric conversion apparatus concerning this Embodiment 3.
  • the first embodiment of the method for producing a silicon-based thin film photoelectric conversion device of the present invention includes a step of forming a transparent conductive film on a substrate, a first p-type semiconductor layer, and an i-type amorphous film on the transparent conductive film. Forming an amorphous pin structure stack having a crystalline silicon-based photoelectric conversion layer and a first n-type semiconductor layer, a second p-type semiconductor layer, an i-type crystalline silicon-based photoelectric conversion layer, and a second Forming a crystalline pin structure stack having the n-type semiconductor layer in this order, and the step of forming the amorphous pin structure stack is performed in the first plasma CVD deposition chamber.
  • the step of forming the crystalline pin structure stack by performing film formation is performed by one-chamber film formation in the second plasma CVD film forming chamber, and the step of forming the amorphous pin structure stack is the first step.
  • the film forming pressure in the plasma CVD film forming chamber is 200 Pa or higher.
  • A is 3000Pa hereinafter, characterized in that the power density per unit electrode area is formed by the 0.01 W / cm 2 or more 0.3 W / cm 2 following conditions.
  • a pin structure laminate is a p-type layer, an i-type layer, and an n-type layer formed in this order, or an n-type layer, an i-type layer, and a p-type layer in this order.
  • a laminated body is used for a stacked structure of an amorphous pin structure stack having an i-type amorphous silicon photoelectric conversion layer and a crystalline pin structure stack having an i-type crystalline silicon photoelectric conversion layer.
  • a laminate is also referred to as a stacked silicon-based thin film photoelectric conversion device.
  • FIG. 1 is a schematic cross-sectional view showing a silicon-based thin film photoelectric conversion device according to the present invention
  • FIG. 2 is a schematic view of a plasma DVD device used in the present invention
  • FIG. 3 is a flowchart schematically showing a method for manufacturing a silicon-based thin film photoelectric conversion device according to the present invention. Note that “S” such as S1 in FIG. 3 indicates “process”.
  • a transparent conductive film 2 is formed on a substrate 1 as shown in FIG.
  • the substrate 1 is a substrate having heat resistance and translucency in a plasma CVD film forming process, and can be exemplified as a glass substrate, a resin substrate such as polyimide, and the like that are generally used.
  • a known transparent conductive film such as tin oxide, indium tin oxide (ITO), or zinc oxide can be applied, and these are formed by a method such as CVD, sputtering, or vapor deposition. Can do.
  • the amorphous pin structure laminate including the first p-type semiconductor layer 11, the i-type amorphous silicon-based photoelectric conversion layer 12, and the first n-type semiconductor layer 13 on the transparent conductive film 2. 10 is formed.
  • This step can be performed using a plasma CVD apparatus as shown in FIG.
  • the substrate 1 on which the transparent conductive film 2 is formed is transferred to the heating chamber 210 and heated and held for a certain period of time until reaching the film forming temperature (S1 and S2 in FIG. 3).
  • the heating chamber 210 is provided with a known heating mechanism such as a heater.
  • the substrate 1 is transferred to the first plasma CVD film forming chamber 220 via the connecting portion 5 (S3 in FIG. 3), and a desired pin structure laminate is formed (S4 in FIG. 3).
  • the first plasma CVD film forming chamber 220 can be sealed, and a cathode 222 and an anode 223 are disposed opposite to each other in the first plasma CVD film forming chamber 220, and these have a parallel plate type electrode structure. .
  • each pin structure stack is formed in a separate plasma CVD film forming chamber.
  • a plasma CVD film forming chamber for forming a crystalline pin structure laminate having an i-type crystalline silicon-based photoelectric conversion layer as the electrode structure in order to form a high-quality film, a cathode and The anode distance is set small.
  • the distance between the cathode and the anode is, for example, 3 mm to 20 mm, preferably 5 mm to 15 mm, more preferably 7 mm to 12 mm, and it is necessary to form a film under a high pressure condition in the plasma CVD film forming chamber.
  • the distance between the cathode and the anode is usually set larger as the electrode structure.
  • the reason why the distance is increased as described above is that if the distance between the cathode and the anode is set small, the non-uniformity in the cathode surface of the distance is caused by the distribution in the cathode surface of the electric field strength between the cathode and the substrate on the anode. This is because it greatly affects, and when an i-type amorphous silicon-based photoelectric conversion layer is formed, it is introduced into the plasma CVD film formation chamber as compared with the case where an i-type crystalline silicon-based photoelectric conversion layer is formed. This is because the raw material gas has a gas composition that is easier to discharge, and the degree of freedom in the distance between the cathode and the anode is large.
  • a good quality In order to form the i-type crystalline silicon-based photoelectric conversion layer, a device in which the distance between the cathode and the anode is set small, and in order to form the i-type amorphous silicon-based photoelectric conversion layer, the distance between the cathode and the anode.
  • an apparatus set larger than the case of forming an i-type crystalline silicon-based photoelectric conversion layer is required.
  • an amorphous pin structure laminate having an i-type amorphous silicon photoelectric conversion layer and an i-type crystalline silicon photoelectric conversion layer are provided. It is possible to manufacture the double pin structure laminate using an apparatus in which the distance between the cathode and the anode when forming the crystalline pin structure laminate having the same is set to be substantially the same. It is. That is, since the distance between the cathode and the anode of a plurality of plasma CVD apparatuses can be set to be the same, any i-type can be obtained by changing the gas introduction conditions without being restricted by the arrangement of the apparatuses. A silicon-based photoelectric conversion layer can be formed.
  • the electrode structure for forming the i-type amorphous silicon-based photoelectric conversion layer is the same as that for forming the i-type crystalline silicon-based photoelectric conversion layer.
  • the distance between the anodes is set to be small, for example, 3 mm to 20 mm, preferably 5 mm to 15 mm, and more preferably 7 mm to 12 mm.
  • Paschen's law the pressure at the time of film formation in the plasma CVD film forming chamber is increased to facilitate discharge. .
  • the inventors have found that a high-quality i-type amorphous silicon-based photoelectric conversion layer cannot be formed only by increasing the pressure in the deposition chamber.
  • the film formation pressure is set higher than the normal conditions for forming the amorphous pin structure laminate having the i-type amorphous silicon-based photoelectric conversion layer and applied to the cathode.
  • the one-chamber film formation refers to a method in which a p-type layer, an i-type layer, and an n-type layer are successively formed in the same film formation chamber.
  • the formation condition that the film forming pressure is 200 Pa or higher is a pressure condition higher than the conventional condition (about 100 Pa to 120 Pa) for forming the amorphous silicon-based semiconductor layer.
  • the first p-type semiconductor layer 11 and the i-type amorphous silicon-based photoelectric conversion layer 12 under the formation conditions of a film-forming pressure of 3000 Pa or less, a silicon-based semiconductor having good film quality for a thin film photoelectric conversion device A thin film can be formed.
  • the cathode 222 is formed.
  • the energy of electrons and ions in the impinging plasma can be reduced. Since the n-type impurity atoms are knocked out by the electrons and ions in the plasma from the second n-type semiconductor layer 13 attached to the cathode 222, the first p-type formed by reducing the energy of these n-type impurity atoms is reduced.
  • the amount of n-type impurity atoms taken into the semiconductor layer 11 and the i-type amorphous silicon photoelectric conversion layer 12 can be reduced.
  • the first p-type semiconductor layer 11 and the i-type amorphous silicon-based photoelectric conversion layer 12 under the formation conditions with a power density of 0.01 W / cm 2 or more, good film quality for a thin film photoelectric conversion device is obtained.
  • the silicon-based semiconductor thin film can be formed.
  • the substrate 1 on which the transparent conductive film 2 transferred to the first plasma CVD film forming chamber 220 is formed is loaded on the anode 223.
  • the first p-type semiconductor layer 11 is formed on the transparent conductive film 2.
  • the first p-type semiconductor layer 11 can be an amorphous silicon-based semiconductor or a crystalline silicon-based semiconductor.
  • the formation condition thereof is, for example, a film forming pressure of 200 Pa to 3000 Pa, preferably 300 Pa to 2000 Pa. , more preferably not more than 1500Pa least 400 Pa, under the conditions underlying temperature is 250 ° C.
  • a dilution gas, a material gas, a doping gas, and the like are introduced from a gas inlet (not shown). .
  • Examples of the diluent gas include a gas containing hydrogen gas, and examples of the material gas include silane-based gas, methane gas, and germane gas. Gases such as methane and trimethyldiborane are included for the purpose of reducing the amount of light absorption in the first p-type semiconductor layer 11, and thereby, p-type impurities are added to the i-type amorphous silicon-based photoelectric conversion layer to be formed next. A p-type semiconductor layer which is not affected by atoms can be formed.
  • the impurity atoms that determine the conductivity type of the first p-type semiconductor layer 11 are not particularly limited, but have a high doping effect and are versatile. From this point, it is preferably a boron atom or an aluminum atom, and a conventionally known doping gas such as diborane gas can be used.
  • the film thickness of the first p-type semiconductor layer 11 is preferably 2 nm or more in order to give a sufficient internal electric field to the i-type amorphous silicon-based photoelectric conversion layer 12, and is a first layer that is an inactive layer.
  • the first p-type semiconductor layer 11 By forming the first p-type semiconductor layer 11 under the above formation conditions, it adheres to at least one of the cathode 222 and the indoor surface 221 when forming an i-type amorphous silicon-based photoelectric conversion layer 12 described later. The amount of p-type impurities in the p-type semiconductor layer mixed into the i-type amorphous silicon photoelectric conversion layer 12 is reduced.
  • an i-type amorphous silicon-based photoelectric conversion layer 12 is formed on the first p-type semiconductor layer 11.
  • the mixed gas introduced from the gas inlet is changed to one containing a silane-based gas and a dilution gas.
  • Hydrogen gas or the like can be used as the dilution gas.
  • the flow rate of the dilution gas with respect to the silane-based gas is preferably 3 to 100 times, and more preferably 5 to 30 times by volume. By setting such a flow rate ratio, an amorphous i-type photoelectric conversion layer having good film quality can be formed.
  • the base temperature of the substrate 1 is preferably 250 ° C. or lower.
  • the film formation pressure and power density are 200 Pa to 3000 Pa, preferably 300 Pa to 2000 Pa, more preferably 400 Pa to 1500 Pa, and the cathode power density is 0.01 W / cm 2 to 0.3 W. / cm 2 or less, preferably 0.015 W / cm 2 or more 0.2 W / cm 2 or less, more preferably 0.02 W / cm 2 or more 0.15 W / cm 2 or less of the CW output of the frequency 13.56MHz AC power
  • the conditions for applying the voltage to the cathode 222 are satisfied, the conditions may be different from the conditions for forming the p-type semiconductor layer.
  • the thickness of the i-type amorphous silicon-based photoelectric conversion layer 12 is preferably 0.1 ⁇ m or more from the viewpoint of exhibiting a sufficient function as an amorphous thin-film photoelectric conversion layer. Further, the thickness of the i-type amorphous silicon-based photoelectric conversion layer 12 is preferably 0.5 ⁇ m or less, more preferably 0.4 ⁇ m or less in that a sufficient internal electric field is required.
  • the first n-type semiconductor layer 13 is formed on the i-type amorphous silicon-based photoelectric conversion layer 12.
  • the first n-type semiconductor layer 13 can be an amorphous silicon semiconductor or a crystalline silicon semiconductor.
  • the mixed gas introduced from the gas inlet is silane gas, hydrogen gas, n-type conductivity-determining impurity while maintaining the deposition pressure in the first plasma CVD deposition chamber 220 and the power density applied to the cathode 222. Change to one containing doping gas containing atoms.
  • the flow rate of the hydrogen gas relative to the silane gas may be about several tens of times in volume ratio.
  • the base temperature of the substrate 1 is preferably 250 ° C. or lower.
  • the film formation pressure and power density are 200 Pa to 3000 Pa, preferably 300 Pa to 2000 Pa, more preferably 400 Pa to 1500 Pa, and the cathode power density is 0.01 W / cm 2 to 0.3 W. / cm 2 or less, preferably 0.015 W / cm 2 or more 0.2 W / cm 2 or less, more preferably 0.02 W / cm 2 or more 0.15 W / cm 2 or less of the CW output of the frequency 13.56MHz AC power
  • the conditions for applying the voltage to the cathode 222 are satisfied, the conditions may be different from the conditions for forming the p-type semiconductor layer or the i-type amorphous silicon-based photoelectric conversion layer.
  • the conductivity type determining impurity atom of the first n-type semiconductor layer 13 is not particularly limited, but is preferably a phosphorus atom from the viewpoint of high doping efficiency and versatility. Further, the content of phosphorus atoms relative to silicon atoms in the raw material gas is preferably 0.05 atomic% or more, more preferably 0.1 atomic% or more in order to obtain a sufficient doping effect, and avoids deterioration of film quality. Therefore, it is preferably 3 atomic% or less, more preferably 1 atomic% or less.
  • atomic% refers to the percentage of the number of doping atoms relative to the number of silicon atoms expressed as a percentage. In such a condition, the conductivity type determining impurity atom concentration of the first n-type semiconductor layer 13 can be 3 ⁇ 10 19 cm ⁇ 3 or less.
  • the thickness of the first n-type semiconductor layer 13 is preferably 2 nm or more, and more preferably 5 nm or more in terms of giving a sufficient internal electric field to the i-type amorphous silicon-based photoelectric conversion layer 12.
  • the thickness of the first n-type semiconductor layer 13 is such that the n-type impurity in the residual film that may diffuse into the i-type amorphous silicon-based photoelectric conversion layer during the residual film etching step described later. 50 nm or less is preferable and 30 nm or less is more preferable in the point that the operation of reducing the amount of atoms and removing the residual film containing n-type impurity atoms is facilitated.
  • the n-type impurity atoms in the remaining film in the first n-type semiconductor layer 11 and the deposition chamber 220 are diffused to other layers. It is difficult and does not affect the second p-type semiconductor layer 21 and the i-type crystalline silicon-based photoelectric conversion layer 22 described later.
  • the first p-type semiconductor layer 11 and the i-type amorphous silicon-based photoelectric conversion layer 12 obtained by the formation conditions of the amorphous pin structure stacked body 10 as described above are the second n-type semiconductor layer. 13 is hardly affected by the n-type impurity atoms of the residual film formed in the plasma CVD film forming chamber.
  • the amorphous pin structure laminate 10 is formed by one-chamber film formation through the above steps.
  • the substrate 1 on which the amorphous pin structure laminate 10 is formed is transferred to the second plasma CVD film forming chamber 230 via the connection portion 5.
  • the second plasma CVD film formation chamber 230 has a structure that is similar to that of the reaction chamber 220 and can be sealed, and a cathode 232 and an anode 233 are opposed to each other.
  • the cathode 232 and the anode 233 have a parallel plate type electrode structure.
  • the distance between the cathode 232 and the anode 233 is set to, for example, 3 mm to 20 mm, preferably 5 mm to 15 mm, and more preferably 7 mm to 12 mm.
  • the substrate 1 transferred to the second plasma CVD film forming chamber 230 is loaded on the anode 233.
  • the crystalline pin structure laminate 20 is continuously formed on the amorphous pin structure laminate 10 by one-chamber deposition.
  • the crystalline pin structure stacked body 20 includes a second p-type semiconductor layer 21, an i-type crystalline silicon-based photoelectric conversion layer 22, and a second n-type semiconductor layer 23.
  • the second p-type semiconductor layer 21 is formed under the same conditions as those of the first p-type semiconductor layer 11 or general formation conditions (for example, conditions described in Japanese Patent Laid-Open No. 2000-243993). in may be formed, for example, deposition pressure of about 3000Pa from 600 Pa, the power density per unit electrode area is 0.05 W / from cm 2 0.3 W / cm p-type is formed by two approximately ranging microcrystalline silicon layer, such as It can be.
  • the source gas introduced into the second plasma CVD film formation chamber 230 when forming the second p-type semiconductor layer 21 includes a silane-based gas and a diluent gas containing hydrogen gas, and a diluent gas for the silane-based gas.
  • the second p-type semiconductor layer 21 is, for example, a p-type amorphous or microcrystalline silicon thin film doped with boron atoms of 0.01 atomic% or more and 5 atomic% or less as conductivity type determining impurity atoms. be able to.
  • the source gas may contain methane, trimethyldiborane, or the like for the purpose of reducing the amount of absorption in the second p-type semiconductor layer 21.
  • the base temperature of the substrate 1 when forming the second p-type semiconductor layer 21 is preferably 250 ° C. or less, so that the i-type amorphous silicon-based photoelectric conversion layer 12 is not affected.
  • the second p-type semiconductor layer 21 can be formed.
  • the second p-type semiconductor layer 21 may be formed of a layer made of an alloy material such as amorphous and microcrystalline silicon carbide or amorphous silicon germanium, or a polycrystalline silicon-based thin film or alloy system. It is a thin film and can also be made into a laminated body of a plurality of different thin films.
  • an alloy material such as amorphous and microcrystalline silicon carbide or amorphous silicon germanium, or a polycrystalline silicon-based thin film or alloy system. It is a thin film and can also be made into a laminated body of a plurality of different thin films.
  • the conductivity-type determining impurity atoms of the second p-type semiconductor layer 21 are not particularly limited, but boron atoms or aluminum atoms are preferable from the viewpoint of high doping efficiency and versatility.
  • the conductivity-type determining impurity concentration of the second p-type semiconductor layer 21 can be 5 ⁇ 10 19 cm ⁇ 3 or less, and the first n-type semiconductor layer 13 and the first p-type semiconductor layer 13 can be formed without inserting an extra recombination layer in the middle. A good ohmic junction is obtained between the second p-type semiconductor layers 21.
  • the thickness of the second p-type semiconductor layer 21 can be set in the same range as that of the first p-type semiconductor layer 11, and a sufficient internal electric field is applied to the i-type microcrystalline silicon-based photoelectric conversion layer 22. In terms of giving, 2 nm or more is preferable, and 5 nm or more is more preferable. In addition, the thickness of the second p-type semiconductor layer 21 is preferably 50 nm or less, and more preferably 30 nm or less in that it is necessary to suppress the amount of light absorption on the incident side of the inactive layer.
  • An i-type crystalline silicon-based photoelectric conversion layer 22 is formed on the substrate 1 on which the second p-type semiconductor layer 21 is formed.
  • the i-type crystalline silicon-based photoelectric conversion layer 22 may be formed under general formation conditions (for example, described in Japanese Patent Application Laid-Open No. 2000-243993).
  • the film formation pressure is about 600 Pa to 3000 Pa, can be the power density is an i-type crystalline silicon layer formed in the range of 0.05 W / cm 2 of about 0.3 W / cm 2.
  • the i-type crystalline silicon-based photoelectric conversion layer 22 can be formed without affecting the i-type amorphous silicon-based photoelectric conversion layer 12 by setting the base temperature of the substrate 1 to preferably 250 ° C. or lower.
  • the flow rate of the dilution gas with respect to the silane-based gas is preferably 30 times or more, preferably 100 times or less, and more preferably 80 times or less.
  • the i-type crystalline silicon-based photoelectric conversion layer 22 having a peak intensity ratio I 520 / I 480 of a peak at 520 cm ⁇ 1 to a peak at 480 cm ⁇ 1 measured by Raman spectroscopy of 5 or more and 10 or less. can get.
  • a sufficient crystallization rate can be obtained, and the removal (also referred to as cleaning) of a residual film formed on the cathode and / or the inner surface of the film formation chamber described later. The same can be applied to the i-type silicon photoelectric conversion layer even after the treatment.
  • the thickness of the i-type crystalline silicon-based photoelectric conversion layer 22 is preferably 0.5 ⁇ m or more, and more preferably 1 ⁇ m or more in terms of exhibiting a sufficient function as a silicon-based thin film photoelectric conversion layer containing microcrystals. Further, the thickness of the i-type crystalline silicon-based photoelectric conversion layer 22 is preferably 20 ⁇ m or less, and more preferably 15 ⁇ m or less, from the viewpoint of securing the productivity of the device. In the present invention, the i-type crystalline silicon-based photoelectric conversion layer refers to a microcrystalline i-type silicon-based photoelectric conversion layer.
  • the i-type crystalline silicon-based photoelectric conversion layer an i-type crystalline silicon thin film or a weak p-type or weak n-type thin film containing a small amount of impurities and having a sufficient photoelectric conversion function is used. May be. Further, the present invention is not limited to the microcrystalline silicon thin film, and a thin film such as silicon carbide or silicon germanium which is an alloy material may be used.
  • a second n-type semiconductor layer 23 is formed on the i-type crystalline silicon-based photoelectric conversion layer 22.
  • the second n-type semiconductor layer 23 may be formed under general formation conditions (for example, described in Japanese Patent Application Laid-Open No. 2000-243993).
  • the film formation pressure is about 600 Pa to 3000 Pa, and the power density per unit area of the electrode. It may be such as n-type microcrystalline silicon layer formed in the range of 0.05 W / cm 2 of about 0.3 W / cm 2.
  • the second n-type semiconductor layer 23 can be formed without affecting the i-type amorphous silicon photoelectric conversion layer by setting the base temperature of the substrate 1 to preferably 250 ° C. or lower.
  • the conductivity type determining impurity atom of the second n-type semiconductor layer 23 is not particularly limited, but a phosphorus atom is preferable from the viewpoint of high doping efficiency and versatility.
  • the content of phosphorus atoms relative to silicon atoms in the raw material gas is preferably 0.1 atomic% or more, more preferably 0.3 atomic% or more, from the viewpoint that a sufficient doping effect is obtained. From the point of avoidance, it is preferably 5 atomic% or less, more preferably 3 atomic% or less.
  • the thickness of the second n-type semiconductor layer 23 is preferably 2 nm or more, and more preferably 5 nm or more in terms of giving a sufficient internal electric field to the i-type crystalline silicon-based photoelectric conversion layer 22. Further, the thickness of the second n-type semiconductor layer 23 is preferably 50 nm or less, and more preferably 30 nm or less, from the viewpoint that the light absorption amount of the inactive layer needs to be suppressed.
  • the description of the film formation conditions for the second n-type semiconductor layer is not limited, and the second n-type semiconductor layer 23 is formed of an alloy material such as microcrystalline silicon carbide or silicon germanium. Are also included within the scope of the present invention.
  • the amorphous pin structure laminate and the crystalline pin structure laminate are formed by the above process. Then, as shown in FIG. 1, a conductive film 3 made of, for example, ZnO is formed on the second n-type semiconductor layer 23, and then a metal electrode made of, for example, Al, Ag, or the like is formed on the conductive film 3. 4 is formed. These conductive film 3 and metal electrode 4 constitute a back electrode part, and a silicon-based thin film photoelectric conversion device is completed.
  • the electrically conductive film 3 and the metal electrode 4 are not limited to the said illustration, It shall include all conventionally well-known aspects.
  • a second embodiment of the method for producing a silicon-based thin film photoelectric conversion device of the present invention includes a step of forming a transparent conductive film on a substrate, a first n-type semiconductor layer, and i-type amorphous silicon on the transparent conductive film.
  • the step of forming the crystalline pin structure laminate is performed by one-chamber deposition in the second plasma CVD deposition chamber, and the step of forming the amorphous pin structure laminate is performed by the first plasma.
  • the film formation pressure in the CVD film formation chamber is 200 Pa or more and 30 A is 0Pa hereinafter, characterized in that the power density per unit electrode area is formed by the 0.01 W / cm 2 or more 0.3 W / cm 2 following conditions.
  • Each p-type semiconductor layer, i-type amorphous silicon-based photoelectric conversion layer, i-type crystalline silicon-based photoelectric conversion layer, and each n-type semiconductor layer in the amorphous-type pin structure stacked body and the crystalline-type pin structure stacked body are It can be formed by the method described in Embodiment 1 above.
  • each of the pin structure laminates is formed in one chamber in the order of an n-type layer, an i-type layer, and a p-type layer.
  • a silicon-based thin film photoelectric conversion device is manufactured.
  • the chamber is formed in the order of the p-type layer, the i-type layer, and the n-type layer.
  • the influence of impurity atoms on the i-type layer which is a photoelectric conversion layer is reduced.
  • an n-type impurity atom for example, a phosphorus atom
  • a p-type impurity atom for example, a boron atom
  • the step of forming the amorphous pin structure laminate may be a step of repeatedly forming the amorphous pin structure laminate. That is, for example, the first p-type semiconductor layer and the i-type amorphous material are continuously formed in the first plasma CVD film formation chamber 220 without carrying out the substrate after forming the first n-type semiconductor layer in the first embodiment. A single-chamber silicon-based photoelectric conversion layer and a first n-type semiconductor layer are formed in this order. Thereafter, the second p-type semiconductor layer, the i-type crystalline silicon-based photoelectric conversion layer, and the second n-type semiconductor layer are formed in this order in the chamber by being transferred to the second plasma CVD film forming chamber 230. .
  • FIG. 4 shows a schematic cross-sectional view of a silicon-based thin film photoelectric conversion device 300 manufactured according to the third embodiment.
  • the substrate 1 on which the transparent conductive film 2 is formed is carried into the heating chamber 210 shown in FIG. 2 and heated to a desired substrate substrate temperature.
  • the substrate 1 is carried into the first plasma CVD film forming chamber 220 and loaded on the anode 223.
  • a desired voltage is applied to the cathode by the same process as in the first embodiment, and the first p-type semiconductor layer 11, the i-type amorphous silicon-based photoelectric conversion layer 12, and the first An amorphous pin structure stack 10 including the n-type semiconductor layer 13 is formed.
  • a p-type semiconductor layer 41 is formed on the first n-type semiconductor layer 13 in the same first plasma CVD film forming chamber 220.
  • the p-type semiconductor layer 41 can be formed under the same conditions as the first p-type semiconductor layer 11.
  • the impurity nitrogen atom concentration is set to 1 ⁇ in order to repeatedly form a thin film having a pin structure using the same plasma CVD film forming chamber. It is desirable that 10 20 cm -3 or less and the impurity oxygen atom concentration be 1 ⁇ 10 19 cm -3 or less.
  • the first n-type semiconductor layer 13 has an impurity nitrogen atom concentration of 1 ⁇ 10 20 cm so that a thin film having a pin structure can be repeatedly formed using the same plasma CVD deposition chamber. ⁇ 3 or less, and the impurity oxygen atom concentration is desirably 1 ⁇ 10 19 cm ⁇ 3 or less. As a result, a good ohmic junction can be obtained between the first n-type semiconductor layer 13 and the p-type semiconductor layer 41 without inserting an extra recombination layer in the middle.
  • an i-type amorphous silicon-based photoelectric conversion layer 42 is formed on the p-type semiconductor layer 41 by the same manufacturing method as that for the i-type amorphous silicon-based photoelectric conversion layer 12, followed by the n-type semiconductor layer 43.
  • the n-type semiconductor layer 43 can be formed under the same formation conditions as the first n-type semiconductor layer.
  • a conductive film 3 made of, for example, ZnO is formed on the second n-type semiconductor layer 23, and then a metal electrode made of, for example, Al, Ag, or the like is formed on the conductive film 3. 4 is formed.
  • the conductive film 3 and the metal electrode 4 constitute a back electrode part, and the silicon-based thin film photoelectric conversion device 300 is completed.
  • the electrically conductive film 3 and the metal electrode 4 are not limited to the said illustration, It shall include all conventionally well-known aspects.
  • the p-type layered body is formed with the p-type layer, the i-type layer, and the n-type layer in this order.
  • the pin-structured layered body is used as in the second embodiment.
  • the n-type layer, i-type layer, and p-type layer may be formed in this order.
  • the method for producing a silicon-based thin film photoelectric conversion device includes a step of unloading the silicon-based thin film photoelectric conversion device from the second plasma CVD film forming chamber after the step of forming the crystalline pin structure laminate. And a step of removing a residual film on at least one of the cathode and the chamber surface in the first plasma CVD film forming chamber or the second plasma CVD film forming chamber.
  • Etching under-etching or over-etching the remaining film on 222, 232 and / or on the interior surfaces 221, 231, and when forming the final n-type semiconductor layer, the first plasma CVD deposition chamber 220 or the second plasma
  • the influence of impurity atoms (n-type dopant) in the residual film formed on the cathodes 222 and 232 and / or on the indoor surfaces 221 and 231 of the CVD film forming chamber 230 is removed.
  • the removal of the residual film can be performed by gas plasma obtained by converting hydrogen gas, inert gas, fluorine-based cleaning gas, or any mixed gas thereof into plasma.
  • the step of removing the residual film is usually a step of removing the entire residual film formed on the cathodes 222 and 232.
  • some overetching or underetching is required.
  • the residual film formed when the double pin structure laminate is formed once is over-etched to a thickness of about 5% to 10% of the film thickness.
  • the predeposition film on the cathode formed for the purpose of stabilizing the discharge is gradually etched, so that the metal surface of the cathode appears. This may cause a large influence on a portion having a thickness of about several tens of nanometers in the initial stage of formation of the next double pin structure laminate.
  • under-etching which leaves a portion close to the cathode of the residual film formed when the double pin structure laminate is formed once.
  • This under-etching is performed from the surface layer of the residual film to the first n-type layer closest to the cathode and / or the interior surface, and preferably to a depth of 10 nm or more in the thickness direction of the amorphous i-type layer.
  • the depth of the amorphous i-type layer to be removed by etching is less than 10 nm in the thickness direction, the influence of impurity atoms (n-type dopant) in the first n-type layer diffused in the i-type layer is affected.
  • the etching removal preferably has a depth of up to 90% or less of the thickness of the i-type layer, and more preferably a depth of up to 80% or less of the thickness of the i-type layer.
  • the etching is performed deeper than 90% of the thickness of the i-type layer, the influence of impurity atoms (p-type dopant) in the p-type layer existing on the base of the i-type layer starts to appear, and the p-layer formed in the next step The doping amount may be deviated from the optimum value.
  • the influence of impurity atoms in the remaining film is completely removed by etching and removing the i-type layer together with the n-type layer to a depth of about 80% of its thickness.
  • the next substrate is carried into each plasma CVD film forming chamber after the residual film removal step is completed, and a double pin structure laminate is formed repeatedly, including the double pin structure laminate.
  • Another silicon-based thin film photoelectric conversion device is manufactured.
  • the formation process of the double pin structure laminate including the above-described under-etching process is repeated a plurality of times, residual films not etched on the cathodes 222 and 232 are laminated for the number of times the double pin structure laminate is formed. Is done. If the treatment is continued as it is, the laminated residual film may be peeled off from the cathode surface due to internal stress, and may be taken into the pin structure laminate as a powder having a diameter of several ⁇ m. A point defect to be short-circuited is created, and the product yield of the photoelectric conversion device is drastically reduced to 30% or less.
  • the photoelectric conversion device after the photoelectric conversion device is manufactured, when the residual film is peeled off from the cathodes 222 and 232, it is preferable to remove all the residual films on the cathodes 222 and 232. Further, even if the residual film is not peeled off from the cathodes 222 and 232, the above point defects are prevented from occurring before the residual film is peeled off, and the yield in manufacturing the photoelectric conversion device is kept high. Is more preferable.
  • the degree of peeling of the residual film varies greatly depending on the film formation conditions and the surface state of the electrode when the film is attached. However, when a silicon-based thin film is formed in a plasma CVD film formation chamber, the cathodes 222 and 232 are generally used.
  • the cumulative film thickness of the residual film on the cathodes 222 and 232 is preferably 10 ⁇ m or more and 800 ⁇ m or less, and more preferably 300 ⁇ m or more and 500 ⁇ m or less, the residual film stacked on the cathode is removed. It is desirable to remove all.
  • the step of removing the residual film laminated on the cathodes 222 and 232 is performed by gas plasma in which hydrogen gas, inert gas, fluorine-based cleaning gas, or a mixed gas containing these gases at an arbitrary ratio is turned into plasma.
  • a fluorine-based cleaning gas such as nitrogen trifluoride because the etching rate of the residual film is relatively high.
  • a mixed gas of 10 volume% to 30 volume% nitrogen trifluoride gas and 90 volume% to 70 volume% argon gas is introduced as an etching gas, and plasma discharge is performed at a pressure of 300 pa or less, thereby causing 10 nm.
  • the etching rate can be higher than / s.
  • the conductive film 3 made of, for example, ZnO is formed on the second n-type semiconductor layer 23 of the double pin structure laminate 30, and then A metal electrode 4 made of, for example, Al or Ag is formed on the conductive film 3.
  • the back electrode portion is constituted by the conductive film 3 and the metal electrode 4 to complete the photoelectric conversion device.
  • the apparatus can be operated over a long period of time without opening the film forming chamber, so that the tact time during manufacturing can be greatly reduced, and the manufacturing cost can be reduced. Can be lowered.
  • the silicon-based thin film photoelectric conversion device of the present invention manufactured in the above first to fourth embodiments includes, for example, the first n-type semiconductor layer 13 and the second p-type semiconductor layer 21 in the amorphous pin structure stacked body.
  • the first n-type semiconductor layer 13, the p-type semiconductor layer 21, and the n-type semiconductor layer 43 each have an impurity nitrogen atom concentration of 1 ⁇ 10 19 cm ⁇ 3 or less, and The impurity oxygen atom concentration is 1 ⁇ 10 20 cm ⁇ 3 or less.
  • the first n-type semiconductor layer 13 and the second p-type semiconductor layer 21 are each doped with impurity nitrogen.
  • a stacked silicon thin film photoelectric conversion device having a high photoelectric conversion efficiency with an atomic concentration of 1 ⁇ 10 19 cm ⁇ 3 or less and an impurity oxygen atom concentration of 1 ⁇ 10 20 cm ⁇ 3 or less is obtained.
  • a silicon-based thin film photoelectric conversion device having good performance can be easily manufactured at low cost and efficiently.

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Abstract

L'invention porte sur un procédé de fabrication d'un dispositif de conversion photoélectrique à film mince au silicium ayant des qualités excellentes et un rendement de conversion photoélectrique élevé à bas coût et haut rendement à l'aide d'un appareil de fabrication simple. Dans un premier mode du procédé, une étape de formation d'u corps stratifié à structure pin amorphe (10) comprenant une première couche semi-conductrice de type p (11), une couche de conversion photoélectrique au silicium amorphe de type i (12) et une première couche semi-conductrice de type n (13), et une étape de formation d'un corps stratifié à structure pin de type cristallin (20) comprenant une seconde couche semi-conductrice de type p (21), une couche de conversion photoélectrique au silicium cristallin de type i (22) et une seconde couche semi-conductrice de type n (23) sont exécutées dans des chambres de formation de film par dépôt chimique en phase vapeur (CVD) activé par plasma, respectivement, au moyen d'une formation de film en chambre unique. L'étape de formation du corps stratifié à structure pin amorphe (10) est caractérisée en ce que le corps stratifié est formé dans les conditions de pression de formation de film dans une première chambre de formation de film par dépôt chimique en phase vapeur (CVD) par plasma (230) de 200 Pa ou plus mais inférieur ou égal à 3000 Pa et de densité de puissance par unité de surface d'électrode de 0,01 W/cm² ou plus mais inférieur ou également à 0,3 W/cm².
PCT/JP2009/070101 2008-12-01 2009-11-30 Dispositif de conversion photoélectrique à film mince au silicium et son procédé de fabrication Ceased WO2010064599A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563223A (ja) * 1991-09-04 1993-03-12 Kanegafuchi Chem Ind Co Ltd 非単結晶タンデム型太陽電池の製法及びそれに用いる製造装置
JP2000252496A (ja) * 1999-02-26 2000-09-14 Kanegafuchi Chem Ind Co Ltd タンデム型の薄膜光電変換装置の製造方法
WO2007040183A1 (fr) * 2005-10-03 2007-04-12 Sharp Kabushiki Kaisha Convertisseur photoélectrique à film mince à base de silicium, procédé et appareil de fabrication de celui-ci
WO2008099524A1 (fr) * 2007-02-16 2008-08-21 Mitsubishi Heavy Industries, Ltd. Convertisseur photoélectrique et son procédé de fabrication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090013599A1 (en) * 2007-07-10 2009-01-15 Peter Cordani Water retention mixture and method for spray application

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563223A (ja) * 1991-09-04 1993-03-12 Kanegafuchi Chem Ind Co Ltd 非単結晶タンデム型太陽電池の製法及びそれに用いる製造装置
JP2000252496A (ja) * 1999-02-26 2000-09-14 Kanegafuchi Chem Ind Co Ltd タンデム型の薄膜光電変換装置の製造方法
WO2007040183A1 (fr) * 2005-10-03 2007-04-12 Sharp Kabushiki Kaisha Convertisseur photoélectrique à film mince à base de silicium, procédé et appareil de fabrication de celui-ci
WO2008099524A1 (fr) * 2007-02-16 2008-08-21 Mitsubishi Heavy Industries, Ltd. Convertisseur photoélectrique et son procédé de fabrication

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