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WO2010058836A1 - Dispositif d’affichage et système de télévision - Google Patents

Dispositif d’affichage et système de télévision Download PDF

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Publication number
WO2010058836A1
WO2010058836A1 PCT/JP2009/069697 JP2009069697W WO2010058836A1 WO 2010058836 A1 WO2010058836 A1 WO 2010058836A1 JP 2009069697 W JP2009069697 W JP 2009069697W WO 2010058836 A1 WO2010058836 A1 WO 2010058836A1
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WO
WIPO (PCT)
Prior art keywords
circuit
self
output
signal
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2009/069697
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English (en)
Japanese (ja)
Inventor
伸介 安西
好博 中谷
宏晃 藤野
裕文 松井
雅美 森
浩一 細川
利男 渡部
昌史 勝谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Publication date
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Publication of WO2010058836A1 publication Critical patent/WO2010058836A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H04N17/04—Diagnosis, testing or measuring for television systems or their details for receivers
    • H04N17/045—Self-contained testing apparatus
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

  • the present invention relates to a display device using a drive circuit that performs self-detection and self-repair of a defect in a DA converter output circuit.
  • FIG. 32 is a block diagram showing a configuration of a conventional semiconductor integrated circuit for driving a liquid crystal.
  • the liquid crystal driving semiconductor integrated circuit 101 shown in the figure can output m gray scale output voltages from n liquid crystal driving signal output terminals.
  • a liquid crystal driving semiconductor integrated circuit 101 includes an external clock input terminal 102, a gradation data input terminal 103 having a plurality of signal input terminals, a LOAD signal input terminal 104, and V0 terminals 105 and V1 terminals which are reference power supply terminals. 106, a V2 terminal 107, a V3 terminal 108, and a V4 terminal 109.
  • the liquid crystal driving semiconductor integrated circuit 101 includes n liquid crystal driving signal output terminals 111-1 to 111-n (hereinafter, the liquid crystal driving signal output terminals are referred to as signal output terminals. Terminals 111-1 to 111-n are collectively referred to as signal output terminal 111).
  • the liquid crystal driving semiconductor integrated circuit 101 includes a reference power correction circuit 121, a pointer shift register circuit 123, a latch circuit unit 124, a hold circuit 125, and a D / A converter (Digital Analog Converter: hereinafter referred to as DAC) circuit. 126 and an output buffer 127.
  • the pointer shift register circuit 123 includes n stages of shift register circuits 123-1 to 123-n.
  • the latch circuit unit 124 includes n latch circuits 124-1 to 124-n, and the hold circuit 125 includes n hold circuits 125-1 to 125-n.
  • the DAC circuit 126 is composed of n DAC circuits 126-1 to 126-n.
  • the output buffer 127 includes n output buffers 127-1 to 127-n, and each output buffer includes an operational amplifier.
  • the pointer shift register circuit 123 sequentially selects from the first latch circuit 124-1 to the nth latch circuit 124-n based on the clock input signal input from the clock input terminal 102.
  • the latch circuit 124 selected by the pointer shift register circuit 123 stores the gradation output data from the gradation data input terminal 103.
  • the gradation output data corresponds to each latch circuit 124, in other words, corresponds to each signal output terminal 111 and is data synchronized with the clock input signal. Accordingly, each of the latch circuits 124-1 to 124-n can store gradation output data having different values corresponding to each signal output terminal 111.
  • the gradation output data stored in the latch circuits 124-1 to 124-n is transferred to the corresponding n number of hold circuits 125-1 to 125-n by the data LOAD signal. Further, the hold circuits 125-1 to 125-n output the gradation output data input from the latch circuits 124-1 to 124-n to the DAC circuits 126-1 to 126-n as digital data.
  • the DAC circuits 126-1 to 126-n select one voltage value among m kinds of gradation voltages based on the gradation output data from the hold circuit 125, and output buffers 127-1 to 127- output to n.
  • the DAC circuit 126 can output m types of gradation voltages depending on voltages input from the reference power supply terminal V0 terminal 105 to the V4 terminal 109.
  • the output buffer 127 buffers the gradation voltage from the DAC circuit 126 and outputs it as a liquid crystal panel drive signal to the signal output terminals 111-1 to 111-n.
  • the same number of shift register circuits 123, latch circuits 124, hold circuits 125, DAC circuits 126, and output buffers 127 as the liquid crystal drive signal output terminals 111 are required, and the liquid crystal drive signal output terminals 111 are 1000 in number. If it is a terminal, 1000 of each of the circuits 124 to 127 is required.
  • the display driving semiconductor integrated circuit needs to give a signal of gradation voltage of R, G, B for each data line.
  • the number of outputs of one display driving semiconductor integrated circuit is 720, eight display driving semiconductor integrated circuits are required.
  • a semiconductor integrated circuit for display driving is tested at a wafer stage, is subjected to a shipping test after being packaged, and a display test is performed after being mounted on a liquid crystal panel. Furthermore, semiconductor integrated circuits that may cause initial failures are removed by screening tests such as burn-in and stress tests. Therefore, a display device on which a display driving semiconductor integrated circuit in which display failure occurs is not shipped to the market. However, a display defect rarely occurs while using the display device due to a very small defect or a foreign matter adhering and mixing that has not been determined to be defective during a pre-shipment test or a screening test.
  • the display defect occurrence rate is 57.6 ppm (57.6 / 1,000,000). That is, about one in about 17361 units will cause display defects, and the larger the size and the higher definition, the higher the rate of occurrence of display defects.
  • the display driving semiconductor integrated circuit is provided with a spare circuit provided for the defective circuit, and the defective circuit is switched to the spare circuit, so that the defect of the display driving semiconductor integrated circuit is eliminated. Avoidance is disclosed.
  • the display driving semiconductor integrated circuit includes a spare parallel circuit at each stage of the shift register, and performs a self-inspection of the shift register.
  • a technique for avoiding display defects caused by a defective shift register by selecting one having no defect is disclosed.
  • a selector is provided at the input and output of the DAC circuit, and the selector is switched based on the RAM information in which the position of the defective DAC circuit is stored, and a DAC circuit without a defect is selected. A method of using the same is disclosed.
  • Patent Document 1 and Patent Document 2 do not disclose any self-detection method for detecting a defect in an output circuit such as a DAC circuit.
  • Patent Document 3 discloses a technique for providing redundancy to a drive circuit of a product in which a drive circuit is integrated with a display panel and restoring the drive circuit even after the product is completed.
  • a spare output is provided for the drive output in the drive circuit, and one output of the drive output is compared with the spare output, and the output circuit determines whether the output values are equal.
  • the display panel is driven by a spare output circuit instead of the output circuit to be diagnosed during self-detection.
  • Japanese Patent Publication Japanese Patent Laid-Open No. 6-208346 (published July 26, 1994)” Japanese Patent Publication “Japanese Patent Laid-Open No. 8-278771 (published on October 22, 1996)” Japanese Patent Gazette “Special Table 2004-511022 (April 8, 2004)”
  • the drive circuit to be diagnosed is separated from the display panel, the display panel is driven by the spare drive circuit, and the output of the spare drive circuit and the drive circuit to be diagnosed are The output is compared to determine whether the drive circuit to be diagnosed is good or bad.
  • image data representing an image to be displayed to the drive circuit to be diagnosed and the spare drive circuit an image is displayed on the display panel by the spare drive circuit, and the drive circuit to be diagnosed is also displayed.
  • Self-detection can be performed. That is, when the analog clamp voltage is selected and output as in the configuration of Patent Document 3, a part of the data is compared with the display data, so that the difference between the output circuits can be detected.
  • the data for comparing the output of the spare drive circuit and the output of the drive circuit to be diagnosed is limited to the image data to be displayed.
  • a DA converter circuit that outputs a voltage corresponding to the digital data is required.
  • a driver circuit for 256 gradation display requires a DA converter circuit that selects 256 voltages. Therefore, in order to detect a malfunction of the DA conversion circuit, it is necessary to compare all input data corresponding to 256 voltage outputs.
  • the present invention has been made in view of the above problems, and its object is to provide a display device provided with a drive circuit capable of self-detecting and self-repairing defects in an output circuit and an output block around the output circuit. It is an object of the present invention to provide a display device that performs self-detection and self-repair at an appropriate timing without disturbing viewing.
  • a display device is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected.
  • Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
  • the drive circuit drives the display panel.
  • the drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure.
  • the drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels.
  • Self-detection processing can be executed using the key data.
  • the image may be a still image or a moving image, that is, a video.
  • a self-detection / self-repair means performs the process which detects the defect of a drive circuit, when the image which should be displayed on the said display panel switches discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously. A process for detecting a circuit defect is executed. Further, for example, the self-detecting / self-recovery means is driven when the image to be displayed on the display panel is switched discontinuously when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM. A process for detecting a circuit defect is executed.
  • the self-detection process can be executed in a period that does not affect the display.
  • the display device according to the present invention executes a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the current display content is temporarily interrupted on the screen of the display device. Since the self-detection process is executed at the timing, the user does not feel uncomfortable. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
  • the display device includes a display panel, a supply period in which an image signal is supplied, and a supply stop period in which the supply of the image signal is stopped, among periods in which an image is displayed on the display panel.
  • Drive circuit for driving the display panel while switching between them, and having self-detection / self-repair means for detecting and repairing a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected
  • the self-detecting / self-repairing means executes a process of detecting a defect of the driving circuit during the supply stop period.
  • the drive circuit switches between the supply period in which the image signal is supplied and the supply stop period in which the supply of the image signal is stopped, during the period in which the image is displayed on the display panel. While driving the display panel.
  • the drive circuit can detect a failure of the drive circuit itself, and has self-detection / self-repair means for repairing the detected failure.
  • the drive circuit executes processing for detecting and repairing its own defect in a state where the electrical connection with the display panel is disconnected. In other words, the drive circuit disconnects the electrical connection with the display panel and detects its own defect (that is, self-detection), so that not only the gradation data representing the image being displayed on the display panel but also all levels. Self-detection processing can be executed using the key data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit during the supply stop period.
  • the self-detecting / self-repairing unit executes processing for detecting a defect in the driving circuit in the horizontal scanning period and the vertical scanning period.
  • the display device According to the display device according to the present invention, it is possible to execute the self-detection process in a period in which the display device is driven and does not affect the display. That is, the display device according to the present invention performs a process of detecting a defect in the drive circuit in a state where the electrical connection with the display panel is disconnected, but the image signal is supplied to the display panel that is displaying an image. Since the self-detection process is executed at a timing that is not performed, driving of the display panel is not hindered. Therefore, according to the display device of the present invention, it is possible to execute self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved. .
  • a display device is a drive circuit for driving a display panel and the display panel, and the drive circuit is in a state where electrical connection with the display panel is disconnected.
  • Drive circuit having self-detection / self-repair means for detecting and repairing a defect of the display device, and the self-detection / self-repair means is configured to switch the drive circuit when an image to be displayed on the display panel is switched discontinuously. It is characterized in that a process for detecting a defect is executed.
  • the display device includes a display panel, a supply period in which an image signal is supplied, and a supply stop in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel.
  • the self-detecting / self-repairing means is characterized by executing a process of detecting a defect of the driving circuit during the supply stop period.
  • the display device According to the display device according to the present invention, at the timing when the content currently displayed on the screen of the display device is temporarily interrupted, or at the timing when the image signal is not supplied to the display panel displaying the image, Since the self-detection process is executed, it is possible to execute the self-detection and self-repair processes at an appropriate timing without disturbing the user's viewing, and the convenience for the user can be improved.
  • FIG. 1 is a block diagram illustrating a configuration of a liquid crystal television according to an embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus based on one Embodiment of this invention. It is a figure which shows an example of a display when abnormality generate
  • a liquid crystal television it is a figure which shows a mode that self-detection and a self-repair operation
  • (c) is a figure which shows the mode after a channel change.
  • a liquid crystal television it is a figure which performs a mode that self-detection and a self-repair operation are performed at the time of CM shift
  • (a) is a diagram showing a state before CM shift
  • (b) is a state during a self-detection operation.
  • (c) is a figure which shows the mode in CM
  • (d) is a figure which shows the mode at the time of program resumption. It is a timing chart showing the signal for driving the display panel of a liquid crystal television.
  • FIG. 3 is a time chart according to an embodiment of the present invention, in which (a) to (f) are a scanning signal, a video signal, and a voltage value of a pixel electrode input to a display device according to an embodiment of the present invention.
  • FIG. It is a block diagram which shows the structure of the operation
  • Embodiment 1 A first embodiment of the present invention will be described below with reference to FIGS.
  • liquid crystal television 400 As a typical display device using a display driving circuit, a thin-screen television typified by a liquid crystal television can be given.
  • a liquid crystal television (liquid crystal display device) performs display by mounting a plurality of drive circuits created with a semiconductor integrated circuit (LSI) on a display panel.
  • LSI semiconductor integrated circuit
  • the user recognizes it as a direct display defect.
  • it is necessary to repair the defective part promptly, and it is desirable that the repair be completed in a short time at the place where the user is using if possible.
  • the present applicant has proposed a display driving circuit having a self-diagnosis self-repair function (self-detection and self-repair function) for a failure of the display drive circuit itself (for example, Japanese Patent Application No. 2008-130848, Application Nos. 2008-048640, Japanese Patent Application No. 2008-048639, and Japanese Patent Application No. 2008-054130: all unpublished at the time of confirmation prior to the filing of this application.
  • FIG. 1 shows a block diagram showing a configuration of a liquid crystal television 400 according to the present invention.
  • the liquid crystal television 400 includes a TFT-LCD module (display unit) 90 and a remote control I / F 401.
  • the display unit 90 includes source drivers (driving circuits, integrated circuits) 10a and 10b, a TFT-LCD panel (display panel) 80, a gate driver 99, and a controller 100.
  • the source driver 10a that is, the integrated circuits 10a and 10b is a display driving circuit having the above-described self-detection and self-repair functions.
  • the integrated circuits 10a and 10b that is, the generic names of the source drivers 10a and 10b are represented.
  • FIG. 2 is a block diagram illustrating a schematic configuration of the display unit 90.
  • the display unit 90 includes a display panel 80 and a display driving semiconductor integrated circuit (hereinafter referred to as an integrated circuit or a source driver) that drives the display panel 80 based on gradation data input from the outside. ) 10.
  • the source driver that is, the integrated circuit 10 (driving circuit) includes a switching circuit 60 (self-detection / self-repairing means, switching means), a switching circuit 61 (self-detection / self-repairing means, switching means), and an output circuit block 30 (output).
  • the display panel 80 includes a pixel 70 to which the gradation voltage from the integrated circuit 10 is applied.
  • the display unit 90 has two basic operations as basic operations. Specifically, in the display unit 90, the integrated circuit 10 converts gradation data input from the outside into a gradation voltage (output signal), and displays an image on the display panel 80 based on the gradation voltage. A normal operation and a self-detection / repair operation in which the integrated circuit 10 detects whether or not the output circuit block 30 included in the integrated circuit 10 is defective and the output circuit block 30 is defective. It has two basic operations.
  • gradation data for operation confirmation is input to the output circuit block 30 and the spare output circuit block 40 from the outside via the switching circuit 61.
  • Each of the output circuit block 30 and the spare output circuit block 40 converts the input gradation data into a gradation voltage and outputs the gradation voltage to the comparison determination circuit.
  • the comparison determination circuit 50 compares the gradation voltage from the output circuit block with the gradation voltage from the standby output circuit block, and determines whether or not the output circuit block is defective based on the comparison result.
  • the comparison / determination circuit 50 outputs a determination result (failure detection information) indicating whether or not the output circuit block is defective to the switching circuit 61 and the switching circuit 60.
  • the switching circuit 61 switches the output destination of the gradation data from the outside based on the determination result from the comparison determination circuit 50.
  • the switching circuit 60 receives the gradation voltage from each of the output circuit block 30 and the spare output circuit block 40, and displays the display panel from the inputted gradation voltages based on the determination result from the comparison determination circuit.
  • the gradation voltage to be output to 80 is selected.
  • the switching circuit 61 when the determination result indicating that the output circuit block 30 is defective is input, the switching circuit 61 has the same level as the gradation data output to the output circuit block 30 determined to be defective. The tone data is also input to the spare output circuit block 40.
  • the switching circuit 60 when a determination result indicating that the output circuit block 30 is defective is input to the switching circuit 60, instead of the gradation voltage from the output circuit block 30 determined to be defective, the switching circuit 60 outputs from the standby output circuit 40. The gradation voltage is output to the display panel 80. As a result, even if the output circuit block 30 becomes defective, the integrated circuit 10 can output a normal gradation voltage to the display panel 80 using the spare output circuit block instead.
  • the integrated circuit 10 includes the comparison determination circuit 50, the switching circuit 60, and the switching circuit 61, so that it can detect its own defect and can self-repair itself. It becomes.
  • the integrated circuit 10 includes a self-healing circuit (self-repairing means) that detects its own fault and further self-heals the fault.
  • the configuration of the source driver 10, that is, the integrated circuit 10, and details of self-detection and self-repair operations will be described later.
  • FIG. 3 is a diagram illustrating an example of a display when an abnormality occurs in the output circuit block 30 included in the integrated circuit 10 included in the liquid crystal television 400. As shown in FIG. 3, when there is an abnormality in the output circuit block 30, a vertical line appears on the display.
  • the self-recovering operation is instantaneously executed by the self-recovery function of the display driving device so that the vertical stripe in FIG. 3 disappears.
  • FIG. 4 is a diagram showing how the liquid crystal television 400 performs self-detection and self-repair operations when a channel is changed.
  • FIG. 4A is a diagram showing a state before the channel is changed.
  • FIG. 4B is a diagram showing a state during the self-detection operation, and
  • FIG. 4C is a diagram showing a state after the channel change.
  • the liquid crystal television 400 when the user performs a channel change operation using the remote controller 402, a channel selection input signal is received via the remote control I / F 401, the channel selection input signal is converted into a channel selection voltage, and a tuner ( Broadcast receiving means).
  • the tuner receives a broadcast signal of a channel corresponding to the channel selection voltage. Then, the liquid crystal television 400 displays the program of the channel received by the tuner.
  • the liquid crystal television 400 first receives and displays a 1ch (one channel) program as shown in FIG.
  • the liquid crystal television 400 starts a self-detecting operation.
  • the display on the screen disappears as shown in FIG.
  • the self-detection of the source driver 10 is performed when the channel is switched from 1ch to 2ch, that is, when the display based on the image signal representing the 1ch program is interrupted.
  • the controller 100 shown in FIG. 1 senses the user's channel selection operation, that is, switching from 1ch to 2ch.
  • the controller 100 image switching means
  • the controller 100 When the controller 100 senses channel switching, it instructs the source driver 10 to execute self-detection processing, and the source driver 10 executes self-detection processing. That is, in the liquid crystal television 400, in order to switch from display based on an image signal representing a 1ch program on the display panel 80 to display based on an image signal representing a 2ch program, an image signal representing a 1ch program is displayed. When the display based on is interrupted, the self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 instructs the source driver 10 to perform self-detection processing based on a channel selection input signal input via the remote control I / F.
  • FIG. 4 shows an example of channel switching from 1ch to 2ch.
  • the display based on the image signal representing the 1ch program is temporarily interrupted.
  • the source driver 10 executes self-detection processing in accordance with an instruction from the controller 100 based on the channel selection input signal, for example.
  • the liquid crystal television 400 is a digital television
  • the video signal and audio signal are encoded and transmitted as a digital broadcast wave, so that the compressed video signal and audio signal included in the received digital broadcast wave are decoded.
  • the program of the designated channel is not displayed immediately, but is displayed for a short period of time. Is displayed. Therefore, if self-detection is performed at this timing, the user does not feel uncomfortable. That is, the liquid crystal television 400 completes self-detection in a period that does not affect the display.
  • the liquid crystal television 400 displays the switched program, that is, the 2ch program, as shown in FIG.
  • FIG. 5 is a diagram illustrating a state in which the liquid crystal television 400 performs self-detection and self-repair operations during the transition to CM.
  • FIG. 5A illustrates a state before the transition to CM.
  • FIG. 5B is a diagram showing a state during the self-detection operation
  • FIG. 5C is a diagram showing a state during the CM
  • FIG. 5D is a diagram showing a state when the program is resumed.
  • the liquid crystal television 400 first receives a 1ch broadcast and displays a program included in the 1ch broadcast, as shown in FIG.
  • the liquid crystal television 400 starts a self-detection operation.
  • the display on the screen disappears as shown in FIG.
  • the self-detection of the source driver 10 is performed at the time of transition from the program to the CM, that is, when the display based on the image signal representing the program is interrupted.
  • the controller 100 shown in FIG. 1 senses a transition from a program to a CM.
  • the controller 100 image switching means
  • the source driver 10 is instructed to execute the self-detection process, and the source driver 10 executes the self-detection process. That is, in the liquid crystal television 400, when the display based on the image signal representing the program is interrupted on the display panel 80 in order to shift from the display based on the image signal representing the program to the display based on the image signal representing the CM.
  • the self-detection process of the source driver 10 is executed. At this time, for example, the controller 100 performs scene detection, detects a CM based on the result, and instructs the source driver 10 to perform self-detection processing.
  • Scene detection is a function that detects not only silence and stereo / monaural audio, but also “sound switching” such as the boundary between music and conversation and “video switching” with large scene changes.
  • Scene detection is a technique used when, for example, a CM part is chapter-divided by a hard disk decoder or the like.
  • the liquid crystal television 400 displays a CM as shown in FIG. Thereafter, in the liquid crystal television 400, as shown in FIG. 4D, the program is resumed, and the display shifts from the CM to the program.
  • the self-detection process may include a plurality of steps.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one channel switching.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one transition from a program to a CM.
  • the process may be divided and all the processes included in the self-detection process may be completed by changing the channel several times.
  • the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one channel switching.
  • the time of the self-detection process executed at the time of one channel change can be shortened, and a situation in which the period during which screen display is not performed after the channel switching operation becomes too long can be avoided.
  • the self-repair processing may be divided into a plurality of process groups including one or more processes, and the process groups may be executed one by one in one transition from the program to the CM. .
  • the process included in the self-repair process is divided into n process groups
  • the process of one process group that is, 1 / n of the self-detection process is performed in one channel switching.
  • processing of n process groups that is, all processes of self-detection are completed.
  • the process included in the self-repair process is divided into n process groups
  • the process of one process group that is, 1/1 of the self-detection process is performed in switching from one program to CM. n.
  • the process of n process groups that is, all processes of self-detection are completed by shifting to CM for n times.
  • the self-detection process includes a plurality of steps, details will be described later.
  • one gradation data is obtained.
  • steps for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit
  • several types of processes are performed for all the gradation data.
  • such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is performed for each channel switching. And the self-detection process for one gradation is completed by switching the channel twice.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each CM transition, and one gradation is obtained by two CM transitions.
  • the self-detection process may be completed.
  • the process which comprises each process group may be preset, and the structure by which the setting information is memorize
  • the source driver 10 when executing the self-detection process, the source driver 10 reads the setting information from the memory, and executes the process group process one by one for each channel switching.
  • the number of processes constituting each process group may be set in advance, and the source driver 10 may be configured to execute the set number of processes for each channel switching.
  • the display panel 80 shown in FIG. 1 constitutes the display unit 90 together with the controller 100, the gate driver 99, and the source dry 10.
  • the display panel 80 has a plurality of gate lines (scanning signal lines) and a plurality of source lines (data signal lines) orthogonal to the gate lines, and at the intersections of these gate lines and source lines, respectively.
  • a pixel portion including a switching element and a liquid crystal capacitor is provided. That is, in the display panel 80, the pixel portions are arranged in a matrix.
  • a gate line is connected to the gate terminal, a source line is connected to the source terminal, and a pixel electrical connection is connected to the drain terminal.
  • a common counter electrode is provided in all the pixel formation portions so as to face the pixel electrode, and the pixel electrode and the counter electrode form a liquid crystal capacitor with a liquid crystal layer interposed therebetween.
  • the pixel electrode is given a potential according to the image to be displayed by the source line and the gate line, and a predetermined potential is given to the common electrode. By applying this voltage, the amount of light transmitted to the liquid crystal layer is controlled, whereby image display is performed. Note that a deflection plate may be used to control the amount of light transmitted by applying a voltage to the liquid crystal layer.
  • FIG. 6 is a timing chart showing signals for driving the display panel 80 of the liquid crystal television 400.
  • Various control signals shown in FIG. 6 are supplied to the controller 100.
  • the controller 100 controls the gate driver 99 and the source driver 10 based on the control signal shown in FIG.
  • the gate driver 99 and the source driver 10 supply a gate signal and a data signal to the display panel 80. Thereby, the display panel 80 is driven.
  • a period 501 is a vertical period
  • a period 502 is a vertical data valid period
  • a period 503 is a vertical blanking period
  • a period 504 is a horizontal period
  • a period 505 is a horizontal data valid period
  • a period 506 is a horizontal blanking period.
  • a period 507 is a vertical effective data start period indicating a period from the input of the vertical synchronization signal to the start of effective data
  • a period 508 is a horizontal effective data indicating a period from the input of the horizontal synchronization signal to the start of effective data. Indicates the data start period.
  • the gate lines are sequentially selected by the gate driver 99 based on the horizontal synchronization signal and supplied with the scanning signal. Then, the gate of the switching element connected to the gate line to which the scanning signal is supplied is turned ON, and an active state in which a data signal can be supplied to the pixel electrode connected to the switching element is obtained. As a result, a data signal is supplied to the pixel electrode from the source driver 10 via the source line, and a voltage representing an image is supplied.
  • a data signal is sequentially supplied from the left pixel to the right pixel for each line of the screen to form a scanning line.
  • the blanking period that is, the blanking period is the time for the scanning line that has scanned the screen to return to the original state.
  • the horizontal blanking period 506 is a time for scanning from left to right in one line of the screen and then returning to the left again.
  • the vertical blanking period 503 is performed while scanning from left to right sequentially from the upper left in all lines of the screen. This is the time from scanning to the lower right until returning to the upper left again.
  • the control signal period shown in FIG. 6 varies depending on the standard of the panel to be driven, the driving method, and the like, as an example, the vertical blanking period is 1.14 ms and the horizontal blanking period is 9 ⁇ s.
  • the data line is not driven, and no data signal is supplied to each pixel constituting the display panel 80.
  • image data is not written to each pixel during these periods, even if the output of the source driver 10 that is a display driving element is high impedance, it does not affect image display. Therefore, in the liquid crystal television 400, the source driver 10 is self-detected and self-repaired using these periods.
  • the controller 100 shown in FIG. 1 senses the horizontal blanking period 506 or the vertical blanking period 503 in response to the supply of the control signal shown in FIG.
  • controller 100 (period switching detection means) senses the horizontal blanking period 506 or the vertical blanking period 503
  • the controller 100 instructs the source driver 10 to execute self-detection processing, and the source driver 10 performs self-detection processing. Execute.
  • self-detection and self-repair are performed in real time because repair is performed for each line.
  • self-detection / self-repair is performed during the vertical blanking period 503 since the repair is performed for each screen, it can be said that self-detection / self-repair is performed in real time. That is, according to the liquid crystal television 400, the self-detection process can be executed in real time without disturbing the viewing of the user.
  • the controller 100 In the vertical blanking period 503, other information such as teletext may be supplied to the controller 100 or the like, but self-detection and self-restoration can be performed by the display driver, that is, the source driver 10 alone. Regardless of other devices such as the controller 100, self-detection and self-repair operations are possible.
  • the vertical blanking period is also called the vertical blanking period.
  • An example of self-detection in the vertical blanking period will be described later again.
  • the self-repairing process may include a plurality of steps.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one horizontal blanking period 506.
  • the liquid crystal television 400 may be configured to execute all the steps included in the self-repair process in one vertical blanking period 503.
  • the self-repair process is divided into a plurality of process groups including one or more processes, and the process groups are executed one by one in one horizontal blanking period 506 or vertical blanking period 503. May be.
  • the time of the self-detection process executed in one horizontal blanking period 506 or the vertical blanking period 503 is shortened, and the period during which the screen display is not performed after the channel switching operation becomes too long. Can avoid the situation.
  • n horizontal blanking period 506 or vertical blanking period 503 the process of one process group, that is, the self-detection process. Of 1 / n. Then, in n horizontal blanking periods 506 or vertical blanking periods 503, processing of n process groups, that is, all processes of self-detection are completed.
  • the self-detection process includes a plurality of steps, details will be described later.
  • one gradation data is obtained.
  • steps for example, a plurality of comparison steps for comparing the output from the output circuit and the output from the auxiliary output circuit
  • several types of processes are performed for all the gradation data.
  • such a drive circuit may have a configuration in which processes included in the self-detection process for one gradation are divided and processed.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process is performed for each horizontal blanking period 506.
  • the group processing is executed, and the self-detection processing for one gradation can be completed by two horizontal blanking periods 506.
  • the process included in the self-detection process for one gradation is divided into two process groups, and one process group process is executed for each vertical blanking 503, and the vertical blanking 503 is performed twice.
  • the self-detection process for one gradation may be completed.
  • the configuration of the source driver 10a according to the present invention will be described with reference to FIG.
  • the spare source driver 10b can have a simpler configuration than the source driver 10a, but can also have the same configuration as the source driver 10a.
  • a circuit capable of performing self-detection and self-recovery operations similar to those of the source driver 10a will be referred to as an integrated circuit 10 and will be described.
  • FIG. 7 is an explanatory diagram showing the configuration of the integrated circuit 10 (drive circuit).
  • the integrated circuit 10 includes n liquid crystal driving signal output terminals OUT1 to OUTn (hereinafter referred to as output terminals OUT1 to OUTn) via a data bus from a grayscale data input terminal (not shown).
  • N sampling circuits 6-1 to 6-n hereinafter collectively referred to as sampling circuit 6
  • n hold circuits 7-1 to 7-n hereinafter collectively referred to as a hold circuit 7
  • n DAC circuits 8-1 to 8-n hereinafter collectively referred to as “hold circuit 7” that convert gradation data into gradation voltage signals.
  • DAC circuit 8 n operational amplifiers 1-1 to 1-n (hereinafter collectively referred to as operational amplifier 1) having a role of a buffer circuit for the gradation voltage signal from the DAC circuit 8, n judgment circuits 3-1 3-n (hereinafter collectively referred to as determination circuit 3), n determination flags 4-1 to 4-n (hereinafter collectively referred to as determination flag 4), n number of determination flags Pull-up / pull-down circuits 5-1 to 5-n (hereinafter collectively referred to as pull-up / pull-down circuits 5) are provided.
  • the integrated circuit 10 includes a plurality of switches 2 a that are turned on and off by a test signal, a plurality of switches 2 b that are turned on and off by a test B signal, and an output signal from the determination flag 4.
  • switches 2c connection switching means
  • 2d connection switching means
  • the switches 2a, 2b, and 2d are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned off when an “H” signal is inputted, and is turned on when an “H” signal is inputted.
  • the integrated circuit 10 includes a spare sampling circuit 26, a spare hold circuit 27, a spare DAC circuit 28 (spare output circuit), and a spare operational amplifier 21, one for each circuit.
  • the sampling circuit 6, the hold circuit 7, and the DAC circuit 8 correspond to the output circuit block 30 shown in FIG. 2, and the sampling circuit 26, the hold circuit 27, and the DAC circuit 28 are shown in FIG.
  • the operational amplifier 1, the determination circuit 3, and the determination flag 4 correspond to the preliminary circuit block 40 shown, the comparison determination circuit 50 shown in FIG. 2, and the switches 2d and 2c connected to the output terminals OUT1 to OUTn. 2 corresponds to the switching circuit 60 shown in FIG. 2, and the switch 2d connected to the sampling circuit 6 corresponds to the switching circuit 61 shown in FIG.
  • the integrated circuit 10 shown in FIG. 7 is connected to the display panel 80 shown in FIG. 2 via output terminals OUT1 to OUTn, and the display panel 80 is not shown in FIG.
  • the test signal is “L” and the test B signal is “H”.
  • the switch 2a is turned off and the switch 2b is turned on.
  • the corresponding sampling circuits 6 input STR1 to STRn signals (hereinafter collectively referred to as STR signals), which are signals from a pointer shift register (not shown).
  • STR signals are signals from a pointer shift register (not shown).
  • the sampling circuit 6 acquires gradation data corresponding to itself from the gradation data input terminal via the data bus.
  • the hold circuit 7 inputs the gradation data acquired by the sampling circuit 6 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 (output circuit) inputs gradation data from the hold circuit 7.
  • the DAC circuit 8 converts the input gradation data into a gradation voltage signal, and outputs the gradation voltage signal to the positive input terminal of the operational amplifier 1 (comparing means).
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 serves as a buffer circuit for the grayscale voltage from the DAC circuit 8, and the grayscale voltage signal input to its positive input terminal is used as the corresponding output terminals OUT1 to OUTn. Output to.
  • the switch 2c is ON and the switch 2d is OFF. The operation of the switches 2c and 2d will be described later.
  • the output circuit block has gradation
  • An object of the present invention is to convert gradation data input from a data input terminal into a gradation voltage for driving the display panel 80, and to output the converted gradation voltage to the display panel 80 via an output terminal.
  • test signal and the test B signal are output from a control circuit (not shown) that controls switching of the operation check test and operation of the operation check test.
  • the control circuit is also a circuit for controlling gradation data and a data LOAD signal input via the data bus in the operation check test. Further, the control circuit may be the same as or different from the control circuit that controls the gradation data, the data LOAD signal, and the shift clock input signal during normal operation.
  • FIG. 8 is a flowchart showing a first procedure of the operation check test according to the first embodiment.
  • step S21 (hereinafter abbreviated as S21) shown in the figure, the test signal is set to “H” and the test B signal is set to “L”.
  • the operational amplifier 1 serves as a comparator by S21.
  • a counter m provided in a control circuit (not shown) is initialized to zero. Further, the control circuit activates the gradation data corresponding to the value of the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR1 signal, and the spare sampling circuit 26 via the data bus. To store. Further, the control circuit samples the gradation data of gradation m + 1 obtained by adding 1 to the value of the counter m, the gradation data of gradation 1 here, the TSTR2 signal active, and the data via the data bus. Store in circuit 6. Next, the spare hold circuit 27 acquires gradation data of gradation 0 from the sampling circuit 26 based on the data LOAD signal.
  • the DAC circuit 28 receives the gradation data from the hold circuit 27 and outputs a gradation voltage of gradation 0 to the negative input terminal of the operational amplifier 1 (S23).
  • the hold circuit 7 acquires gradation data of gradation 1 from the sampling circuit 6 based on the data LOAD signal.
  • the DAC circuit 8 inputs gradation data from the hold circuit 7.
  • Each DAC circuit 8 outputs a gradation voltage of gradation 1 to the positive input terminal of each operational amplifier 1 connected in series with itself (S23).
  • the integrated circuit 10 of the present invention outputs an n gradation voltage, the gradation voltage of gradation 0 is the lowest voltage value, and the gradation voltage of gradation n is the lowest. It is assumed that the voltage value is high.
  • the operational amplifier 1 compares the gradation voltage from the DAC circuit 8 input to the positive input terminal and the gradation voltage from the DAC circuit 28 input to the negative input terminal (S24). Specifically, the operational amplifier 1 inputs a gradation voltage of gradation 1 to its own positive input terminal, and inputs a gradation voltage of gradation 0 to its own negative input terminal. If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs an “H” level signal. Here, if the output of the operational amplifier is an “L” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 (determination means) receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. Note that the expected value stored by the determination circuit 3 is given by the control circuit. In this operation check test 1, the determination circuit 3 stores the expected value as the “H” level.
  • the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is at the “H” level, which is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “L” level, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory. (S25) The determination circuit 3 receives the output signal from the operational amplifier 1 and outputs an “L” flag to the determination flag 4 if the input signal is “H” level, and the input signal is “L” level.
  • the configuration may be such that the “H” flag is output to the determination flag 4.
  • the determination flag 4 holds the “H” flag even if the “L” flag is input from the determination circuit 3 thereafter. Continue.
  • the subsequent determination operation may not be performed.
  • n is the number of gradations that the integrated circuit 10 can output.
  • FIG. 9 is a flowchart showing a second procedure of the operation check test according to the first embodiment.
  • the determination circuit 3 outputs an “L” flag indicating normality.
  • the operation check test 2 is performed by inputting a gradation voltage lower than that of the negative input terminal to the positive input terminal of the operational amplifier 1.
  • the control circuit activates the TSTR1 signal for the gradation data of gradation m + 1, in this case, the gradation data of gradation m + 1 by adding 1 to the value of the counter m, and reserves the data via the data bus. Is stored in the sampling circuit 26.
  • the control circuit activates the gradation data corresponding to the counter m, the gradation data of gradation m, here the gradation data of gradation 0, and the TSTR2 signal to the sampling circuit 6 via the data bus. Store.
  • the DAC circuit 28 inputs the gradation data stored in the sampling circuit 26 via the hold circuit 27. Further, the DAC circuit 28 outputs the gradation voltage of gradation m + 1 corresponding to the inputted gradation data, here, the gradation voltage of gradation 1 to the negative input terminal of the operational amplifier 1.
  • the DAC circuit 8 inputs the gradation data stored by the sampling circuit 6 via the hold circuit 7. Further, each DAC circuit 8 has a gradation voltage of gradation m corresponding to the inputted gradation data, here a gradation voltage of gradation 0, of each operational amplifier 1 connected in series to itself. Output to the positive input terminal (S32).
  • the operational amplifier 1 compares the gradation voltage of gradation 0 from the DAC circuit 8 input to the positive input terminal with the gradation voltage of gradation 1 from the DAC circuit 28 input to the negative input terminal. (S33). If the DAC circuit 8 is normal, the gradation voltage of gradation 1 is higher than the gradation voltage of gradation 0, so that the operational amplifier 1 outputs a signal of the “L” flag. Here, if the output of the operational amplifier is an “H” level signal, the DAC circuit 8 is defective.
  • the determination circuit 3 receives the output signal from the operational amplifier 1 and compares the level of the input signal with the expected value stored by itself. In this operation check test 1, the determination circuit 3 stores the expected value as the “L” level. Here, the determination circuit 3 determines that the DAC circuit 8 is normal if the signal input from the operational amplifier 1 is the “L” level that is the same as the expected value stored by itself. On the other hand, if the signal input from the operational amplifier 1 is “H”, the determination circuit 3 determines that the DAC circuit 8 is defective and outputs an “H” flag to the determination flag 4. When the “H” flag is input from the determination circuit 3, the determination flag 4 stores the input “H” flag in its own internal memory (S34). The above steps S33 to S34 are repeated until the value of m becomes n ⁇ 1 (S35, S36).
  • FIG. 10 is a flowchart showing a third procedure of the operation check test according to the first embodiment.
  • the operational amplifier 1 when there is a problem that the output is open, the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 by the executed confirmation test, and the malfunction is confirmed in the operation confirmation tests 1 and 2. It may not be detected.
  • the operation check test 3 a pull-down circuit is connected to the positive input terminal of the operational amplifier 1.
  • a low voltage is input to the positive input terminal of the operational amplifier 1.
  • the operational amplifier 1 continues to hold the gradation voltage input to the operational amplifier 1 according to the executed confirmation test. Can be prevented.
  • the specific procedure of the operation check test 3 is as follows. First, the counter m is initialized to 0 (S41). Next, the pull-up / pull-down circuit 5 pulls down the positive input terminal of the operational amplifier 1 (S42). Steps S43 to S47 from here are the same as the steps S23 to S27 of the operation check test 1 already described above, and the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling down the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 1, the operational amplifier 1 outputs the “L” level signal. Will be output. As a result, the determination circuit 3 determines from the inputted “L” level signal that the DAC circuit 8 is defective, and the determination flag 4 stores the “H” flag.
  • FIG. 11 is a flowchart showing a fourth procedure of the operation check test according to the first embodiment.
  • the operation check test 4 is for dealing with a problem that the output of the DAC circuit 8 is open.
  • the counter m is initialized to 0 (S51).
  • the pull-up / pull-down circuit 5 pulls up the positive input terminal of the operational amplifier 1 (S52).
  • the subsequent steps S53 to S57 are the same as the steps S32 to S36 of the operation check test 2 already described above, and therefore the description thereof is omitted here.
  • the operational amplifier 1 when the output of the DAC circuit 8 is opened by pulling up the positive input terminal of the operational amplifier 1 and performing the procedure of the operation check test 2, the operational amplifier 1 outputs the “H” level signal. Will be output. As a result, the determination circuit 3 determines that the DAC circuit 8 has a problem from the input “H” level signal, and the determination flag 4 stores “H”.
  • FIG. 12 is a flowchart showing the fifth procedure of the operation check test according to the first embodiment.
  • the DAC circuit 8 there may be a problem that two adjacent gradations in itself are short-circuited. As described above, when two adjacent gradations are short-circuited, the DAC circuit 8 outputs an intermediate voltage between the two short-circuited gradations. In the case of this defect, the gradation voltage output from the DAC circuit 8 does not cause a voltage shift of one gradation or more compared to a normal case. Therefore, this malfunction cannot be detected in the operation confirmation tests 1 to 4.
  • the purpose of the operation check test 5 is to detect a problem in which the two adjacent gradations in the DAC circuit 8 are short-circuited.
  • the counter m is initialized to 0 (S61).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m and here gradation data of gradation 0 are input to sampling circuit 26 and sampling circuit 6 via a data bus.
  • the DAC circuits 28 and 8 acquire gradation data of gradation 0 from the sampling circuits 26 and 6 via the hold circuits 27 and 7. Further, the DAC circuits 28 and 8 output a gradation voltage of gradation 0 to the positive input terminal and the negative input terminal of the operational amplifier 1 (S62).
  • the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited by a switch (not shown). If it is determined in the operation check tests 1 and 2 that the DAC circuit 8 is not defective, the difference between the gradation voltages input to the positive input terminal and the negative input terminal is equal to or greater than one gradation. There is no voltage difference. Therefore, there is no problem that a large current flows by short-circuiting the positive input terminal and the negative input terminal.
  • the two input terminals of the operational amplifier 1 input the same gradation voltage.
  • the operational amplifier 1 since the operational amplifier 1 originally has an input / output offset voltage, the output of the operational amplifier 1 is “H” or “L” even if the same gradation voltage is input to its two input terminals. Either of these will be output.
  • the determination circuit 3 stores the output level of the operational amplifier 1 when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S63).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the gradation voltage of gradation 0 from the DAC circuit 8 is input to the positive input terminal of the operational amplifier 1
  • the gradation voltage of gradation 0 from the DAC circuit 28 is input to the negative input terminal. Is done.
  • the determination circuit 3 compares the output from the operational amplifier 1 with the expected value stored by itself (S64). If the output value from the operational amplifier 1 is different from the expected value, the determination circuit 3 outputs the “H” flag to the determination flag 4 (S65).
  • the gradation voltage from the DAC circuit 28 is input to the positive input terminal of the operational amplifier 1 and the gradation voltage from the DAC circuit 8 is input to the negative input terminal by a switch (not shown).
  • the input is switched (S66).
  • the same processing as S64 is performed (S67).
  • the determination circuit 3 if the output from the operational amplifier 1 is different from the expected value stored in the determination circuit 3, the determination circuit 3 outputs an “H” flag to the determination flag 4 (S68). In this way, by switching between the positive polarity input terminal and the negative polarity input terminal, even if the expected value stored in the determination circuit 3 is either the “H” level or the “L” level, the problem of the DAC circuit 8 is prevented. It can be detected.
  • FIG. 13 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuit 28 and performing self-repair.
  • the determination circuit 3 determines that the DAC circuit 8 is defective, the determination circuit 3 outputs an “H” flag to the determination flag 4. Further, the determination flag 4 receives the “H” flag from the determination circuit 3 and stores it in the inside thereof.
  • the control circuit detects whether or not the determination flag 4 records “H” (S71). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S75. On the other hand, when the control circuit detects that the determination flag 4 stores “H”, the control circuit checks the number of “H” flags stored in each of the determination flags 4-1 to 4-n. Here, when the number of “H” flags stored in the determination flag 4 is plural, the process proceeds to S73. On the other hand, when the number of “H” flags stored in the determination flag 4 is one, the process proceeds to S74 (S72).
  • Judgment flag 4-1 outputs an output signal of Flag1 which becomes “H” level to the switches 2c and 2d.
  • the switch 2c to which the “H” level signal is input is turned OFF and the switch 2d is turned ON by the output signal of Flag1.
  • the switch 2c cuts off the connection between the output from the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1.
  • the switch 2d outputs the STR1 signal input to the sampling circuit 6-1 to the sampling circuit 26.
  • the gradation data corresponding to the liquid crystal driving signal output terminal OUT1 also stores the sampling circuit 26.
  • the switch 2d connects the output of the operational amplifier 21 and the liquid crystal driving signal output terminal OUT1.
  • the switches 2c and 2d are switched by the output signal of Flag1 from the determination flag 4-1, so that the defective DAC circuit 8-1 is switched to the spare DAC circuit 28.
  • the integrated circuit 10 can switch the defective DAC circuit to the spare DAC circuit 28 by performing the operation check tests 1 to 5 and the self-repair process. Further, in the first embodiment, a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28 are provided. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 14 is a flowchart showing a processing procedure from when the display device is turned on until the operation check test is performed and the normal operation is started.
  • FIG. 15 is an explanatory diagram showing a configuration of the operational amplifier 1 and peripheral circuits for confirming the operation of the operational amplifier 1.
  • the positive input terminal of the operational amplifier 1 is connected to a switch S5 for switching input between an output from the DAC circuit 8 and a predetermined voltage. Further, a switch S3 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S5. On the other hand, the negative input terminal of the operational amplifier 1 is connected to a switch S6 for switching input between an output of the operational amplifier 1 for performing negative feedback from the operational amplifier 1 and a predetermined voltage. Further, a switch S4 for switching between two predetermined voltages Vref1 and Vref2 is connected to the B side (a predetermined voltage input side) of the switch S4.
  • the operational amplifier 1 operates as a voltage follower circuit by setting the switch S5 to the A side (output side of the DAC circuit 8) and the switch S6 to the A side.
  • the switches S1 and S2 are switched to the B side. Thereby, there is no negative feedback of the operational amplifier 1, and the operational amplifier 1 operates as a comparator.
  • the switches S3 and S4 are switched to the A side.
  • Vref1 is input to the positive input terminal of the operational amplifier 1
  • Vref2 is input to the negative input terminal.
  • Vref1 and Vref2 are voltages generated in advance, and the voltage value of Vref1 is larger than the voltage value of Vref2.
  • the difference in voltage value between Vref1 and Vref2 is set to a value larger than the input / output offset value of the operational amplifier 1.
  • the operational amplifier 1 outputs a signal of “H” level because the voltage of Vref1 input to the positive input terminal is higher than Vref2 input to the negative input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “H” stored by itself. Here, when the output of the operational amplifier 1 is at the “L” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the expected value stored by the determination circuit 3 is given by the control circuit.
  • the switches S3 and S4 are switched to the B side, Vref2 is input to the positive input terminal of the operational amplifier 1, and Vref1 is input to the negative input terminal.
  • the operational amplifier 1 outputs the “L” level because the voltage value of Vref1 input to the negative input terminal is higher than Vref2 input to the positive input terminal.
  • the determination circuit 3 detects the output from the operational amplifier 1 and compares it with the expected value “L” stored by itself. Here, when the output of the operational amplifier 1 is at the “H” level, the determination circuit 3 can determine that the operational amplifier 1 has a problem. Note that the switches S3 to S6 are switched by the control circuit.
  • the operational amplifier 1 compares the output of the DAC circuit 8 with the output of the spare DAC circuit 28.
  • two adjacent DAC circuits 8 are set as one set, and the outputs from the DAC circuits 8 are compared in the operational amplifier 1.
  • FIG. 16 is an explanatory diagram showing the configuration of the integrated circuit 20 (integrated circuit for driving the display device).
  • the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier 1 to its positive input terminal. Furthermore, the operational amplifier 1 inputs the output from the DAC circuit 8 connected in series to the operational amplifier adjacent to the operational amplifier 1 to its negative input terminal. Specifically, as shown in the figure, the operational amplifier 1-1 inputs the output from the DAC circuit 8-1 to its positive input terminal, and outputs the output from the DAC circuit 8-2. It inputs to its own negative input terminal via the switch 2a. Similarly, the operational amplifier 1-2 inputs the output from the DAC circuit 8-2 to its own positive input terminal, and outputs the output from the DAC circuit 8-1 through its switch 2a to its own negative input terminal. To enter.
  • the integrated circuit 20 also includes spare sampling circuits 26A and 26B, spare hold circuits 27A and 27B, spare DAC circuits 28A and 28B, operational amplifiers 21A and 21B, and pull-up / pull-down circuits 25A and 25B.
  • the output from the DAC circuit 28A is input to its own positive input terminal, and the output from the DAC circuit 28B is input to its own negative input terminal via the switch 2a.
  • the output from the DAC circuit 28B is input to its own positive input terminal, and the output from the DAC circuit 28A is input to its own negative input terminal via the switch 2a.
  • the control circuit sets the test signal to the “L” level and the test B signal to the “H” level.
  • the DAC circuit 8 converts the grayscale data input from the hold circuit 7 into a grayscale voltage signal and outputs the grayscale voltage to the positive input terminal of the operational amplifier 1.
  • the output of the operational amplifier 1 is negative feedback to its own negative input terminal because the switch 2b is ON.
  • the operational amplifier 1 operates as a voltage follower. Therefore, the operational amplifier 1 buffers the gradation voltage from the DAC circuit 8 and outputs it to the corresponding output terminals OUT1 to OUTn.
  • the control circuit sets the test signal to the “H” level and sets the test B signal to the “L” level.
  • the switch 2a is turned ON, the TSTR1 signal is sent to the sampling circuit 26A and the odd-numbered sampling circuits 6 (sampling circuits 6-1, 6-3,..., 6- (n ⁇ 1)). Entered. Further, the TSTR2 signal is input to the sampling circuit 26B and the even-numbered sampling circuits 6 (sampling circuits 6-2, 6-3,..., 6-n).
  • the switch 2a when the switch 2a is turned ON, the output from the adjacent even-numbered DAC circuit 8 is input to the negative-polarity input terminal of the odd-numbered operational amplifier 1, and the negative-polarity input terminal of the even-numbered operational amplifier 1 is input. Are supplied with outputs from adjacent odd-numbered DAC circuits 8. Further, when the test B signal becomes “L” level, the switch 2b is turned OFF. As a result, negative feedback of the output of the operational amplifier 1 to the negative input terminal is cut off. As a result, the operational amplifier 1 becomes a comparator that compares the output from the DAC circuit 8 connected in series with the operational amplifier 1 with the output from the adjacent DAC circuit 8.
  • FIG. 17 is a flowchart showing a first procedure of the operation check test according to the second embodiment.
  • the control circuit sets the test signal to the “H” level and the test B signal to the “L” level (S101). As a result, the operational amplifier 1 operates as a comparator (S102). Next, the control circuit sets the expected value of the odd-numbered determination circuit 3 (determination circuits 3-1, 3-3,..., 3- (n ⁇ 1)) to the “L” level. On the other hand, the control circuit sets the expected value of the even-numbered determination circuit 3 (determination circuits 3-2, 3-4,..., 3-n) to the “H” level.
  • control circuit initializes a counter m included in the control circuit to 0 (S103). Further, the control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m through the data bus. In addition, the control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m + 1 through the data bus (S104).
  • the odd-numbered operational amplifier 1 has an odd-numbered DAC in which a gradation voltage of gradation 0 is connected in series to its positive polarity input terminal. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from its adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the odd-numbered operational amplifier 1 becomes “L”.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent odd-numbered DAC circuit 8 to its negative input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “H”.
  • the determination circuit 3 determines whether the level of the output signal from the operational amplifier 1 matches the expected value stored by itself (S105).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 (S106).
  • the above processing from S104 to S106 is repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S107, S108).
  • FIG. 18 is a flowchart showing a second procedure of the operation check test according to the second embodiment.
  • the operation check test 2 in the second embodiment is an operation check in which the voltage relationship of the odd-numbered and even-numbered gradations is reversed in the operation check test 1 in the second embodiment. This is the same as the operation check test in the embodiment.
  • control circuit sets the expected value of the odd-numbered determination circuit 3 to “H”, while setting the expected value of the even-numbered determination circuit 3 to “L”. Further, the control circuit initializes a counter m included in the control circuit to 0 (S111).
  • control circuit activates TSTR1, and the sampling circuit 26A and the odd-numbered sampling circuit 6 input gradation data of gradation m + 1 via the data bus.
  • control circuit activates TSTR2, and the sampling circuit 26B and the even-numbered sampling circuit 6 input gradation data of gradation m via the data bus (S112).
  • the odd-numbered operational amplifier 1 is connected to the positive-polarity input terminal of the grayscale voltage of grayscale 1 in series with the odd-numbered DAC. Input from circuit 8.
  • the odd-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 from the adjacent even-numbered DAC circuit 8 to its negative input terminal.
  • the output of the odd-numbered operational amplifier 1 becomes “H” level.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 0 to its positive input terminal from the even-numbered DAC circuit 8 connected in series to itself.
  • the even-numbered operational amplifier 1 inputs the gradation voltage of gradation 1 from the adjacent odd-numbered DAC circuit 8 to its negative polarity input terminal.
  • the DAC circuit 8 connected to the two input terminals of the operational amplifier 1 is normal, the output of the even-numbered operational amplifier 1 becomes “L” level.
  • the determination circuit 3 compares the level of the output from the operational amplifier 1 with the expected value stored in itself (S113).
  • the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value.
  • the above processes of S112 to S114 are repeated until the value of the counter m is incremented by one until the value of the counter m reaches n ⁇ 1 (S115, S116).
  • FIG. 19 is a flowchart showing a third procedure of the operation check test according to the second embodiment.
  • the gradation voltage input to the operational amplifier 1 by the executed check test is used as the operational amplifier. 1 may continue to be held, and in the operation check tests 1 and 2 of the second embodiment, there may be a case where a failure cannot be detected.
  • the control circuit initializes the value of the counter m included therein to 0 (S121).
  • the pull-up / pull-down circuit 5 is connected to the positive input terminal of the DAC circuit 8.
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull up the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled down (S122).
  • the output of the even-numbered DAC circuit 8 is open, a low voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 20 is a flowchart showing a fourth procedure of the operation check test according to the second embodiment.
  • the control circuit initializes the value of the counter m included in the control circuit to 0 (S131).
  • the control circuit controls the pull-up / pull-down circuit 5 so as to pull down the positive input terminal of the odd-numbered operational amplifier 1 (S122).
  • the control circuit controls the pull-up / pull-down circuit 5 so that the positive input terminals of the even-numbered operational amplifiers 1 are pulled up (S122).
  • the output of the even-numbered DAC circuit 8 is open, a high voltage is input to the positive input terminal of the even-numbered operational amplifier 1.
  • FIG. 21 is a flowchart showing a fifth procedure of the operation check test according to the second embodiment.
  • the DAC circuit 8 may have a problem that two adjacent gray scales in itself are short-circuited.
  • the purpose of the operation check test 5 of the second embodiment is to detect such a problem.
  • the control circuit initializes the value of the counter m included in itself to 0 (S141).
  • TSTR1 and TSTR2 are activated, and further, gradation data of gradation m is input to the sampling circuit 26A, the sampling circuit 26B, and the sampling circuit 6 through the data bus.
  • the odd-numbered DAC circuit 8 and the even-numbered DAC circuit 8 output the gradation voltage of the same gradation m (S142).
  • the control circuit short-circuits the positive input terminal and the negative input terminal of the operational amplifier 1 through a switch (not shown).
  • the determination circuit 3 stores the output level of the operational amplifier when the positive input terminal and the negative input terminal of the operational amplifier 1 are short-circuited as an expected value (S143).
  • the switch (not shown) is turned OFF to cancel the short circuit between the positive input terminal and the negative input terminal of the operational amplifier 1.
  • the positive polarity input terminal of the odd-numbered operational amplifier 1 is input with the grayscale voltage of grayscale m from the odd-numbered DAC circuit 8 connected in series to itself, Are supplied with the gradation voltage of gradation m from the even-numbered DAC circuit 8 adjacent thereto.
  • the gradation input of the gradation m from the even-numbered DAC circuit 8 connected in series to the positive-polarity input terminal of the even-numbered operational amplifier 1 is input to the negative-polarity input terminal.
  • the gradation voltage of gradation m from the adjacent odd-numbered DAC circuit 8 is input.
  • the determination circuit 3 compares the expected value stored by itself with the output from the operational amplifier 1 (S144). Further, the determination circuit 3 outputs an “H” flag to the determination flag 4 when the output from the operational amplifier 1 is different from the expected value stored by itself. Further, the determination flag 4 stores therein the “H” flag input from the determination circuit 3.
  • control circuit switches the signal input to the positive input terminal of the operational amplifier 1 and the signal input to the negative input terminal from the DAC circuit 8 using a switch (not shown) (S146). Thereafter, the same processing as S147 is performed (S147). Similarly to S145, when the output from the operational amplifier 1 is different from the expected value stored in the operational amplifier 1, the determination circuit 3 outputs “H” to the determination flag 4 (S148).
  • FIG. 22 is a flowchart showing a procedure for switching between the DAC circuit 8 determined to be defective and the spare DAC circuits 28A and 28B and performing self-repair.
  • the control circuit detects whether or not the determination flag 4 stores “H” (S151). When the control circuit detects that the determination flag 4 does not store “H”, the control circuit proceeds to S153. On the other hand, when the control circuit detects the determination flag 4 storing “H”, the DAC circuit 8 corresponding to the determination flag 4 storing “H” is switched to the spare DAC circuit 28A or 28B.
  • the operation confirmation is performed with the two DAC circuits 8 as one set, even if the determination flag 4 stores the “H” flag, It cannot be determined whether the DAC circuit is defective.
  • the following description assumes that the DAC circuit 8-1 has a problem.
  • the determination circuits 3-1 and 3-2 output “H” to the determination flags 4-1 and 4-2 by the operation check tests 1 to 5. Will do. Further, the determination flags 4-1 and 4-2 output the “H” flag input from the determination circuits 3-1 and 3-2 to the switches 2c and 2d, thereby turning the switch 2c OFF and turning the switch 2d ON. As a result, the sampling circuit 26A inputs the STR1 signal, and the sampling circuit 26B inputs the STR2 signal.
  • the sampling circuit 26A acquires gradation data corresponding to the liquid crystal driving signal output terminal OUT1 from the data bus
  • the sampling circuit 26B acquires the gradation data corresponding to the liquid crystal driving signal output terminal OUT2.
  • Data is acquired from the data bus.
  • the switch 2c is turned OFF, the connection between the output of the operational amplifier 1-1 and the liquid crystal driving signal output terminal OUT1 is cut off, and the output of the operational amplifier 1-2 and the liquid crystal driving signal output terminal OUT2 are disconnected. The connection is also cut off.
  • the switch 2d is turned on, the output of the operational amplifier 21A is connected to the liquid crystal driving signal output terminal OUT1, and the output of the operational amplifier 21B is connected to the liquid crystal driving signal output terminal OUT2.
  • the defective DAC circuit 8 is switched to the spare DAC circuit 28A and 28B by taking the defective DAC circuit 8 and the DAC circuit 8 paired therewith as a set, thereby switching the defective DAC circuit 8 to the spare DAC circuit. It can be switched to 26A or 26B.
  • control circuit sets the test signal to “L” and the test B signal to “H”, and shifts to normal operation (S153).
  • the gradation voltage from the output circuit block 30 (see FIG. 2) and the gradation voltage from the standby output circuit block 40 (see FIG. 2) are switched.
  • the switching circuit 60 (see FIG. 2) is configured to be provided in the integrated circuits 10 and 20, the present invention is not limited to this, and the switching circuit 60 is configured to be provided on the display panel side. Also good.
  • the configuration and operation of the display unit 90 ′ including the switching circuit 60 on the display panel side will be described as a third embodiment according to the present invention.
  • a different part from Embodiment 1 is demonstrated and the description is abbreviate
  • FIG. 23 is a block diagram showing a schematic configuration of the display unit 90 ′.
  • the display unit 90 ' includes a display panel 80' and an integrated circuit 10 '(drive circuit) that drives the display panel 80' based on gradation data input from the outside.
  • the integrated circuit 10 ′ is different from the integrated circuit 10 of the first embodiment in that the switching circuit 60 is not provided, and the other configuration is the same as that of the integrated circuit 10.
  • the display panel 80 ′ is different from the display panel 80 of the first embodiment in that it includes a switching circuit 60, and other configurations are the same as the display panel 80.
  • FIG. 24 is a block diagram showing a configuration of the integrated circuit 10 ′.
  • the integrated circuit 10 ′ receives n grayscale data corresponding to each of the n output terminals OUT1 to OUTn via a data bus from a grayscale data input terminal (not shown).
  • the integrated circuit 10 ′ includes a plurality of switches 2a that are switched ON / OFF by a test signal, a plurality of switches 2b that is switched ON / OFF by a test B signal, and an ON, OFF by an LF signal. And a plurality of switches 2f for switching OFF.
  • the switches 2a, 2b, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • each of the integrated circuit 10 'spare sampling circuit 26, spare hold circuit 27, spare DAC circuit 28, spare operational amplifier 21, and spare output terminal OUT0 is provided.
  • the display panel 80 ′ includes a connection terminal (not shown) connected to each of the output terminals OUT1 to OUTn included in the integrated circuit 10 ′ and determination flags 9-1 to 9-n ( Hereinafter, when collectively referred to as a determination flag 9), a switch 2 f that is switched ON / OFF by an LF signal from a control circuit (not shown), and an ON / OFF by an LFB signal that is an inverted signal of the LF signal. Switch 2e, and switches 2c and 2d that are turned on and off by Flag1 to Flagn that are output signals from the determination flag 9.
  • the switches 2d, 2e, and 2f are turned on when an “H” signal is input, and are turned off when an “L” signal is input.
  • the switch 2c is turned on when an “L” signal is input, and is turned off when an “H” signal is input.
  • the display panel 80 ′ in the present embodiment is a liquid crystal display panel, and as shown in FIG. 24, the data signal line SL ⁇ is connected to each of the output terminals OUT of the integrated circuit 10 ′ via the switches 2e and 2c. 1 to SL-n (hereinafter collectively referred to as data signal lines SL) are connected. Further, the same number of pixels P as the number of scanning signal lines GL are connected to each of the data signal lines SL. In FIG. 24, the pixel P connected to the data signal line SL-1 is a pixel P-1, and the pixel P connected to the data signal line SL-n is a pixel Pn.
  • the test signal is “H” and the test B signal is “L”. Therefore, the connection between the operational amplifier 1 and the output terminal OUT is disconnected by the switch 2b.
  • the control circuit outputs an “H” LF signal and also outputs an “L” LFB signal.
  • the switch 2 f is turned on, and each determination flag 4 is connected to each determination flag 9 via each output terminal OUT. Further, each of the determination flags 4 outputs the “H” flag or “L” flag stored therein as Flag1 to Flagn to each determination flag 9 via each output terminal OUT.
  • Each determination flag 9 stores Flag1 to Flagn output from the determination flag 4 in its own internal memory and outputs it to the switches 2c and 2d connected to itself.
  • Each switch 2e is turned OFF when the LFB signal becomes “L” during the period when the LF signal is “H”. This prevents Flag1 to Flagn output from the determination flag 4 from being output to the data signal lines SL-1 to SL-n. As a result, Flag1 to Flagn output from the determination flag 4 affects the pixel P. Will not affect.
  • the determination flag 4-1 corresponding to the output terminal OUT1 stores the “H” flag, in other words, when the DAC circuit 8-1 is defective, the determination flag 9-1 is determined by the determination flag 4 The “H” flag is then output, and the output “H” flag is recorded in the internal memory of the device. In this example, it is assumed that the determination flags 4-2 to 4-n record the “L” flag.
  • the determination flag 9-1 outputs Flag1 of the “H” flag to the switches 2c and 2d connected to the determination flag 9-1.
  • the switch 2c connected to the determination flag 9-1 disconnects the output terminal OUT1 from the data signal line SL-1, and the switch 2d connected to the determination flag 9-1
  • the terminal OUT0 and the data signal line SL-1 are connected.
  • each of the determination flags 9-2 to 9-n is connected to the determination flags 9-2 to 9-n in order to output the Flag 2 to Flagn of the “L” flag to the switches 2c and 2d connected thereto.
  • the switch 2c is turned on, and the switch 2d connected to the determination flags 9-2 to 9-n is turned off.
  • each of the data signal lines SL-2 to SL-n is connected to each of the output terminals OUT2 to OUTn via the switch 2e.
  • each determination flag 9 switches the switches 2c and 2d connected to itself based on Flag1 to Flagn from the determination flag 4, the control circuit outputs an “L” LF signal and outputs “H”. LFB signal is output. As a result, each of the output terminals OUT2 to OUTn is connected to each of the data signal lines SL-2 to SL-n.
  • the data signal line SL-1 is connected to the output terminal OUT0.
  • the data signal lines SL-2 to SL-n are connected to the operational amplifiers 1-2 to 1-n via the output terminals OUT2 to OUTn. Since the switch 2d connected to the sampling circuit 6-1 is turned on by Flag1 from the determination flag 4-1, the grayscale data (corresponding to the data signal line SL-1) input to the sampling circuit 6-1. Gradation data to be input) is also input to the sampling circuit 26.
  • gradation data corresponding to the data signal line SL-1 is input to the data signal line SL-1 from the output terminal OUT0 instead of the output terminal OUT1.
  • switching of the gradation data input to each of the sampling circuit 6 and the spare sampling circuit 26 is the same as the operation in the first embodiment, and thus detailed description thereof is omitted here.
  • the display unit 90 ′ performs a self-repair operation, so that the normal grayscale voltage is applied to the data signal line SL using the spare DAC circuit 28 instead of the DAC circuit 8 detected as defective. Can be output. Similar to the first embodiment, this embodiment also includes a spare sampling circuit 26 and a hold circuit 27 corresponding to the spare DAC circuit 28. Therefore, not only the DAC circuit 8 but also the sampling circuit 6 or the hold circuit 7 has a problem, the spare sampling circuit 26 and the hold circuit 28 can be switched.
  • FIG. 25 is a flowchart showing a processing procedure from when the display unit 90 ′ is turned on to when an operation check test is performed and the normal operation is started.
  • the display unit 90 ′ when the display unit 90 ′ detects that the power is turned on by the user, the display unit 90 ′ initializes the integrated circuit 10, thereby setting all the flags stored in the determination flag 4 to the “L” flag. (S161).
  • the control circuit sets the test signal to “H”, the test B signal to “L”, and switches the integrated circuit 10 ′ to the operation check test state (S 162).
  • the control circuit and the integrated circuit 10 perform the above-described operation check test (S163). Further, the control circuit confirms whether or not all the operation confirmation tests 1 to 5 have been completed (S164).
  • the display unit 90 ′ in the present embodiment is configured to include the determination flag 4 and the determination flag 9 as a circuit for storing a flag that is a determination result in the determination circuit 3-1, but the display unit 90 ′ is a modified example.
  • the determination flag 9, the switch 2f, and the switch 2e may not be provided, and the determination flag 4 may control the switches 2c and 2d.
  • the LF signal and the LFB signal for controlling the switches 2f and 2e are also unnecessary, while the determination flag 4 and wiring and connection terminals for connecting the switches 2c and 2d are required.
  • the integrated circuit and the display panel are connected via the output terminal OUT.
  • the integrated circuit and the display panel are not connected via the output terminal OUT.
  • An integrated display device is also included in the scope of the present invention.
  • a display unit 90 ′′ in which an integrated circuit and a display panel are integrated will be described as a fourth embodiment with reference to FIG. 26.
  • the display unit 90 ′′ according to the present embodiment is an embodiment. 1 is a modification of the display unit 90 according to the first embodiment. In the present embodiment, portions different from those of the first embodiment will be described, and descriptions of overlapping portions will be omitted.
  • FIG. 26 is a block diagram illustrating the configuration of the display unit 90 ′′.
  • the display unit 90 ′′ has no distinction between the integrated circuit 10 and the display panel 80 shown in the first embodiment, and the outputs of the operational amplifiers 1 and 21 are connected via the switches 2b, 2c, and 2d.
  • the display unit 90 ′′ of the present embodiment is different from the display unit 90 of the first embodiment in whether or not the output terminal OUT is provided.
  • Other configurations are the same as those of the display unit 90 of the first embodiment.
  • FIG. 27 is a block diagram illustrating a configuration of the television system 300.
  • the television system 300 is described as including the display unit 90 according to the first embodiment.
  • the television system according to the present invention is not limited to this, and instead of the display unit 90, The display device according to Embodiments 2 to 4 may be provided.
  • a television system 300 includes an antenna 301 that receives a broadcast wave, a tuner unit 302 that demodulates the received broadcast wave into a video / audio signal, and the demodulated video / audio signal as a video signal and an audio.
  • a signal separation unit 303 that separates the signal into a signal
  • a video signal processing unit 304 that decodes the separated video signal into a digital video signal, and obtains the decoded digital video signal as gradation data.
  • a display unit 90 that displays video on the display panel 80 (see FIG. 2), an audio signal processing unit 305 that decodes the separated audio signal into a digital audio signal, and the decoded digital audio signal as an analog signal.
  • An audio signal output unit 306 is provided that outputs the converted analog audio signal as audio from a speaker after conversion into the audio signal.
  • the antenna 301 receives a broadcast wave from a broadcast station, and outputs the received broadcast wave to the tuner unit 302.
  • the tuner unit 302 demodulates the output broadcast wave into a video / audio signal, and outputs it to the signal separation unit 303.
  • the signal separation unit 303 separates the output video / audio signal into a video signal and an audio signal, and outputs them to the video signal processing unit 304 and the audio signal processing unit 305, respectively.
  • the video signal processing unit 304 decodes the output video signal into a digital video signal, and outputs the decoded digital video signal to the display unit 90 as gradation data.
  • the display unit 90 displays the output gradation data using the display panel 80 provided therein.
  • the audio signal processing unit 305 decodes the audio signal separated by the signal separation unit 303 into a digital audio signal and outputs it to the audio output unit 306.
  • the audio signal output unit 306 converts the output digital audio signal into an analog audio signal, and then outputs the analog audio signal as audio using a speaker provided therein.
  • the television system 300 is configured to acquire from a broadcasting station using the antenna 301 and the tuner unit 302 as means for acquiring a video / audio signal, but the present invention is not limited to this.
  • the content data recorded on the recording medium may be read from the recording medium, and may be acquired via a PC (personal computer) from a content reading device such as a DVD player or the Internet.
  • the operation check test and the self-repair processing operation described in the first and fourth embodiments are performed immediately after power is supplied to the liquid crystal driving semiconductor integrated circuit 10, but the present invention is not limited to this. Instead, it may be configured by inputting a control signal to the liquid crystal driving semiconductor integrated circuit 10 and may be performed at an arbitrary timing. For example, a signal indicating a display blanking period may be input to the liquid crystal driving semiconductor integrated circuit 10 from the controller of the display device, and an operation check test and self-repair may be performed at this timing.
  • the liquid crystal driving semiconductor integrated circuit 10 is configured to detect a malfunction of the liquid crystal driving semiconductor integrated circuit 10, and the liquid crystal driving semiconductor integrated circuit 10 has an abnormality. Sometimes you can go. For example, the current of the signal output from the liquid crystal driving semiconductor integrated circuit 10 may be detected, and when the detected current exceeds the set current, an operation check test and a self-repair processing operation may be performed.
  • the operation check test and the self-repair processing operation may be performed periodically. For example, it may be performed every vertical blanking period in which no display is performed, or may be performed every preset total display time.
  • the operation check test and the self-repair processing operation may be performed during a part of the display period. For example, since a pixel stores a display voltage in a liquid crystal display device, there is no problem in display even if the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance after charging of the display voltage is completed. During a part of the display period, the output of the semiconductor integrated circuit 10 for driving the liquid crystal is set to high impedance, and an operation check test and a self-repair processing operation are performed.
  • one pattern is determined in a part of the display period of one line, and it is performed in a display period of one screen or a period of displaying several screens. You can also.
  • the integrated circuit 10 according to the present invention needs to stop the output signal for driving the display panel 80 (see FIG. 2) in order to self-detect its own defect (operation check test). There is. That is, the integrated circuit 10 cannot drive the display panel 80 during the self-detection period. Therefore, the timing at which the integrated circuit 10 performs self-detection needs to be performed in a period that does not affect the display of video on the display device.
  • the case where the integrated circuit 10 performs self-detection and self-repair is described as the period during which the integrated circuit 10 performs self-detection during the startup process when the display device is turned on. This is because the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device because the display device does not display video during the startup process of the display device. Because.
  • the integrated circuit 10 in the present embodiment performs self-detection to detect its own defect during the startup process when the display device is turned on.
  • the present invention is not limited to this.
  • Self-detection and self-repair can be performed in a period other than during the startup process of the display device.
  • Example 1 (Self-detection and self-repair in the vertical blanking period)
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device. Become. The reason will be described below.
  • FIG. (A) to (f) of FIG. 28 are time charts showing timings of signals inputted to the liquid crystal display device.
  • FIG. 28A shows the scanning signal line SCN1 that is output from the scanning side driving circuit that drives the scanning lines of the display device and is given to the first scanning signal line of the display device
  • FIG. Indicates a scanning signal line SCN2 output from the scanning side drive circuit and applied to the second scanning signal line of the display device
  • (c) in FIG. 8 is a video signal inversion from the integrated circuit 10 (see FIG. 7).
  • a video signal DSj corresponding to the j-th data signal line of the display device, which is given to the circuit, is shown, and (d) in the same figure shows the j-th data signal line from the video signal inversion circuit to the data side drive circuit.
  • the video signal DRVj corresponding to the data signal line is shown, (e) in the figure shows the video signal DATAj given to the jth data signal line of the display device, and (f) in the figure shows 1 in the display device.
  • the first scanning signal line and the jth It shows a driving voltage VD1j applied to pixels connected to the data signal line.
  • a period TV from time t1 to t5 is a vertical scanning period of the display device
  • a period TV1 is a vertical blanking period
  • a period TH from time t1 to t3 is a horizontal scanning period
  • a period TH1 from t2 to t3 is a horizontal blanking period.
  • the video signal inversion circuit inverts the polarity of the video signal DSj from the integrated circuit 10 in order to invert the polarity of the display electrode in each pixel of the display device every horizontal scanning period TH and vertical scanning period TV. Circuit.
  • the scanning side drive circuit sequentially delays the timing by the horizontal scanning TH from the first scanning signal line for each scanning signal line of the display device. , Scan signal SCN1, scan signal SCN2,..., Scan signal SCNm. Further, the scanning side driving circuit repeatedly outputs each scanning signal SCN1 to scanning signal SCNm to each scanning signal line of the display device every vertical scanning period TV. Note that here, the display device has m scanning signal lines.
  • the video signal DSj from the integrated circuit 10 is input to the video signal inversion circuit.
  • the video signal inversion circuit inverts the polarity of the video signal DSj every horizontal scanning period TH and also inverts the polarity every vertical scanning period TV, so that the video signal DRVj shown in FIG. Generate. Further, the video signal inversion circuit inputs the generated video signal DRVj to the data side driving circuit.
  • the data side driving circuit samples the video signal DRVj from the video signal inverting circuit every horizontal scanning period TH, delays the sampled signal value by one horizontal scanning period TH, and (e) of FIG. Is output to the jth data signal line of the display device.
  • the scanning signal SCN1 in the horizontal scanning period TH from time t1 to t2 is used.
  • the TFT in the pixel 1j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t1 to t2 is applied to the display electrode in the pixel 1j via the jth data signal line as the drive voltage VD1j. Is done.
  • the drive voltage VD1j applied to the display electrode of the pixel 1j continues to hold the voltage level during the time t1 to t2 even when the TFT in the pixel 1j is cut off during the time t2 to t5.
  • the scanning signal SCN2 in the horizontal scanning period TH from time t3 to t4.
  • the TFT in the pixel 2j becomes conductive, and as a result, the video signal voltage of the video signal DATAj at time t3 to t4 is applied to the display electrode in the pixel 2j via the jth data signal line as a drive voltage.
  • the drive voltage applied to the display electrode of the pixel 2j continues to hold the voltage level between times t3 and t4 even when the TFT in the pixel 2j is turned off.
  • the scanning-side driving circuit does not output the scanning signals SCN1 to SCNm for conducting the TFTs of the respective pixels to the scanning signal line, in other words, the period in which the conduction of the TFTs of the respective pixels is cut off.
  • the display device does not need to apply a voltage to the display electrode of each pixel. That is, it is not necessary for the integrated circuit 10 to output the video signal DSj that is the basis of the drive voltage, and even if the integrated circuit 10 and the display device are electrically disconnected, the display of the video on the display device is affected. There is no.
  • the integrated circuit 10 can perform self-detection and self-repair without affecting the display of video on the display device.
  • the integrated circuit 10 performs a self-detection process for detecting a defect in an output circuit block included in the integrated circuit 10 for each output circuit block corresponding to each data signal line and for all the output circuit blocks. It is targeted. Therefore, this self-detection process takes time.
  • the integrated circuit 10 does not need to perform self-detection processing when there is no possibility of malfunction in each output circuit block included in the integrated circuit 10. In other words, the integrated circuit 10 only needs to perform self-detection processing only when there is a possibility of malfunction in each output circuit block.
  • the integrated circuit 10 includes an operation determination circuit that determines whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10, and there is an operation failure somewhere in the integrated circuit 10 by the operation determination circuit. If the self-detection process is performed only when it is determined, it is possible to prevent performing a useless self-detection process.
  • FIG. 29 the operation determination circuit 200 for determining whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10 included in the integrated circuit 10 will be described with reference to FIGS. 29 to 31.
  • FIG. 29 the operation determination circuit 200 for determining whether or not there is a possibility of an operation failure with respect to the entire integrated circuit 10 included in the integrated circuit 10 will be described with reference to FIGS. 29 to 31.
  • the power supply current supplied to the integrated circuit 10 is compared with that during normal operation, in other words, compared with the initial stage that is determined to be good when shipped as a product. Become more. Therefore, when the value of the power supply current supplied to the integrated circuit 10 becomes larger than a certain value compared with the normal operation, an operation failure has occurred in the integrated circuit 10. Therefore, the operation determination circuit 200 detects the value of the power supply current supplied to the integrated circuit 10 and determines whether an operation failure has occurred in the integrated circuit 10 from the detected value of the power supply current.
  • FIG. 29 is a block diagram showing a configuration of the operation determination circuit 200.
  • the operation determination circuit 200 includes a resistor 202 (detection means) and a switch 203 between the integrated circuit 10 and the VA 201 that supplies power to the integrated circuit 10.
  • the resistor 202 and the switch 203 are connected so as to be parallel to each other.
  • the operation determination circuit 200 includes an A / D converter 204 (detection means) connected to one end of the resistor 202 and the switch 203 on the integrated circuit 10 side, and a switch for inputting an output signal from the A / D converter 204.
  • a comparison circuit 208 (current value comparison means, drive circuit determination means) that compares the output value with the output value from the data latch circuit 207 is provided. Note that the output terminal of the comparison circuit 208 connects the comparison result in the comparison circuit 208 to a control circuit included in the integrated circuit 10. Note that switching of the switches 203 and 205 is controlled by a control circuit included in the integrated circuit 10.
  • the operation determination circuit 200 previously stores a value corresponding to the power supply current value during normal operation of the integrated circuit 10 in the EEPROM 206 as reference data.
  • the operation determination circuit 200 detects a value corresponding to the power supply current value supplied to the integrated circuit 10.
  • the value of the reference data stored in the EEPROM 206 is compared, and if the detected value is equal to or greater than a certain value, it is determined that an operation failure has occurred in the integrated circuit 10.
  • the operation determination circuit 200 outputs a signal indicating that an operation failure has occurred in the integrated circuit 10 to the control circuit included in the integrated circuit 10, so that the control circuit detects the self-detection of the integrated circuit 10. Start processing and self-healing process.
  • FIG. 30 is a flowchart showing an operation process in which the operation determination circuit 200 stores reference data in the EEPROM 206.
  • the control circuit in generating the reference data, opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S301).
  • the resistance value of the resistor 202 is a resistance value such that the voltage drop of the resistor 202 during the normal operation of the integrated circuit 10 is about 0.1V. Note that the resistance value of the resistor 202 is preferably determined in consideration of current consumption of the integrated circuit.
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S302).
  • the A / D converter 204 inputs the converted digital value to the EEPROM 206 via the switch 205.
  • the EEPROM 206 stores the input digital value from the A / D converter as basic data (S303). Note that the switch 205 in S303 is switched by the control circuit so as to connect the A / D converter 204 and the EEPROM 206.
  • the control circuit short-circuits the switch 203 and returns the integrated circuit 10 to the normal operation state (S304).
  • the generation and storage processing of the reference data from S301 to S304 is performed at the product shipment stage of the display device including the integrated circuit 10, in other words, at the stage where the integrated circuit 10 is determined to be normal by various shipment inspections. Is called.
  • FIG. 31 is a flowchart showing processing for detecting an operation failure of the integrated circuit 10 in the operation determination circuit 200.
  • the control circuit opens the switch 203 so that the power source current from the VA 201 flows through the resistor 202 (S305).
  • the A / D converter 204 converts the voltage value at one end of the resistor 202 on the integrated circuit 10 side into a digital value (S306).
  • the A / D converter 204 inputs the converted digital value to the data latch circuit 207 via the switch 205.
  • the data latch circuit 207 stores the input digital value from the A / D converter as detection data (S307). Note that the switch 205 in S306 is switched by the control circuit so as to connect the A / D converter 204 and the data latch circuit 207.
  • the comparison circuit 208 reads the reference data stored in the EEPROM 206 and the detection data stored in the data latch circuit 207, and compares the value of the read reference data with the value of the detection data (S308). Further, the comparison circuit 208 detects whether or not the difference between the value of the reference data and the value of the detection data is equal to or greater than a predetermined value (for example, 3 or more as a digital value) (S309).
  • a predetermined value for example, 3 or more as a digital value
  • the control circuit 208 when the control circuit 208 receives a signal indicating that a malfunction has occurred in the integrated circuit 10 from the comparison circuit 208, the control circuit starts self-detection of the integrated circuit 10 (S311). Further, in the self-detection of the integrated circuit 10, when the integrated circuit 10 detects a failure in its own output circuit block, the integrated circuit 10 switches between the output of the defective output circuit block and the output of the spare output circuit block, Perform self-healing. Note that if the failure of the output circuit block cannot be detected in the self-detection of the integrated circuit 10 in S311, it is considered that the power supply current value varies due to other factors.
  • the operation determination circuit 200 since the power supply current value fluctuates, the operation determination circuit 200 generates and stores the reference data shown in S301 to S304, and the power supply current value that has fluctuated is newly set.
  • the reference data is stored in the EEPROM 206 (S312). Further, after S312, the control circuit short-circuits the switch 203 to place the operation determination circuit 200 and the integrated circuit 10 in a normal operation state (S310).
  • the comparison circuit 208 detects in S309 that the difference between the reference data value and the detected data value is less than a predetermined value (for example, less than 3 as a digital value), the process proceeds to S310. Transition.
  • a predetermined value for example, less than 3 as a digital value
  • Example 2 (Periodic self-detection of the integrated circuit 10) Further, self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed periodically. Specifically, the self-detection (operation check test) and self-repair of the integrated circuit 10 may be performed for each vertical blanking period of the display device described in the first embodiment. In this case, the vertical synchronization signal is counted and is displayed every certain number of times.
  • the counter can be configured by a non-volatile memory and the counter can count the number of vertical synchronization signals.
  • the integrated circuit 10 may be provided with a timer for measuring time, the operation time is counted by this timer, and the integrated circuit 10 is self-detected and self-repaired every preset accumulated operation time.
  • the self-detection (operation check test) and self-repair processing operation of the integrated circuit 10 may be performed during a part of a period during which the display device displays an image. For example, since each pixel of the display device stores the voltage of the display electrode, after charging of the voltage of the display electrode is finished, the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, There is no problem with the video display.
  • the output terminals OUT1 to OUTn of the integrated circuit 10 are set to high impedance, and self-detection (operation check test) and self-repair processing operations are performed.
  • a method for setting the output terminals OUT1 to OUTn to high impedance by providing a switch in series for each signal transmission path connecting the output terminals OUT1 to OUTn and the display device, and opening the switch, The output terminals OUT1 to OUTn and the display device have high impedance, in other words, can be electrically disconnected.
  • the integrated circuit 10 in the first embodiment has been described.
  • the present invention is not limited to this, and the integrated circuits 10 ′, 20 and in the second and third embodiments, and The present invention can also be applied to the display unit 90 ′′ in the fourth embodiment.
  • the liquid crystal display device that displays an image by the liquid crystal display panel has been described.
  • the present invention is not limited to this, and the present invention is not limited to the liquid crystal display device, such as a plasma television. Is also applicable.
  • the display device driving integrated circuit and the display device of the present invention may be configured as follows.
  • the self-healing means is Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means; If the determination result of the determination means is bad, the output terminal comprises a connection switching means for connecting the spare output circuit instead of the output circuit,
  • the output circuit block and the spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means.
  • Control means for controlling input signals to be input to the output circuit and the standby output circuit includes While inputting input signals of different magnitudes to the output circuit and the standby output circuit, Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
  • the drive circuit according to the first configuration or the second configuration, wherein the determination unit determines that the output circuit is defective when the comparison result and the expected value are different.
  • Flag storage means for storing a flag indicating the determination result of the determination means;
  • the connection switching means connects the spare output circuit to the output terminal instead of the output circuit when the value of the flag indicates that the output circuit is defective.
  • the drive circuit according to any one of the configuration from the third configuration to the third configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit, After the connection switching means connects the output terminal and the output of the auxiliary output circuit, the auxiliary output circuit outputs an output signal to the output terminal.
  • the drive circuit according to any one of the configurations.
  • Detection means for detecting the value of the power supply current supplied to the drive circuit; Normal current value storage means for storing in advance the value of the power supply current during normal operation of the drive circuit; Current value comparison means for comparing the value of the power supply current from the detection means with the value of the power supply current from the normal current value storage means; Drive circuit determination means for determining whether or not the drive circuit is defective based on a comparison result of the current value comparison means; When the determination result of the drive circuit determination means is bad, The comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit, The determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means, The connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to the configuration.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to.
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • the drive circuit according to any one of the configurations up to.
  • a blocking means for blocking a signal transmission path from the output terminal to the display panel After the blocking means blocks the signal transmission path from the output terminal to the display panel,
  • the comparing means compares the output signal from the output circuit with the output signal from the preliminary output circuit,
  • the determination means determines whether or not the output circuit is defective based on a comparison result by the comparison means,
  • the connection switching means switches the connection to the output terminal from the output of the output circuit determined to be defective by the determination means to the output of the spare output circuit.
  • N positive even number
  • N output circuit blocks including an output circuit that is connectable to each of the output terminals and outputs an output signal for driving the display panel
  • a first auxiliary output circuit block including a first auxiliary output circuit connectable to the odd numbered output terminal and capable of outputting the output signal to the display panel
  • a drive circuit for driving the display panel comprising: a second spare output circuit block including a second spare output circuit that can be connected to the even-numbered output terminals and can output the output signal to the display panel.
  • the self-healing means is Comparison means for comparing the output signal from the output circuit and the output signal from the output circuit adjacent to the output circuit; Determination means for determining whether or not the output circuit and the output circuit adjacent to the output circuit are defective based on the comparison result of the comparison means; Connection switching for connecting the first spare output circuit and the second spare output circuit to the output terminal instead of the output circuit and the output circuit adjacent to the output circuit, respectively, when the judgment result of the judging means is bad Means, and
  • the output circuit block, the first spare output circuit block, and the second spare output circuit block further include an output buffer using an operational amplifier, and the operational amplifier is used as the comparing means. .
  • Control means for controlling an input signal input to the output circuit, the first auxiliary output circuit, and the second auxiliary output circuit;
  • the control means includes The odd-numbered output circuit and the first spare output circuit, and the even-numbered output circuit and the second spare output circuit are inputted with different magnitude input signals, Output the expected value of the comparison result from the comparison means corresponding to the input signals of different sizes,
  • the drive circuit according to the tenth configuration, wherein the determination unit determines that the output circuit and an output circuit adjacent to the output circuit are defective when the comparison result and the expected value are different.
  • a display device comprising: the drive circuit according to any one of the first configuration to the eleventh configuration; and the display panel.
  • a display panel A drive circuit including an output circuit for outputting an output signal for driving the display panel from an output terminal connected to the display panel, and a display device comprising:
  • the drive circuit is A preliminary output circuit capable of outputting the output signal to the display panel; Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on the comparison result of the comparison means;
  • the display panel Switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel when the determination result from the determination means is defective. , Prepared, In the drive circuit, an operational amplifier used as an output buffer of the output circuit and the spare output circuit is used as the comparison means.
  • a display panel An output circuit for outputting an output signal for driving the display panel; A preliminary output circuit capable of outputting the output signal to the display panel; Comparison means for comparing the output signal from the output circuit with the output signal from the preliminary output circuit; Determination means for determining whether or not the output circuit is defective based on a comparison result of the comparison means; When the determination result of the determination means is defective, a switching means for switching the output signal from the defective output circuit to the output signal from the spare output circuit as an output signal for driving the display panel, Prepared, An operational amplifier used in the output buffer of the output circuit and the spare output circuit is used as the comparison means.
  • a television system comprising the display device according to any one of the twelfth configuration to the fourteenth configuration.
  • the display unit 90 is a display panel 80 and a drive circuit that drives the display panel 80, and detects a failure of the drive circuit in a state where the electrical connection with the display panel 80 is disconnected.
  • a liquid crystal driving semiconductor integrated circuit 10 having a self-detection / self-repair means for repairing, and the self-detection / self-recovery means is configured to switch the drive circuit when the image to be displayed on the display panel is switched discontinuously. A process for detecting a defect is executed.
  • the liquid crystal driving semiconductor integrated circuit 10 drives the display panel 80.
  • the liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect.
  • the liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected.
  • the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80.
  • the self-detection process can be executed using all the gradation data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the drive circuit when the image to be displayed on the display panel 80 is switched discontinuously. For example, when the display based on the image signal of one channel is interrupted by switching from the first channel to the second channel, the self-detecting / self-recovery means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed. Further, for example, when the display based on the image signal representing the program is interrupted due to the transition from the program to the CM, the self-detecting / self-repairing means switches when the image to be displayed on the display panel 80 switches discontinuously. A process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 is executed.
  • the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected. Since the self-detection process is executed at the timing when the currently displayed content is temporarily interrupted, the user does not feel uncomfortable. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
  • the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair unit performs the display on the display panel 80 once.
  • the self-detection / self-repair unit performs the display on the display panel 80 once.
  • the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups.
  • the self-detecting / self-repairing unit executes the above process group one by one every time the display based on the image signal being supplied to the display panel 80 is interrupted once. For example, when the number of process groups is n, all the processes included in the self-detection process can be completed when the display is interrupted n times.
  • the process is executed each time the display on the display panel 80 is interrupted. Since the processing time of the process group does not become so long, it is possible to execute self-detection and self-repair processing without making the user feel uncomfortable.
  • the process includes a plurality of steps, and the self-detection / self-repair means is included in the process when the display on the display panel is interrupted once. It is preferable to carry out all the steps.
  • the process for detecting a defect of the semiconductor integrated circuit 10 for driving the liquid crystal that is, the self-detection process includes a plurality of steps, and the self-detection / self-repair means is supplied to the display panel 80.
  • the display based on the middle image signal is interrupted once, all the steps included in the self-detection process are executed.
  • the display unit 90 receives a remote control I / F 401 that receives a channel selection operation by a user and a broadcast corresponding to the channel selection operation received by the remote control I / F 401, and displays the image signal of the broadcast on the display panel.
  • a controller 100 that detects that an image to be displayed on the display panel 80 switches discontinuously when switching between broadcasts received by the tuner, and the self-detection / self-repair means includes a controller When switching of an image to be displayed on the display panel 80 is detected by 100, it is preferable to start processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10.
  • the remote control I / F 401 receives a broadcast program tuning by the user. Further, the tuner receives a broadcast corresponding to the channel selection accepted by the remote control I / F 401 and supplies an image signal of the broadcast to the display panel. For example, the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
  • the controller 100 should display the display panel 80 when the display is interrupted by the tuner receiving a new broadcast in response to the user's channel selection. Detect that the images switch discontinuously. For example, when the user selects channel 2 while displaying a one-channel broadcast on display panel 80, when display of one channel is interrupted because the tuner receives the two-channel broadcast, display panel 80 It detects that the image to be displayed switches discontinuously.
  • the self-detecting / self-repairing means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detecting process when switching the broadcast received by the tuner.
  • a tuner that receives a broadcast and supplies an image signal of the broadcast to the display panel 80, and when the content of the broadcast received by the tuner is switched from a program to a CM (Commercial Message), And a controller 100 for detecting that the image to be displayed on the display panel 80 switches discontinuously, and the self-detection / self-repair means detects the switching of the image to be displayed on the display panel 80 by the controller 100.
  • CM Common Message
  • the tuner receives a broadcast and supplies an image signal of the broadcast to the display panel 80.
  • the tuner receives a broadcast of a channel designated by the user and supplies a video signal to the display panel 80.
  • the controller 100 switches the image signal supplied to the display panel 80 from the image signal representing the program included in the broadcast to the image signal representing the CM included in the broadcast.
  • the controller 100 detects that the image to be displayed on the display panel 80 is switched discontinuously when the display based on the image signal representing the program is interrupted by the program being broadcast being shifted to the CM.
  • the self-detection / self-repair means starts a process of detecting a defect of the liquid crystal driving semiconductor integrated circuit 10, that is, a self-detection process when the controller 100 detects the interruption of the display on the display panel 80.
  • the display unit 90 includes the display panel 80, a supply period in which an image signal is supplied, and a supply in which the supply of the image signal is stopped, during a period in which an image is displayed on the display panel 80.
  • Self-detection / self-repair means for detecting and repairing a defect in the drive circuit that drives the display panel 80 while switching the stop period and is disconnected from the display panel 80.
  • the self-detecting / self-repairing means executes processing for detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period.
  • the liquid crystal driving semiconductor integrated circuit 10 stops the supply period in which the image signal is supplied and the supply of the image signal in the period in which the image is displayed on the display panel 80.
  • the display panel 80 is driven while switching the supply stop period.
  • the liquid crystal driving semiconductor integrated circuit 10 can detect a defect of the liquid crystal driving semiconductor integrated circuit 10 itself, and has self-detection / self-repair means for repairing the detected defect.
  • the liquid crystal driving semiconductor integrated circuit 10 executes the process of detecting and repairing its own defect in a state where the electrical connection with the display panel 80 is disconnected.
  • the liquid crystal driving semiconductor integrated circuit 10 detects gradation of itself by disconnecting the electrical connection with the display panel 80 (that is, self-detection), thereby representing gradation data representing an image being displayed on the display panel 80.
  • the self-detection process can be executed using all the gradation data.
  • the image may be a still image or a moving image, that is, a video.
  • the self-detecting / self-repairing means executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 during the supply stop period.
  • the self-detecting / self-repairing unit executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in the horizontal scanning period and the vertical scanning period.
  • the self-detection process can be executed in a period that does not affect the display. That is, the display unit 90 according to the present embodiment executes a process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 in a state where the electrical connection with the display panel 80 is disconnected, but the display while displaying an image. Since the self-detection process is executed at the timing when the image signal is not supplied to the panel 80, the display panel 80 is not hindered. Therefore, according to the display unit 90 according to the present embodiment, it is possible to perform self-detection and self-repair processing at an appropriate timing without disturbing the user's viewing, thereby improving convenience for the user. Can do.
  • the process is divided into a plurality of process groups including one or more processes, and the self-detection / self-repair means performs the process group for each supply stop period. Are preferably performed one by one.
  • the process of detecting a defect in the liquid crystal driving semiconductor integrated circuit 10 that is, the self-detection process includes a plurality of processes, and these processes are divided into a plurality of process groups.
  • the self-detecting / self-repairing means executes the above process group one by one for each supply stop period. For example, when the number of process groups is n, all processes included in the self-detection process can be completed in n supply stop periods.
  • the process includes a plurality of processes, and the self-detecting / self-repairing unit executes all processes included in the process in one supply stop period. It is preferable.
  • the process for detecting a defect in the semiconductor integrated circuit 10 for driving the liquid crystal that is, the self-detection process includes a plurality of steps. In the period, all the steps included in the self-detection process are executed.
  • the display unit 90 further includes a controller 100 that detects switching from the supply period to the horizontal blanking period as the supply stop period in a period during which an image is displayed on the display panel 80,
  • the self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
  • the controller 100 detects the horizontal blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the horizontal blanking period. In the horizontal blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
  • the display unit 90 further includes a controller 100 that detects switching from the supply period to the vertical blanking period as the supply stop period in a period during which an image is displayed on the display panel 80,
  • the self-detecting / self-repairing unit preferably starts the processing when the controller 100 detects the switching.
  • the controller 100 detects the vertical blanking period during the period in which the image is displayed on the display panel 80. Then, the self-detection / self-repair means executes self-detection processing during the vertical blanking period. In the vertical blanking period, an image is displayed, but an image signal is not supplied to the display panel 80, and the display panel 80 is not driven.
  • the self-detection process in the vertical blanking period in which the image signal is not supplied to the display panel 80. Therefore, the self-detection process does not affect the screen display. The user does not feel uncomfortable.
  • the liquid crystal driving semiconductor integrated circuit 10 includes an output circuit block 30 that outputs an output signal for driving the display panel 80, and the self-detection / self-repair means includes an output circuit.
  • a comparison / determination circuit 50 for determining whether or not the block 30 is defective is provided. When the determination result of the comparison / determination circuit 50 is defective, a liquid crystal driving semiconductor is output so as to output a normal output signal to the display panel 80.
  • the integrated circuit 10 is preferably self-healing.
  • the liquid crystal driving semiconductor integrated circuit 10 includes the output circuit block 30 that outputs an output signal for driving the display panel 80.
  • the output circuit block 30 converts, for example, video data into a gradation voltage and outputs it as an output signal for driving the display panel 80.
  • the self-detection / self-repair means includes the comparison determination circuit 50 that determines whether or not the output circuit block 30 is defective, and the determination result in the comparison determination circuit 50 is defective. If so, the liquid crystal driving semiconductor integrated circuit 10 is self-repaired so as to output a normal output signal to the display panel 80.
  • the display unit 90 in the display unit 90 according to the present embodiment, a defect in the output circuit block 30 of the liquid crystal driving semiconductor integrated circuit 10 can be detected, and self-repair can be performed when the output circuit block 30 is defective.
  • the liquid crystal driving semiconductor integrated circuit 10 includes a spare output circuit block 40 that can output the output signal to the display panel 80, and the self-detection / self-repair means is a comparison / determination circuit.
  • the determination result of 50 is defective, a switching circuit 60 that switches the output signal from the defective output circuit block 30 to the output signal from the standby output circuit block 40 as an output signal to the display panel 80, It is preferable to provide.
  • the drive circuit includes the spare output circuit block 40 that can output an output signal to the display panel 80.
  • the preliminary output circuit block 40 can convert, for example, video data into a gradation voltage and output it as an output signal for driving the display panel 80.
  • the self-detection / self-repair means includes the switching circuit 60 that switches the output circuit block 30 determined to be defective in the comparison determination circuit 50 to the spare output circuit block 40.
  • the display unit 90 when the output circuit block 30 is defective, the defective output circuit block 30 is switched to the spare output circuit block 40, whereby the liquid crystal driving semiconductor integrated circuit 10 is replaced. Self-healing can be easily performed.
  • the comparison determination circuit 50 compares the output signal from the output circuit block 30 with the output signal from the auxiliary output circuit block 40, as operational amplifiers 1-1, 1-2, 1-. It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n.
  • the operational amplifiers 1-1, 1-2, and 1-n compare the output signal from the output circuit block 30 with the output signal from the spare output circuit block 40. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • a defect in the output circuit block 30 can be determined by comparing the output of the output circuit block 30 and the output of the standby output circuit block 40.
  • a defect in the output circuit block 30 can be easily detected.
  • the display unit 90 further includes control means for controlling input signals input to the output circuit block 30 and the spare output circuit block 40, and the control means includes the output circuit block 30, the spare output circuit block 40, and the like.
  • control means for controlling input signals input to the output circuit block 30 and the spare output circuit block 40
  • the control means includes the output circuit block 30, the spare output circuit block 40, and the like.
  • an input signal of a different magnitude is input, and an expected value of a comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signal of the different magnitude is output, and a comparison determination circuit 50, it is preferable to determine that the output circuit block 30 is defective when the comparison result is different from the expected value.
  • the control means controls the input signals input to the output circuit block 30 and the spare output circuit block 40 and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes.
  • the comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
  • an input signal of gradation m is input to the output circuit block 30, and an input signal of gradation m + 1 is input to the standby output circuit block 40.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the spare output circuit block 40 is higher.
  • the output circuit block 30 when the output circuit block 30 is defective and the output circuit block 30 can output only a high gradation voltage even if a signal of gradation m is input, the operational amplifiers 1-1, 1-2, and 1-n A signal indicating that the input gradation voltage is higher than that of the output circuit block 30 is output.
  • the operational amplifiers 1-1, 1-2, and 1-n compare the grayscale voltages output from the output circuit block 30 and the spare output circuit block 40. Then, different values of signals are output depending on whether the output circuit block 30 is defective or not.
  • the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when the input signal of gradation m is input to the output circuit block 30 and the input signal of gradation m + 1 is input to the standby output circuit block 40 as described above, the level from the output circuit block 30 is increased. When a signal indicating that the regulated voltage is high is input from the operational amplifiers 1-1, 1-2, and 1-n, the output circuit block 30 is determined to be defective.
  • the comparison / determination circuit 50 determines that the output circuit block 30 is defective. It is determined that it is not.
  • the display unit 90 includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
  • the comparison determination circuit 50 includes operational amplifiers 1-1, 1-2, and 1-n that compare output signals from at least two output circuits in the output circuit block 30; It is preferable to determine whether or not the output circuit block 30 is defective based on the comparison results of the operational amplifiers 1-1, 1-2, and 1-n.
  • the comparison / determination circuit 50 includes the operational amplifiers 1-1, 1-2, and 1-n.
  • the operational amplifiers 1-1, 1-2, and 1-n compare output signals from at least two output circuits in the output circuit block 30. Then, the comparison determination circuit 50 determines whether or not the output circuit block 30 is defective based on the comparison result of the operational amplifiers 1-1, 1-2, and 1-n.
  • the display unit 90 can determine the failure of the output circuit block 30 by comparing the output of the output circuit block 30. Therefore, the failure of the output circuit block 30 can be easily detected with a simple configuration. Can be detected.
  • the display unit 90 further includes control means for controlling input signals to be input to at least two output circuits in the output circuit block 30, and the control means is different from the at least two output circuits.
  • the input signal of the magnitude is input, and the expected value of the comparison result from the operational amplifiers 1-1, 1-2, 1-n corresponding to the input signals of the different magnitudes is output.
  • the comparison result and the expected value are different, it is preferable to determine that one of the at least two output circuits is defective.
  • the control means controls the input signals input to at least two output circuits in the output circuit block 30, and inputs the input signals having different sizes. Further, the control means outputs the expected value of the comparison result from the operational amplifiers 1-1, 1-2, and 1-n corresponding to the input signals having different sizes.
  • the comparison determination circuit 50 determines that the output circuit block 30 is defective when the actual comparison result from the operational amplifiers 1-1, 1-2, and 1-n is different from the expected value from the control means.
  • the input signal of gradation m is input to the first output circuit
  • the input signal of gradation m + 1 is input to the output circuit 2.
  • the gradation voltage of gradation m is lower than the gradation voltage of gradation m + 1.
  • the operational amplifiers 1-1, 1-2, and 1-n output a signal indicating that the gradation voltage input from the second output circuit is higher. .
  • the operational amplifiers 1-1, 1-2, 1-n Outputs a signal indicating that the gradation voltage input from the first output circuit is higher.
  • the operational amplifiers 1-1, 1-2, and 1-n have the grayscale voltages output from at least two output circuits in the output circuit block 30. And output signals having different values depending on whether the output circuit block 30 is defective or not.
  • the comparison / determination circuit 50 determines whether or not the output circuit block 30 is defective based on the signals output from the operational amplifiers 1-1, 1-2, and 1-n. Specifically, when different input signals are input to the two output circuits of the first output circuit and the second output circuit as described above, the input signal of the gradation m is input to the first output circuit. When an input signal of gradation m + 1 is input to the second output circuit, a signal indicating that the gradation voltage from the first output circuit is high is supplied to the operational amplifiers 1-1, 1-2, 1-n. When more inputs are made, the comparison / determination circuit 50 determines that at least one of the first output circuit and the second output circuit is defective.
  • the first output circuit and the second output circuit are switched to a spare output circuit.
  • the comparison determination circuit 50 causes the output circuit block 30 to be defective. It is determined that it is not.
  • the display unit 90 includes specific means for easily detecting a defect in the output circuit block 30 and can self-repair when the output circuit block 30 is defective.
  • the output circuit block 30 includes an operational amplifier 21 as an output buffer, and the operational amplifiers 1-1, 1-2, and 1-n are comparators including the operational amplifier 21. It is preferable.
  • the output circuit block 30 includes the operational amplifier 21 as an output buffer.
  • the operational amplifiers 1-1, 1-2, and 1-n are comparators configured by the operational amplifier 21.
  • an output signal from the output circuit block 30 that drives the display panel 80 is buffered and output to an output terminal.
  • the operational amplifier 21 provides a voltage follower circuit by negatively feeding back its output to its negative input terminal, and has a function as a buffer circuit.
  • the operational amplifier 21 buffers the output signal from the output circuit block 30.
  • both the buffer circuit and the operational amplifiers 1-1, 1-2, and 1-n are combined. Therefore, the liquid crystal driving semiconductor integrated circuit 10 according to the present embodiment does not require a separate buffer circuit for buffering the output signal from the output circuit block 30, and has the effect of reducing costs.
  • the operational amplifier 21 preferably operates as a voltage follower when the display panel 80 is driven.
  • the television system 300 may be configured to include the display unit 90.
  • the present invention provides a display device including a display drive integrated circuit that includes specific means for detecting a defect in the output circuit and self-repairing, and that can more easily cope with the malfunction of the output circuit. It is suitable for a liquid crystal display device that can perform self-detection and self-repair at an appropriate timing.

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  • Engineering & Computer Science (AREA)
  • Biomedical Technology (AREA)
  • Multimedia (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • General Health & Medical Sciences (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

Télévision à cristaux liquides (400), comportant un module d’affichage (90) comprenant : un panneau d’affichage (80) ; et un module d’attaque des sources (10) destiné à attaquer le panneau d’affichage (80). Le module d’attaque des sources (10) comprend un circuit de contrôle de comparaison (50) et un circuit de commutation (60) destinés à détecter une défaillance du module d’attaque des sources (10) et à exécuter une reprise sur défaillance lorsque celui-ci est déconnecté électriquement du panneau d’affichage (80). Le circuit de contrôle de comparaison (50) et le circuit de commutation (60) exécutent un procédé de détection d’une défaillance du module d’attaque des sources au moment d’un changement de chaîne ou d’une commutation d’un programme sur un CM. La détection et la reprise sont donc réalisées automatiquement à un instant judicieux.
PCT/JP2009/069697 2008-11-20 2009-11-20 Dispositif d’affichage et système de télévision Ceased WO2010058836A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008-296965 2008-11-20
JP2008296965A JP2010122513A (ja) 2008-11-20 2008-11-20 表示装置、およびテレビジョンシステム

Publications (1)

Publication Number Publication Date
WO2010058836A1 true WO2010058836A1 (fr) 2010-05-27

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TW (1) TW201037680A (fr)
WO (1) WO2010058836A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10600378B2 (en) 2016-03-01 2020-03-24 Rohm Co., Ltd. Liquid crystal driving device
JP6706954B2 (ja) 2016-04-01 2020-06-10 三菱電機株式会社 ドライバｉｃおよび液晶表示装置
CN109906607A (zh) * 2016-10-26 2019-06-18 Nec显示器解决方案株式会社 视频信号输出装置、显示系统以及视频信号输出方法
JP7132010B2 (ja) * 2018-07-23 2022-09-06 ローム株式会社 異常検知回路
JP7040368B2 (ja) * 2018-09-06 2022-03-23 株式会社デンソー 液晶表示装置の異常検出装置
US11783739B2 (en) * 2020-09-10 2023-10-10 Apple Inc. On-chip testing architecture for display system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10339861A (ja) * 1997-03-15 1998-12-22 Sharp Corp フォールトトレラントアーキテクチャ
JP2002043943A (ja) * 2000-07-21 2002-02-08 Toshiba Corp アナログ出力装置
JP2008139861A (ja) * 2006-11-10 2008-06-19 Toshiba Matsushita Display Technology Co Ltd 有機発光素子を用いたアクティブマトリクス型表示装置、および有機発光素子を用いたアクティブマトリクス型表示装置の駆動方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10339861A (ja) * 1997-03-15 1998-12-22 Sharp Corp フォールトトレラントアーキテクチャ
JP2002043943A (ja) * 2000-07-21 2002-02-08 Toshiba Corp アナログ出力装置
JP2008139861A (ja) * 2006-11-10 2008-06-19 Toshiba Matsushita Display Technology Co Ltd 有機発光素子を用いたアクティブマトリクス型表示装置、および有機発光素子を用いたアクティブマトリクス型表示装置の駆動方法

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JP2010122513A (ja) 2010-06-03

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