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WO2009139185A1 - Dispositif mémoire non volatil à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif mémoire non volatil à semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2009139185A1
WO2009139185A1 PCT/JP2009/002148 JP2009002148W WO2009139185A1 WO 2009139185 A1 WO2009139185 A1 WO 2009139185A1 JP 2009002148 W JP2009002148 W JP 2009002148W WO 2009139185 A1 WO2009139185 A1 WO 2009139185A1
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Prior art keywords
layer
electrode wiring
interlayer insulating
memory device
insulating layer
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English (en)
Japanese (ja)
Inventor
姫野敦史
三河巧
有田浩二
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Definitions

  • the present invention relates to a cross-point type nonvolatile semiconductor memory device using a resistance change layer, and more particularly to a configuration in which a diode is inserted in series in a resistance change layer.
  • nonvolatile semiconductor memory devices using a ferroelectric as a capacitor element have already been used in many fields.
  • a nonvolatile semiconductor memory device (hereinafter referred to as a nonvolatile semiconductor memory device) using a material whose resistance value changes by application of an electric pulse and keeps the state after the change.
  • ReRAM ReRAM
  • the ReRAM includes a transistor and a nonvolatile storage unit connected to the drain of the transistor. And this memory
  • an oxygen-deficient tantalum oxide film (TaO x ), a nickel oxide film (NiO), a vanadium oxide film (V 2 O 5 ), a zinc oxide film (ZnO), a niobium oxide film (Nb 2 O 5 )
  • a titanium oxide film (TiO 2 ), a tungsten oxide film (WO 3 ), a cobalt oxide film (CoO), or the like is used.
  • Such a transition metal oxide film exhibits a specific resistance value when a voltage or current exceeding a threshold is applied, and may continue to hold the specific resistance value until a new voltage or current is applied. It is known and has a feature that it can be manufactured by using an existing DRAM process as it is.
  • the above example is composed of one transistor and one nonvolatile memory portion, but a cross-point type ReRAM using a perovskite structure material is also shown (for example, see Patent Document 2).
  • a stripe-shaped lower electrode is formed on a substrate, and an active layer is formed on the entire surface so as to cover the lower electrode.
  • a resistance change layer whose resistance is reversibly changed by an electric pulse is used.
  • a stripe-shaped upper electrode is formed perpendicular to the lower electrode.
  • a region where the lower electrode and the upper electrode intersect with each other with the active layer interposed therebetween is a memory portion, and each of the lower electrode and the upper electrode functions as either a word line or a bit line.
  • a ReRAM comprising a formed lower electrode, a resistance structure formed on the lower electrode, a diode structure formed on the resistance structure, and an upper electrode formed on the diode structure (For example, see Patent Document 3).
  • the unit cell structure can be a continuous stacked structure of one diode structure and one resistance structure, and an array cell structure can be easily realized.
  • a cross-point type ReRAM there is also shown a configuration in which a memory plug is formed at the intersection of a conductive array line in the X direction and a conductive array line in the Y direction (see, for example, Patent Document 4).
  • This memory plug is composed of seven layers, and a composite metal oxide sandwiched between two electrode layers is a memory element, and a metal-insulator-metal (MIM) structure formed on the memory element is It constitutes a non-ohmic element.
  • MIM metal-insulator-metal
  • the memory cells are connected to the bit lines and isolation diodes, and the isolation diodes are further connected to individual word lines.
  • the structure is also shown (see, for example, Patent Document 6).
  • the isolation diode a Schottky diode made of a metal-semiconductor contact is used, and it is shown that platinum (Pt) is suitable for the metal portion.
  • JP 2004-363604 A JP 2003-68984 A Japanese Patent Laid-Open No. 2006-140489 US Pat. No. 6,753,561 JP 2003-197880 A JP 2003-273335 A
  • the configuration of one diode having a switching function and one resistor is also described, but the specific structure of the resistor and the diode is not described or suggested at all.
  • the second example shows a cross-point configuration, but in this example, diodes are connected in series, and the specific structure of the cross-point configuration is completely described and suggested in the same manner as described above. It has not been.
  • the third example shows a configuration in which a resistor structure is formed on the lower electrode, a diode structure is further formed on the resistor structure, and an upper electrode is formed on the diode structure.
  • This diode structure is shown to be formed of a p-type oxide and an n-type oxide made of NiO, TiO 2 or the like.
  • the diode structure described in the third example is formed with the same outer dimensions as the resistor structure, it is difficult to increase the current capacity of the diode structure. If the current capacity of the diode is small, the current necessary for writing cannot be sufficiently passed, and there is a problem that the stable operation of the ReRAM is hindered.
  • the manufacturing method is complicated. Furthermore, in this configuration, since the non-ohmic element has the same shape as the variable resistance layer, the current capacity cannot be increased. For this reason, similarly to the above, there is a problem of inhibiting the stable operation of ReRAM.
  • the present invention solves the above-described conventional problems, and a nonvolatile semiconductor memory device capable of ensuring a sufficient current capacity and stable operation in a cross-point type structure in which a non-ohmic element and a resistance change layer are combined.
  • the purpose is to provide.
  • a nonvolatile semiconductor memory device includes a substrate, a lower electrode wiring formed on the substrate, an interlayer insulating layer formed on the substrate and the lower electrode wiring, An upper layer electrode wiring formed on the interlayer insulating layer; and a memory cell provided through the interlayer insulating layer and connected to the lower layer electrode wiring and the upper layer electrode wiring, wherein the memory cell includes the lower layer wiring A non-ohmic element provided on the electrode wiring, and a resistance change layer provided on the non-ohmic element and connected to the upper electrode wiring, wherein the non-ohmic element is at least a semiconductor layer or an insulating layer.
  • a body layer and a metal electrode body layer wherein the metal electrode body layer is formed in a contact hole provided through the interlayer insulating layer, and the semiconductor layer or the insulating layer Layer is formed in a wider area than the cross-section of the contact hole on the outer and and the lower electrode wiring of the contact hole.
  • Nonvolatile semiconductors that can ensure the flatness of the semiconductor layer or insulator layer constituting the ohmic element, have small variations in the characteristics of non-ohmic elements, have good reproducibility, and can secure sufficient current capacity A storage device can be realized.
  • the interlayer insulating layer may be a stacked structure including a plurality of layers.
  • the interlayer insulating layer becomes a non-ohmic element.
  • the contact hole for connection is formed by dry etching, the amount of digging by etching of the semiconductor layer or insulator layer that becomes a part of the non-ohmic element can be reduced, and the characteristic variation of the non-ohmic element is small.
  • a nonvolatile semiconductor memory device with good reproducibility can be realized.
  • the upper layer side of the interlayer insulating layer is made to have a hard film type in CMP by forming a multilayer structure of the interlayer insulating layer. By selecting, it is possible to reduce the polishing amount of the interlayer insulating layer.
  • the lower layer electrode wiring, the interlayer insulating layer, the non-ohmic element, the resistance change layer, and the upper layer electrode wiring are used as a single-stage structural unit, and the upper layer electrode is formed on the structural unit.
  • Another structural unit may be stacked using the wiring as a new lower electrode wiring.
  • the lower layer electrode wiring may be formed in a stripe shape
  • the upper layer electrode wiring may be formed in a stripe shape intersecting the lower layer electrode wiring
  • the lower layer electrode wiring and the upper layer electrode wiring can be used as a bit line and a word line, and further, a resistance change phenomenon according to a combination with a resistance change layer as a material used for the upper layer electrode wiring
  • the upper electrode wiring can be suitably used also as the upper electrode of the resistance change layer, so that the manufacturing process can be further simplified.
  • the non-ohmic element may be an MSM diode having a three-layer structure in which the semiconductor layer is sandwiched between the metal electrode body layer and another metal electrode body layer.
  • the non-ohmic element may be a MIM diode having a three-layer structure in which the insulator layer is sandwiched between the metal electrode layer and another metal electrode layer.
  • the non-ohmic element may be a Schottky diode having a two-layer structure including the semiconductor layer and the metal electrode body layer.
  • the method for manufacturing a nonvolatile semiconductor memory device of the present invention includes a step of forming a lower layer electrode wiring on a substrate and a semiconductor layer or an insulator layer that becomes a part of a non-ohmic element on the lower layer electrode wiring.
  • a step of forming an interlayer insulating layer on the substrate and the semiconductor layer or the insulator layer; and forming a contact hole in the interlayer insulating layer to form a part of the semiconductor layer or the insulator layer A step of exposing a metal electrode body layer to be a part of the non-ohmic element on the semiconductor layer or the insulator layer exposed in the contact hole; and on the metal electrode body layer Forming a resistance change layer, and forming an upper-layer electrode wiring on the resistance change layer.
  • a layer including a semiconductor layer or an insulator layer having a stacked structure constituting a non-ohmic element is formed on a lower electrode wiring having a flat surface formed by a damascene method. Since the flatness of the semiconductor layer or the insulator layer of the ohmic element can be ensured, the interface state of the non-ohmic element can be improved. As a result, it is possible to suppress a decrease in breakdown voltage and variations in breakdown voltage due to electric field concentration or the like, and to increase a current capacity.
  • the upper layer electrode wiring is used as a new lower electrode wiring, and the process from the step of forming the insulator layer to the step of forming the upper layer electrode wiring is repeated to obtain the new lower layer electrode wiring.
  • a new non-ohmic element, a new resistance change layer, and a new upper electrode wiring may be formed on the upper electrode wiring.
  • the lower electrode wiring may be formed in a stripe shape, and the semiconductor layer or the insulator layer may be formed in a stripe shape similar to the lower electrode wiring on the lower electrode wiring.
  • the semiconductor layer or the insulator layer of the non-ohmic element can be simultaneously processed, and three layers of the non-ohmic element are formed. Since the metal electrode body at the lower part of the structure can be covered by the lower electrode wiring, the manufacturing process can be further simplified.
  • the lower electrode wiring may be formed in a stripe shape
  • the upper electrode wiring may be formed in a stripe shape intersecting the lower electrode wiring
  • the lower layer electrode wiring and the upper layer electrode wiring can be used as a bit line and a word line, and further, a resistance change phenomenon according to a combination with a resistance change layer as a material used for the upper layer electrode wiring
  • the upper electrode wiring can be suitably used also as the upper electrode of the resistance change layer, so that the manufacturing process can be further simplified.
  • the nonvolatile semiconductor memory device of the present invention includes a semiconductor layer or an insulator layer among the layers constituting the non-ohmic element in a cross-point configuration in which the non-ohmic element is provided in series with respect to each resistance change layer. Since at least one layer is formed on the lower electrode wiring and other layers constituting the non-ohmic element are embedded in the contact hole, the current capacity is increased while simplifying the manufacturing process, and the characteristics of the non-ohmic element There is a great effect that can be stabilized.
  • the non-volatile semiconductor memory device of the present invention has a laminated structure of a plurality of interlayer insulating layers, whereby a semiconductor layer or an insulator constituting a non-ohmic element is formed when a contact hole is formed in the interlayer insulating layer. Variations in the thickness of the layers can be reduced, and the characteristics of the non-ohmic element can be stabilized.
  • FIGS. 1A and 1B are a plan view and a cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device according to the first embodiment of the invention.
  • 2A and 2B are a partially enlarged plan view and a partially enlarged cross-sectional view of a main part of the nonvolatile semiconductor memory device according to the first embodiment.
  • FIG. 3 is a block diagram illustrating a schematic circuit configuration of the nonvolatile semiconductor memory device according to the first embodiment.
  • 4A to 4D are views for explaining a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
  • 5A to 5C are views for explaining the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment.
  • FIGS. 9A and 9B are a cross-sectional view and a main part enlarged cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.
  • 10A to 10D are views for explaining a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
  • 11A to 11C are diagrams for explaining a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
  • FIGS. 12A to 12C are diagrams for explaining a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
  • 13A to 13C are diagrams for explaining a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment.
  • FIG. 14 is a cross-sectional view illustrating the configuration of a nonvolatile semiconductor memory device according to the third embodiment of the present invention.
  • FIG. 15 is a partial enlarged cross-sectional view of the main part of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention.
  • FIG. 16 is a partial enlarged cross-sectional view of the main part of the nonvolatile semiconductor memory device according to the fifth embodiment of the present invention.
  • FIGS. 17A and 17B are a partially enlarged plan view and a partially enlarged sectional view of the main part of the nonvolatile semiconductor memory device according to the sixth embodiment of the present invention.
  • FIGS. 1A and 1B are diagrams illustrating the configuration of the nonvolatile semiconductor memory device 10 according to the first embodiment of the present invention.
  • FIG. 1A is a plan view
  • FIG. 1B is a cross-sectional view taken along the line 1A-1A shown in FIG.
  • a part of the uppermost insulating protective layer 27 is notched for easy understanding.
  • FIG. 2 (a) and 2 (b) are partial enlarged views of the main part for showing the configuration of the non-ohmic element 17 and the storage unit 21.
  • FIG. FIG. 2A is a plan view
  • FIG. 2B is a cross-sectional view taken along the line 2A-2A shown in FIG.
  • the nonvolatile semiconductor memory device 10 includes a substrate 11, a stripe-shaped lower electrode wiring 15 formed on the substrate 11, an interlayer insulating layer 16 formed on the lower electrode wiring 15 and the substrate 11, and the like.
  • the contact hole formed through the interlayer insulating layer 16 is connected to the lower electrode wiring 15 and the non-ohmic element 17 formed on the lower electrode wiring 15 is embedded in the contact hole.
  • the non-ohmic element 17 is an MSM diode having a three-layer structure including a buried electrode 20 that is a metal electrode body layer, a semiconductor layer 19, and a lower electrode 18 that is another metal electrode body layer.
  • At least one layer including the semiconductor layer 19 having the above-described stacked structure, that is, the lower electrode 18 and the semiconductor layer 19 are formed outside the contact hole and on the lower electrode wiring 15 in a region wider than the cross section of the contact hole. Further, the other layer having the above-described laminated structure, that is, the buried electrode 20 is buried in the contact hole.
  • the upper layer electrode wiring 23 is formed on the interlayer insulating layer 16 in a stripe shape intersecting with the lower layer electrode wiring 15.
  • the embedded portion 20, the resistance change layer 22, and the upper electrode wiring 23 in a region connected to the resistance change layer 22 constitute a storage unit 21.
  • oxygen-deficient tantalum oxide (TaO x ) is preferable from the viewpoint of stability of resistance change characteristics, reproducibility of production, and the like.
  • the upper-layer electrode wiring 23 extends to the outside of the region where the non-ohmic element 17 and the storage unit 21 are formed in a matrix.
  • a semiconductor circuit in which active elements 12 such as transistors are integrated using a silicon single crystal substrate as the substrate 11 is provided.
  • active elements 12 such as transistors are integrated using a silicon single crystal substrate as the substrate 11
  • FIG. 1B as an example of the active element 12, a transistor including a source region 12a, a drain region 12b, a gate insulating film 12c, and a gate electrode 12d is shown.
  • elements necessary for a memory circuit such as a DRAM may be included.
  • the lower electrode wiring 15 and the upper electrode wiring 23 are respectively connected to the active element 12 in a region different from the matrix region in which the non-ohmic element 17 and the storage unit 21 are formed. That is, in FIG. 1B, the lower layer electrode wiring 15 is connected to the source region 12 a of the active element 12 through the buried conductors 24 and 25 and the semiconductor electrode wiring 26. Note that the upper-layer electrode wiring 23 is similarly connected to another active element (not shown) through the buried conductor 28.
  • the lower electrode wiring 15 can be easily formed by, for example, forming a film by sputtering using Ti—Al—N alloy, copper (Cu), or aluminum (Al), and performing an exposure process and an etching process.
  • the non-ohmic element 17 for example, the lower electrode 18 and the buried electrode 20 are made of tantalum nitride (TaN), tungsten (W), or a combination thereof, and the semiconductor layer 19 is nitrogen-deficient silicon nitride (SiN).
  • An MSM diode having a structure in which x ) is stacked can be used. If TaN or W is used as the electrode, the wiring resistance increases, and it is desirable to further form a thin film made of Al, Cu or the like.
  • an insulating oxide material can be used for the interlayer insulating layer 16.
  • a TEOS-SiO film or a silicon nitride (SiN) film formed by CVD using silicon oxide (SiO) or ozone (O 3 ) and tetraethoxysilane (TEOS) by CVD can be used.
  • a silicon carbonitride (SiCN) film, a silicon carbonation (SiOC) film, a silicon fluorine oxide (SiOF) film, or the like, which is a low dielectric constant material, may be used.
  • the resistance change layer 22 constituting the storage unit 21 is not only the above TaO x but also iron oxide, titanium oxide, vanadium oxide, cobalt oxide, nickel oxide, zinc oxide, niobium oxide film, tungsten oxide film, A transition metal oxide such as a hafnium oxide film may be used and formed by a sputtering method or the like. Such a transition metal oxide material exhibits a specific resistance value when a voltage or current exceeding a threshold value is applied, and the specific value is applied until a pulse voltage or current having a certain magnitude is newly applied. Continue to maintain the resistance value.
  • FIG. 3 is a block diagram illustrating a schematic circuit configuration of the nonvolatile semiconductor memory device 10 according to the present embodiment.
  • the non-ohmic element 17 and the resistance change layer 22 constituting the memory unit 21 shown in FIG. 1B are represented by symbols of a diode and a resistor, respectively.
  • the non-ohmic element 17 and the resistance change layer 22 are connected in series to constitute a memory cell.
  • One end of the non-ohmic element 17 is connected to the lower layer electrode wiring 15, and one end of the resistance change layer 22 is connected to the upper layer electrode wiring 23.
  • the non-ohmic element 17 and the entire storage unit 21 may be included in the memory cell.
  • the lower layer electrode wiring 15 is connected to the bit line decoder 6 and the readout circuit 7.
  • the upper layer electrode wiring 23 is connected to the word line decoder 5.
  • the lower layer electrode wiring 15 is a bit line and the upper layer electrode wiring 23 is a word line, and a plurality of memory cells are arranged in a matrix.
  • a peripheral circuit is constituted by the bit line decoder 6, the word line decoder 5, and the read circuit 7, and these peripheral circuits are constituted by an active element 12 made of, for example, a MOSFET.
  • FIG. 5 is a diagram showing a process until a lower electrode 18 and a semiconductor layer 19 are formed.
  • FIG. 4A is a cross-sectional view of a state in which the semiconductor interlayer insulating layer 14 is formed on the substrate 11 on which the active element 12 is formed
  • FIG. 4B is a stripe shape at a predetermined position of the semiconductor interlayer insulating layer 14.
  • FIG. 4C is a plan view showing a state in which a contact hole 24a for connecting to the wiring groove 15a and the semiconductor electrode wiring 26 is formed.
  • FIG. 4C shows the lower electrode wiring 15 and the buried conductor 24 in the semiconductor interlayer insulating layer 14 by the dual damascene method.
  • FIG. 4D is a cross-sectional view in which a lower electrode 18 and a semiconductor layer 19 constituting a non-ohmic element are further formed on the lower electrode wiring 15.
  • an interlayer insulating layer 16 is formed on a semiconductor interlayer insulating layer 14 including a lower electrode 18 and a semiconductor layer 19 constituting a non-ohmic element. It is a figure which shows the process until it forms the contact hole 29 in this position.
  • FIG. 5A is a cross-sectional view of a state in which an interlayer insulating layer 16 is formed on a semiconductor interlayer insulating layer 14 including a lower electrode 18 and a semiconductor layer 19 constituting a non-ohmic element
  • FIG. FIG. 5C is a cross-sectional view of the cross section taken along the line 5A-5A shown in FIG. 5B in the direction of the arrow, with the contact hole 29 formed at a predetermined position of the layer 16. 4 to 8 are all taken along line 5A-5A.
  • 6 (a) to 6 (d) are diagrams showing steps until the buried electrode 20 is buried in the contact hole 29 and the resistance thin film layer 22a to be the resistance change layer 22 is further formed.
  • FIG. 6A is a cross-sectional view of a state in which an electrode thin film layer 20a to be the buried electrode 20 is formed on the interlayer insulating film 16 including the contact hole 29, and FIG. 6B is an electrode thin film on the interlayer insulating film 16 by CMP.
  • FIG. 6C is a cross-sectional view in a state where the layer 20a is removed
  • FIG. 6C is a cross-sectional view in which the surface side of the embedded electrode 20 in the contact hole 29 is further removed
  • FIG. FIG. 6 is a cross-sectional view of a state in which a resistive thin film layer 22a to be a layer 22 is formed.
  • FIG. 7A and 7B are views showing a state in which the buried electrode 20 and the resistance change layer 22 are buried in the contact hole 29.
  • FIG. 7A is a plan view
  • FIG. 7B is a cross-sectional view taken along the line 5A-5A shown in FIG. 7A in the direction of the arrow.
  • FIG. 8A and 8B are views showing a state in which the upper layer electrode wiring 23 is formed on the interlayer insulating layer 16.
  • 8A is a plan view
  • FIG. 8B is a cross-sectional view taken along the line 5A-5A shown in FIG. 8A in the direction of the arrow.
  • a semiconductor interlayer insulating layer 14 is formed on a substrate 11 on which a plurality of active elements 12, buried conductors 25, semiconductor electrode wirings 26, and a semiconductor interlayer insulating layer 13 are formed.
  • Al is mainly used for the buried conductor 25 and the semiconductor electrode wiring 26, but recently, Cu that can realize low resistance even when miniaturized is mainly used.
  • the semiconductor interlayer insulating layers 13 and 14 also have a fluorine-containing oxide (for example, SiOF), a carbon-containing nitride (for example, SiCN), or an organic resin material (for example, polyimide) in order to reduce parasitic capacitance between wirings. Is used. Also in the present embodiment, for example, Cu can be used as the semiconductor electrode wiring 26, and SiOF, which is a fluorine-containing oxide, can be used as the semiconductor interlayer insulating layers 13 and 14, for example.
  • a fluorine-containing oxide for example, SiOF
  • SiCN silicon-containing nitride
  • organic resin material for example, polyimide
  • a stripe-shaped wiring groove 15 a for embedding the lower electrode wiring 15 in the semiconductor interlayer insulating layer 14 and a contact hole 24 a for connecting to the semiconductor electrode wiring 26 are formed. These can be easily formed by using a technique used in a general semiconductor process.
  • the lower electrode wiring 15 can be embedded in the semiconductor interlayer insulating layer 14.
  • the lower electrode wiring 15 other than the Ti—Al—N alloy material described above, for example, Cu, Al, Ti—Al alloy or a laminated structure thereof may be used.
  • a lower electrode 18 and a semiconductor layer 19 which are part of the non-ohmic element 17 are stacked so as to be connected to the lower electrode wiring 15.
  • the lower electrode 18 and the semiconductor layer 19 are formed on the lower electrode wiring 15 in the same stripe shape as the lower electrode wiring 15.
  • SiN x nitrogen deficient silicon nitride
  • the SiN x film having semiconductor characteristics can be formed, for example, by reactive sputtering in a nitrogen gas atmosphere using a Si target.
  • the chamber pressure may be 0.1 Pa to 1 Pa and the Ar / N 2 flow rate may be 18 sccm / 2 sccm at room temperature.
  • An interlayer insulating layer 16 made of TEOS-SiO is formed by CVD.
  • the interlayer insulating layer 16 various materials can be used as described above.
  • contact holes 29 are formed in the interlayer insulating layer 16 on the semiconductor layer 19 at a constant arrangement pitch.
  • the contact hole 29 has an outer shape smaller than the width of the lower layer electrode wiring 15 and the semiconductor layer 19 formed on the lower layer electrode wiring 15.
  • a quadrangular shape is used, but it may be a circular shape, an elliptical shape, or another shape. Since the contact hole 29 having such a shape can be formed by a general semiconductor process, detailed description thereof is omitted.
  • an electrode thin film layer 20a to be a buried electrode 20 is formed on the interlayer insulating layer 16 including the contact hole 29.
  • the electrode thin film layer 20a is a part of the non-ohmic element 17 and also a part of the storage unit 21, and TaN, W, or Pt is used.
  • the electrode thin film layer 20a on the interlayer insulating layer 16 is removed using a CMP process, and a buried electrode 20 is buried in the contact hole 29.
  • over polishing is further performed to remove a part of the surface of the buried electrode 20 in the contact hole 29.
  • a method for removing the electrode thin film layer 20a not only CMP but also an etch back method may be used.
  • a resistance thin film layer 22 a serving as a resistance change layer is formed on the interlayer insulating layer 16 including the contact holes 29.
  • TaO x is formed by sputtering as the variable resistance layer.
  • a film forming method not only sputtering but also CVD method, ALD method, or the like may be used.
  • the resistance thin film layer 22 a on the interlayer insulating layer 16 is removed using a CMP process, and the resistance change layer 22 is embedded in the contact hole 29.
  • an upper electrode wiring 23 is formed so as to be connected to the resistance change layer 22.
  • the upper electrode wiring 23 is formed on the interlayer insulating layer 16 in a stripe shape that is at least larger than the contact hole 29 and intersects the lower electrode wiring 15.
  • Cu, Pt or iridium (Ir) is used as the upper electrode wiring 23.
  • a buried conductor 28 is also formed at the same time, connected to a semiconductor electrode wiring (not shown) via the buried conductor 28, and electrically connected to an active element provided at a position not shown. Connect.
  • Equation 1 the current flowing through the MSM diode is proportional to the area of the MSM diode and inversely proportional to the thickness of the semiconductor layer 19. . Therefore, in order to obtain a large current capacity at a low voltage, it is required to form the semiconductor layer 19 thin.
  • the lower electrode wiring 15 is embedded in the semiconductor interlayer insulating layer 14 by a damascene process, and the surface of the lower electrode wiring 15 is formed. Is processed very smoothly.
  • the lower electrode 18 and the semiconductor layer 19 are laminated on the smooth lower electrode wiring 15, a dense and continuous film can be obtained even if the semiconductor layer 19 is thin.
  • the semiconductor layer 19 has a shape larger than that of the buried electrode 20 in the contact hole 29, the phenomenon that the lower electrode wiring 15 and the buried electrode 20 contact and leak does not occur. Furthermore, since the semiconductor layer 19 is also disposed outside the buried electrode 20, the current path flowing through the non-ohmic element is formed to extend outside the area of the buried electrode.
  • the nonvolatile semiconductor memory device 10 as shown in FIGS. 1A and 1B can be manufactured.
  • FIGS. 9A and 9B are diagrams illustrating the configuration of the nonvolatile semiconductor memory device 30 according to the second embodiment of the present invention.
  • FIG. 9A is a cross-sectional view
  • FIG. FIG. 3 is an enlarged cross-sectional view of a main part for showing the configuration of the non-ohmic element 17 and the storage unit 21.
  • the nonvolatile semiconductor memory device 30 of the present embodiment has the same basic configuration as the nonvolatile semiconductor memory device 10 of the first embodiment, but the interlayer insulating layer 31 on the substrate 11 including the lower electrode wiring 15 It is characterized by having a laminated structure of a plurality of layers, and an upper electrode wiring is embedded in the interlayer insulating layer 32.
  • FIG. 3 is a view showing a process until an interlayer insulating layer 31 having a three-layer structure is formed thereon and a contact hole 29 is formed in the interlayer insulating layer 31.
  • FIG. 10A is a cross-sectional view of a state in which the lower electrode 18 and the semiconductor layer 19 constituting the non-ohmic element 17 are formed on the lower electrode wiring 15 embedded in the interlayer insulating layer 14, and FIG. ) Is a cross-sectional view of a state in which an interlayer insulating layer 31 having a three-layer structure is formed, and FIG. 10C shows an interlayer insulating layer 31a and a lower interlayer insulating layer 31a of the interlayer insulating layer 31 having a three-layer structure by using an etching process.
  • FIG. 10D is a cross-sectional view of the state in which the contact hole 29 is formed up to the boundary surface of the layer 31b, and FIG. It is sectional drawing of the state which carried out.
  • FIGS. 11A to 11C are diagrams showing a process of embedding and forming the embedded electrode 20.
  • FIG. 11A is a cross-sectional view of a state in which an electrode thin film layer 20a to be the buried electrode 20 is formed on the interlayer insulating layer 31 including the contact hole 29, and FIG. 11B is an electrode thin film on the interlayer insulating layer 31 by CMP.
  • FIG. 11C is a cross-sectional view showing a state in which the embedded electrode 20 in the contact hole 29 is further overpolished and a recess is formed on the surface layer side.
  • the resistance change layer 22 is further embedded on the buried electrode 20 in the contact hole 29, and the interlayer insulation layer 32 is formed on the interlayer insulation layer 31 including the resistance change layer 22. It is a figure which shows the process until it does.
  • FIG. 12A is a cross-sectional view in a state in which a resistance thin film layer 22a to be the resistance change layer 22 is formed
  • FIG. 12B is a cross-sectional view in a state in which the resistance thin film layer 22a on the interlayer insulating layer 31 is removed by CMP
  • FIG. 12C is a cross-sectional view in a state where an interlayer insulating layer 32 is further formed.
  • FIGS. 13A to 13C are diagrams showing a process of forming a stripe-shaped wiring groove 33 in the interlayer insulating layer 32 and embedding the upper electrode wiring 23 in the wiring groove 33.
  • FIG. 13A to 13C are diagrams showing a process of forming a stripe-shaped wiring groove 33 in the interlayer insulating layer 32 and embedding the upper electrode wiring 23 in the wiring groove 33.
  • FIG. 13A is a cross-sectional view showing a state in which the wiring groove 33 is formed in the interlayer insulating layer 32
  • FIG. 13B shows an electrode thin film layer 23a that becomes the upper electrode wiring 23 on the interlayer insulating layer 32 including the wiring groove 33
  • FIG. 13C is a cross-sectional view showing a state in which the electrode thin film layer 23a on the interlayer insulating layer 32 is removed by CMP and the upper electrode wiring 23 is embedded in the wiring groove 33.
  • a non-ohmic element formed in a stripe shape similar to the lower electrode wiring 15 is formed on the lower electrode wiring 15 embedded in the semiconductor interlayer insulating layer 14.
  • a lower electrode 18 and a semiconductor layer 19 are stacked.
  • the lower interlayer insulating layer 31a made of SiCN, SiON, SiOC, SiOF, or the like using a CVD method or the like, and an insulating film of a film type different from the lower interlayer insulating layer 31a, for example,
  • a middle interlayer insulating layer 31b made of TEOS-SiO or the like and an upper interlayer insulating layer 31c made of, for example, SiON harder than TEOS-SiO are stacked.
  • the lower interlayer insulating layer 31a, the intermediate interlayer insulating layer 31b, and the upper interlayer insulating layer 31c constitute the interlayer insulating layer 31.
  • the film thickness of the lower interlayer insulating layer 31a is preferably sufficiently smaller than the film thickness of the intermediate interlayer insulating layer 31b.
  • the upper interlayer insulating layer 31c acts as a stopper in the CMP process, and by forming the upper interlayer insulating layer 31c, the CMP process can be performed easily and reliably.
  • contact holes 29 for connecting to the semiconductor layer 19 are formed in the interlayer insulating layer 31 at a constant arrangement pitch.
  • the contact hole 29 has an outer shape smaller than the width of the lower electrode wiring 15 and is the same as the shape described with reference to FIGS.
  • This processing can be performed by a general semiconductor process, for example, dry etching.
  • the lower interlayer insulating layer 31a functions as a stopper in etching. It is possible to reduce the digging amount of the semiconductor layer 19 due to the contact hole formation.
  • the thickness of the semiconductor layer 19 is not reduced at the bottom of the contact hole 29, and the semiconductor layer 19 can be prevented from being reduced in resistance and short-circuiting due to contact between the upper and lower electrodes of the semiconductor layer. Can be obtained.
  • SiON or silicon nitride (SiN) is used as the lower interlayer insulating layer 31a
  • TEOS-SiO is used as the intermediate interlayer insulating layer 31b.
  • the contact hole is formed by dry etching, for example, if the chamber pressure is 2.1 Pa and C 5 F 8 , O 2 and Ar are used as the etching gas at a flow rate of 17 sccm / 23 sccm / 500 sccm, the etching rate of SiON is TEOS The etching rate is as low as 1/5 compared to the etching rate of -SiO, and the etching rate of SiN is even smaller than 1/20 compared with the etching rate of TEOS-SiO. Therefore, it was confirmed that when the main interlayer insulating layer is TEOS-SiO, SiON or SiN acts as a stopper in the etching process.
  • contact holes are formed by over-etching until the semiconductor layer 19 is exposed.
  • the lower interlayer insulating layer 31a is removed by an etching process
  • SiON is used as the lower interlayer insulating layer 31a
  • only the flow rate is set to 10 sccm / 30 sccm / 500 sccm using the etching gas described above.
  • the etching rate of SiON increases 4 times compared to the above conditions.
  • SiN is used, the etching rate of SiN increases when only CF 4 is used as the etching gas.
  • an electrode thin film layer 20 a to be the buried electrode 20 is formed on the interlayer insulating layer 31 including the contact hole 29.
  • the electrode thin film layer 20a is a part of the non-ohmic element 17 and also a part of the memory unit 21, and TaN or W is used.
  • the electrode thin film layer 20a on the interlayer insulating layer 31 is removed using a CMP process, and the embedded electrode 20 is embedded in the contact hole 29.
  • the upper interlayer insulating layer 31c is provided in the interlayer insulating layer 31, the upper interlayer insulating layer 31c effectively functions as a stopper, and the interlayer insulating layer 31 is hardly polished and is thinned by the electrode thin film layer 20a. Only can be removed reliably.
  • a resistance thin film layer 22 a that becomes the resistance change layer 22 is formed on the interlayer insulating layer 31 including the contact hole 29.
  • TaO x is formed by sputtering as the resistive thin film layer 22a.
  • a film forming method not only sputtering but also CVD method, ALD method, or the like may be used.
  • the resistance thin film layer 22 a on the interlayer insulating layer 31 is removed by using a CMP process, and the resistance change layer 22 is embedded in the contact hole 29. Also in this case, since the upper interlayer insulating layer 31c is provided in the interlayer insulating layer 31, the upper interlayer insulating layer 31c effectively acts as a stopper, and the interlayer insulating layer 31 is hardly polished and is a resistive thin film layer. Only 22a can be reliably removed.
  • an interlayer insulating layer 32 is further formed on the interlayer insulating layer 31 including the resistance change layer 22.
  • the interlayer insulating layer 32 is formed to a thickness necessary for embedding the upper-layer electrode wiring 23, and as the material thereof, TEOS-SiO may be used, or other interlayer insulating materials generally used in semiconductor devices may be used. It may be used. Further, as with the interlayer insulating layer 31, a multilayer structure including two or more layers in which a hard insulating layer is formed as an upper layer may be employed.
  • a stripe-shaped wiring groove 33 that exposes the resistance change layer 22 and intersects the lower electrode wiring 15 is formed.
  • This processing can be performed by a general semiconductor process, for example, dry etching.
  • an electrode thin film layer 23 a to be the upper electrode wiring 23 is formed on the interlayer insulating layer 32 including the wiring trench 33. Also in the present embodiment, Cu, Pt, Ir or the like is used as the material of the upper electrode wiring 23.
  • the electrode thin film layer 23 a on the interlayer insulating layer 32 is removed by CMP process or etch back, and the upper electrode wiring 23 is embedded in the wiring trench 33.
  • the non-ohmic element 17 is constituted by the lower electrode 18, the semiconductor layer 19, and the buried electrode 20, and the upper electrode wiring 23 in the region connected to the buried electrode 20, the resistance change layer 22, and the resistance change layer 22;
  • the storage unit 21 is configured.
  • an insulating protective layer (not shown) for protecting the upper electrode wiring 23 is formed. Thereby, the nonvolatile semiconductor memory device by the manufacturing method of this embodiment can be manufactured.
  • the process can be easily performed.
  • the upper electrode wiring 23 is embedded in the interlayer insulating layer 32.
  • the interlayer insulating layer 31 is formed by using the method for manufacturing the nonvolatile semiconductor memory device 10 of the first embodiment.
  • the upper layer electrode wiring 23 may be formed thereon.
  • the upper electrode wiring 23 may be embedded in the interlayer insulating layer.
  • FIG. 14 is a cross-sectional view for explaining the configuration of the nonvolatile semiconductor memory device 40 according to the third embodiment of the present invention.
  • the nonvolatile semiconductor memory device 40 includes a lower layer electrode wiring, an interlayer insulating layer, a non-ohmic element, a resistance change layer, and an upper layer included in the nonvolatile semiconductor memory device 10 of the first embodiment shown in FIG.
  • the electrode wiring is configured as a single-stage structural unit, and an upper-layer electrode wiring immediately below the structural unit is used as a new lower-layer electrode wiring on the lowermost structural unit, and further, two-stage structural units are stacked. By stacking in this way, a larger capacity nonvolatile semiconductor memory device can be realized.
  • the non-ohmic element and the memory unit are stacked in three stages, so that the configuration requirements of the first stage, the second stage, and the third stage can be easily understood. For this reason, the first level is indicated by distinguishing the first level, the second level by the second level, and the third level by the third level.
  • the structural unit in the first stage is configured in the same way as the corresponding part of the nonvolatile semiconductor memory device 10 shown in FIG. Similar to the nonvolatile semiconductor memory device 10, in the nonvolatile semiconductor memory device 40, the first upper-layer electrode wiring 23 in the first stage is formed so as to extend outside the matrix region. Similarly to the first upper-layer electrode wiring 23 in the first stage, the second upper-layer electrode wiring 47 in the second stage and the third upper-layer electrode wiring 58 in the third stage are also formed to extend outside the matrix region. ing.
  • the structural unit in the second stage is formed as follows using the first upper layer electrode wiring 23 as a new lower layer electrode wiring.
  • the second lower electrode 42 and the second semiconductor layer 43 are formed on the first upper layer electrode wiring 23 in the same stripe shape as the first upper layer electrode wiring 23, and the second interlayer insulating layer 48 is further formed.
  • contact holes are provided at positions corresponding to the first memory portion 21, and the second embedded electrode 44 and the second resistance change layer 46 are embedded in the contact holes. .
  • the second upper layer electrode wiring 47 is formed in a stripe shape connected to the second resistance change layer 46 and intersecting the first upper layer electrode wiring 23. Further, a third interlayer insulating layer 51 is formed so as to bury the second upper layer electrode wiring 47.
  • the structural unit in the second stage is formed as follows using the second upper layer electrode wiring 47 as a new lower layer electrode wiring.
  • a third lower electrode 53 and a third semiconductor layer 54 are formed on the second upper layer electrode wiring 47 in the same stripe shape as the second upper layer electrode wiring 47, and a fourth interlayer insulating layer 59 is further formed.
  • the fourth interlayer insulating layer 59 is provided with a contact hole at a position corresponding to the first memory unit 21 and the second memory unit 45, and the third embedded electrode 55 and the third resistance change layer 57 are formed in the contact hole. It is embedded.
  • the third upper layer electrode wiring 58 is formed in a stripe shape connected to the third resistance change layer 57 and intersecting the second upper layer electrode wiring 47. Furthermore, an insulating protective layer 60 is formed to embed and protect the third upper layer electrode wiring 58.
  • the second lower electrode 42, the second semiconductor layer 43, and the second embedded electrode 44 constitute the second non-ohmic element 41.
  • the second embedded portion 44, the second resistance change layer 46, and the second upper layer electrode wiring 47 in the region connected to the second resistance change layer 46 constitute the second storage unit 45.
  • the third non-ohmic element 52 is constituted by the third lower electrode 53, the third semiconductor layer 54 and the third embedded electrode 55.
  • the third storage unit 56 is configured by the third embedded electrode 55, the third resistance change layer 57, and the third upper layer electrode wiring 58 in a region connected to the third resistance change layer 57.
  • the lower layer electrode wiring 15 is connected to the source region 12 a of the active element 12 through the buried conductors 24 and 25 and the semiconductor electrode wiring 26.
  • the first upper layer electrode wiring 23 is connected to another active element (not shown) via a buried conductor (not shown) and a semiconductor electrode wiring (not shown).
  • the second upper layer electrode wiring 47 is connected to the source region 12a of another active element 12 through the buried conductors 24, 25, 49, 50 and the semiconductor electrode wiring 26 as shown in FIG.
  • the third upper layer electrode wiring 58 is connected to another active element (not illustrated) through a buried conductor (not illustrated) and a semiconductor electrode wiring (not illustrated). It is connected.
  • the first-stage lower-layer electrode wiring 15 and the first upper-layer electrode wiring 23 are either bit lines or word lines, and are connected to the bit line decoder and the word line decoder of the circuit shown in FIG.
  • first upper layer electrode wiring 23 and the second upper layer electrode wiring 47 are either bit lines or word lines, respectively, and are connected to the bit line decoder and the word line decoder of the circuit shown in FIG. However, in the first stage, when the first upper layer electrode wiring 23 forms a bit line, the second stage also forms a bit line, and the second upper layer electrode wiring 47 forms a word line. Designed to be
  • the third upper layer electrode wiring 58 is designed to constitute a bit line.
  • the non-ohmic elements 17, 41, 52 are individually provided for the storage units 21, 45, 56 provided in the respective stages. Since it is provided, it is possible to stably and reliably write to and read from the storage units 21, 45, and 56 provided in the respective stages.
  • the manufacturing process of the nonvolatile semiconductor memory device 40 having such a multi-stage storage unit and a non-ohmic element is basically the same as the manufacturing process described in the nonvolatile semiconductor memory device 10 of the first embodiment. . Further, the manufacturing process described in the nonvolatile semiconductor memory device 30 of the second embodiment may be repeated.
  • FIG. 15 is a cross-sectional view showing configurations of a non-ohmic element 72 and a storage unit 81 which are main parts of the nonvolatile semiconductor memory device 70 according to the fourth embodiment of the present invention.
  • the nonvolatile semiconductor memory device 70 according to the present embodiment is a conductor material that does not easily diffuse into the resistance change layer 82 between the embedded electrode 75 and the resistance change layer 82 and that does not oxidize or reduce the resistance change layer 82.
  • the upper electrode 78 is composed of at least two layers, and the connection electrode 79 is also provided on the surface side connected to the resistance change layer 82.
  • a conductive material such as Pt, Ir, TaN or titanium nitride (TiN) can be used.
  • connection electrode 79 the upper layer electrode is connected to the connection electrode 79 and is used in a semiconductor process, for example, a conductive material made of Al or Cu, for example, in a stripe shape intersecting the lower layer electrode wiring 71.
  • a wiring 80 is formed.
  • connection electrode 79 may be extended to the outside of the matrix region so that the connection electrode 79 functions as part of the upper layer electrode wiring. Since other configurations including the interlayer insulating layer 76 are the same as those of the nonvolatile semiconductor memory device 10 according to the first embodiment, description thereof is omitted.
  • connection electrode 79 is selected from an optimum material that exhibits a good resistance change phenomenon in accordance with the combination with the resistance change layer 82, and is selected independently of the connection electrode 79. Since the upper layer electrode wiring 80 can be provided by using a material, an optimum material can be selected for each of the connection electrode 79 and the upper layer electrode wiring 80. Further, when a silicon single crystal substrate on which a semiconductor circuit including an active element such as a transistor is formed is used, electrical connection between the upper electrode wiring and the active element can be easily performed.
  • the lower electrode 73, the insulator layer 74, and the buried electrode 75 that is a metal electrode body layer constitute a non-ohmic element 72 made of an MIM diode.
  • the storage portion 81 is configured by the connection electrode 77 formed in a buried manner, the resistance change layer 82, and the connection electrode 79 in a region connected to the resistance change layer 82.
  • the non-ohmic element 72 the lower electrode 73 and the buried electrode 75 are formed of Al, and silicon nitride (SiN) is used as the insulator layer 74.
  • SiN can be easily formed into a thin film having a good insulating property and a dense thin film by forming by a sputtering method, and can be easily processed into a stripe shape by using a general semiconductor process technology.
  • the present invention is not limited to this.
  • an aluminum oxide (AlO) film or a titanium oxide (TiO) film may be used.
  • AlO any method such as a method of directly forming an AlO film by a dry thermal oxidation method, a wet thermal oxidation method, a plasma oxidation method or a reactive sputtering method after forming an Al film may be used.
  • connection electrodes 77 and 79 are provided on both surfaces of the resistance change layer 82.
  • the connection electrodes 77 and 79 are not essential.
  • a configuration similar to that of the nonvolatile semiconductor memory device 10 of the first embodiment or the nonvolatile semiconductor memory device 30 of the second embodiment may be adopted.
  • FIG. 16 is a cross-sectional view showing a configuration of a non-ohmic element 92 and a storage unit 96 which are main parts of the nonvolatile semiconductor memory device 90 according to the fifth embodiment of the present invention.
  • the nonvolatile semiconductor memory device 90 according to the present embodiment is characterized in that the non-ohmic element 92 is constituted by a pn junction diode having a stacked structure of an n-type semiconductor layer 93 and a p-type semiconductor layer 94.
  • the present embodiment is characterized in that the p-type semiconductor layer 94 constituting the non-ohmic element 92 is buried in the contact hole together with the buried electrode 97.
  • the n-type semiconductor layer 93 may be embedded together with the embedded electrode 97.
  • the storage unit 96 includes a buried electrode 97, a resistance change layer 98, and an upper layer electrode wiring 99 connected to the resistance change layer 98.
  • the lower layer electrode wiring 91, the interlayer insulating layer 95, and the upper layer electrode wiring 99 The basic configuration is the same as that of the nonvolatile semiconductor memory device 10 of the first embodiment, but the variable resistance layer 98 is connected to the buried electrode 97 on the interlayer insulating layer 95 and has a shape larger than the contact hole. It is the characteristic that it is formed.
  • the resistance change layer 98 may be formed in a stripe shape intersecting the lower layer electrode wiring 91 in the same manner as the upper layer electrode wiring 99.
  • the variable resistance layer 98 is formed on the interlayer insulating layer 95.
  • the nonvolatile semiconductor memory device 10 of the first embodiment and the nonvolatile semiconductor memory device 30 of the second embodiment are used. Similarly to the above, it may be embedded in the contact hole.
  • n-type semiconductor material for constituting such a pn junction diode for example, any one selected from ZnO, CdO, SnO 2 , TiO 2 , CeO 2 , Fe 3 O 4 , WO 3 , and Ta 2 O 5 is used.
  • the p-type semiconductor material for example, any material selected from FeO, NiO, CoO, Cu 2 O, and MnO 2 can be used.
  • p-type doped silicon and n-type doped silicon can also be used.
  • the non-ohmic element is the MSM diode described in the first or second embodiment, the MIM diode described in the fourth embodiment, or the pn junction type described in the fifth embodiment.
  • a Schottky diode that forms a Schottky connection with a semiconductor layer and a buried electrode may be used.
  • the configuration of the nonvolatile semiconductor memory device in this case includes the nonvolatile semiconductor memory device 10 shown in FIG. 1, the nonvolatile semiconductor memory device 30 shown in FIG. 4, the nonvolatile semiconductor memory device 70 shown in FIG.
  • the configuration may be similar to that of the nonvolatile semiconductor memory device 90 shown.
  • the non-ohmic element is a Schottky diode having a laminated structure of two layers of a semiconductor layer and a metal electrode body layer, and the semiconductor layer has a shape larger than the contact hole and is a metal electrode body layer embedded An electrode is embedded in the contact hole. Furthermore, a configuration similar to that of the nonvolatile semiconductor memory device 40 having a stacked configuration as shown in FIG.
  • the non-ohmic element is a Schottky diode, the following effects can be obtained.
  • a Schottky diode is a majority carrier element unlike a pn junction diode, it does not accumulate minority carriers and can be accessed at high speed.
  • the diode configuration is simplified and the manufacturing process can be simplified.
  • the pn junction has a problem of characteristic change due to temperature, the Schottky junction is stable with respect to temperature, so that it is possible to widen restrictions on the heating conditions and the like during the manufacturing process.
  • the forward threshold voltage of the diode is high (about 0.5 V).
  • the forward threshold voltage is high. Is 0.2 V, so that disturbance during reading and writing can be suppressed.
  • FIG. 17 is a diagram showing the configuration of the non-ohmic element 102 and the storage unit 107, which are the main parts of the nonvolatile semiconductor memory device 100 according to the sixth embodiment of the present invention.
  • FIG. b) is a cross-sectional view taken along line 17A-17A in FIG.
  • the nonvolatile semiconductor memory device 100 has the same basic configuration as the nonvolatile semiconductor memory device 10 according to the first embodiment, but the lower electrode 103 and the semiconductor layer 104 that constitute the non-ohmic element 102. However, each storage unit 107 is formed separately. Further, the upper electrode wiring 109 is formed in a stripe shape on the interlayer insulating layer 106 so as to connect to the resistance change layer 108 and intersect the lower electrode wiring 101.
  • the non-ohmic element 102 includes an MSM diode composed of a lower electrode 103 that is a metal electrode body layer, a semiconductor layer 104, and a buried electrode 105.
  • the storage unit 107 includes a buried electrode 105, a resistance change layer 108, and an upper electrode wiring 109 in a region connected to the resistance change layer 108.
  • the non-ohmic element 102 is an MSM diode
  • the diode area can be increased and the semiconductor layer 104 can be formed thin. Therefore, it is possible not only to increase the current capacity but also to reduce the characteristic variation.
  • non-ohmic element 102 is not limited to the MSM diode, and may be configured as an MIM diode, an pn junction type diode, or a Schottky junction diode using an insulator layer instead of the semiconductor layer 104. is there.
  • both the lower electrode 103 and the semiconductor layer 104 included in the non-ohmic element 102 are formed separately for each memory portion 107, but only the semiconductor layer 104 is formed separately.
  • the lower electrode 103 may be formed in the same stripe shape as the lower layer electrode wiring 101.
  • the non-ohmic element 102 is provided separately for each storage unit 107 in this embodiment, a plurality of non-ohmic elements 102 may be separated together.
  • non-volatile semiconductor memory device of the sixth embodiment can also have a stacked configuration like the non-volatile semiconductor memory device 40 of the third embodiment.
  • the nonvolatile semiconductor memory device of the present invention can increase the current capacity while simplifying the manufacturing method, and in addition to the variation in characteristics of non-ohmic elements and stabilization of breakdown voltage. It is useful in the field of electronic equipment.
  • Non-volatile semiconductor memory device (ReRAM) DESCRIPTION OF SYMBOLS 11 Substrate 12 Active element 12a Source region 12b Drain region 12c Gate insulating film 12d Gate electrode 13, 14 Semiconductor interlayer insulating layer 15, 71, 91, 101 Lower layer electrode wiring 15a Wiring groove 16, 31, 32, 76, 95, 106 Insulating layer 17 Non-ohmic element (first non-ohmic element) 18, 73, 103 Lower electrode (first lower electrode) 19, 104 Semiconductor layer 20, 75, 97, 105 Embedded electrode (metal electrode body layer) 20a, 23a Electrode thin film layer 21 Memory

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Abstract

L'invention porte sur un dispositif mémoire non volatil à semi-conducteur. Le dispositif est muni d’une configuration de point de croisement qui comprend des éléments non ohmiques et une couche à résistance variable composé d'une couche isolante d'intercouche (16) formée sur un substrat (11) qui comprend un câblage d'électrode de couche inférieure (15), des trous de contact formés dans la couche isolante d'intercouche du câblage d'électrode de couche inférieure, des éléments non ohmiques (17) formés sur le câblage d'électrode de couche inférieure (15), des couches à résistance variable (22) incorporées dans les trous de contact et formées sur les éléments non ohmiques (17), et un câblage d'électrode de couche supérieure (23) connecté aux couches à résistance variable (22) et formé sur la couche isolante d'intercouche (16). Dans un élément non ohmique (17), au moins une couche qui comprend une couche semi-conductrice ou une couche isolante dans une structure en couche empilée d'une pluralité de couches semi-conductrices, une structure à couches empilées de couches d'électrode métallique et de couches semi-conductrices, ou une structure à couches empilées de couches d'électrode métallique et de couches isolantes, est formée pour être plus grande que le trou de contact ; les autres couches de la structure à couches empilées sont formées pour être contenues dans le trou de contact.
PCT/JP2009/002148 2008-05-16 2009-05-15 Dispositif mémoire non volatil à semi-conducteur et son procédé de fabrication Ceased WO2009139185A1 (fr)

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