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WO2008126292A1 - 遅延時間計測方法、遅延時間調整方法及び可変遅延回路 - Google Patents

遅延時間計測方法、遅延時間調整方法及び可変遅延回路 Download PDF

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Publication number
WO2008126292A1
WO2008126292A1 PCT/JP2007/057220 JP2007057220W WO2008126292A1 WO 2008126292 A1 WO2008126292 A1 WO 2008126292A1 JP 2007057220 W JP2007057220 W JP 2007057220W WO 2008126292 A1 WO2008126292 A1 WO 2008126292A1
Authority
WO
WIPO (PCT)
Prior art keywords
delay
delay time
delay elements
reference clock
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/057220
Other languages
English (en)
French (fr)
Inventor
Masazumi Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/057220 priority Critical patent/WO2008126292A1/ja
Priority to KR1020097018867A priority patent/KR101099179B1/ko
Priority to CN2007800521473A priority patent/CN101627538B/zh
Priority to JP2009508839A priority patent/JP4809473B2/ja
Publication of WO2008126292A1 publication Critical patent/WO2008126292A1/ja
Priority to US12/542,861 priority patent/US7977988B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

　可変遅延回路１は、遅延素子Ｄ１～Ｄｎが直列に接続された多段遅延回路２０と、１個又は複数個の遅延素子Ｄ１～Ｄｎに基準クロックを通過させて得られる遅延量が違う遅延信号のうちいずれかを選択する選択部２１と、複数の遅延信号から順次選択した信号の信号論理を、基準クロックに同期した判定タイミングでそれぞれ判定する判定部２３と、この判定タイミングにおいて基準クロックの論理に変化が生じている遅延素子Ｄｍ、Ｄｋを少なくとも２個検出する変化点検出部２４と備え、検出された２個の遅延素子Ｄｍ、Ｄｋにそれぞれ至るまでにクロック信号が通過する遅延素子の個数の差（ｋ－ｍ）を所望の遅延時間を生じる遅延素子の個数として用いる。
PCT/JP2007/057220 2007-03-30 2007-03-30 遅延時間計測方法、遅延時間調整方法及び可変遅延回路 Ceased WO2008126292A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
PCT/JP2007/057220 WO2008126292A1 (ja) 2007-03-30 2007-03-30 遅延時間計測方法、遅延時間調整方法及び可変遅延回路
KR1020097018867A KR101099179B1 (ko) 2007-03-30 2007-03-30 지연 시간 계측 방법, 지연 시간 조정 방법 및 가변 지연 회로
CN2007800521473A CN101627538B (zh) 2007-03-30 2007-03-30 延迟时间测量方法、延迟时间调节方法及可变延迟电路
JP2009508839A JP4809473B2 (ja) 2007-03-30 2007-03-30 遅延時間計測方法、遅延時間調整方法及び可変遅延回路
US12/542,861 US7977988B2 (en) 2007-03-30 2009-08-18 Delay adjusting method, and delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/057220 WO2008126292A1 (ja) 2007-03-30 2007-03-30 遅延時間計測方法、遅延時間調整方法及び可変遅延回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/542,861 Continuation US7977988B2 (en) 2007-03-30 2009-08-18 Delay adjusting method, and delay circuit

Publications (1)

Publication Number Publication Date
WO2008126292A1 true WO2008126292A1 (ja) 2008-10-23

Family

ID=39863473

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/057220 Ceased WO2008126292A1 (ja) 2007-03-30 2007-03-30 遅延時間計測方法、遅延時間調整方法及び可変遅延回路

Country Status (5)

Country Link
US (1) US7977988B2 (ja)
JP (1) JP4809473B2 (ja)
KR (1) KR101099179B1 (ja)
CN (1) CN101627538B (ja)
WO (1) WO2008126292A1 (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101103065B1 (ko) * 2010-02-25 2012-01-06 주식회사 하이닉스반도체 딜레이 회로
CN102227110B (zh) * 2011-06-17 2014-06-25 华为技术有限公司 测量单向时延的方法、设备和通信系统
CN102520338B (zh) * 2011-12-22 2015-10-21 上海华虹宏力半导体制造有限公司 延迟时间测量电路、延迟时间测量方法
CN106464481B (zh) * 2014-05-23 2018-07-24 三菱电机株式会社 通信装置以及通信方法
US20160080138A1 (en) * 2014-09-17 2016-03-17 Telefonaktiebolaget L M Ericsson (Publ) Method and apparatus for timing synchronization in a distributed timing system
US9613679B2 (en) * 2014-11-14 2017-04-04 Cavium, Inc. Controlled dynamic de-alignment of clocks
US9601181B2 (en) 2014-11-14 2017-03-21 Cavium, Inc. Controlled multi-step de-alignment of clocks
WO2018214056A1 (zh) * 2017-05-24 2018-11-29 深圳市乃斯网络科技有限公司 网络链路中时延的校验方法及系统
JP2019113939A (ja) * 2017-12-21 2019-07-11 ルネサスエレクトロニクス株式会社 半導体装置
CN108287482A (zh) * 2018-01-02 2018-07-17 北京新能源汽车股份有限公司 一种基于Simulink的仿真控制方法及装置
JP7338685B2 (ja) * 2019-06-21 2023-09-05 株式会社ソシオネクスト 可変遅延回路および半導体集積回路
CN111157878A (zh) * 2019-12-31 2020-05-15 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） 焊点测试结构及其测试方法
CN117452187B (zh) * 2023-11-15 2024-07-23 广东高云半导体科技股份有限公司 一种io延迟测试电路及方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321590A (ja) * 1996-05-30 1997-12-12 Sanyo Electric Co Ltd 可変遅延線回路
JP2003023343A (ja) * 2001-07-10 2003-01-24 Mitsubishi Electric Corp 遅延信号生成回路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5451894A (en) * 1993-02-24 1995-09-19 Advanced Micro Devices, Inc. Digital full range rotating phase shifter
JP3510966B2 (ja) * 1997-07-24 2004-03-29 隆 成富 ブラインド式防寒シャッター
JPH11306757A (ja) 1998-04-27 1999-11-05 Mitsubishi Electric Corp 同期型半導体記憶装置
JP3769940B2 (ja) * 1998-08-06 2006-04-26 株式会社日立製作所 半導体装置
KR20060131788A (ko) * 2003-11-20 2006-12-20 주식회사 아도반테스토 가변 지연 회로

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09321590A (ja) * 1996-05-30 1997-12-12 Sanyo Electric Co Ltd 可変遅延線回路
JP2003023343A (ja) * 2001-07-10 2003-01-24 Mitsubishi Electric Corp 遅延信号生成回路

Also Published As

Publication number Publication date
US7977988B2 (en) 2011-07-12
KR20100005014A (ko) 2010-01-13
KR101099179B1 (ko) 2011-12-27
US20090302910A1 (en) 2009-12-10
CN101627538A (zh) 2010-01-13
JPWO2008126292A1 (ja) 2010-07-22
JP4809473B2 (ja) 2011-11-09
CN101627538B (zh) 2012-06-27

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