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WO2008114307A1 - 遅延回路及び該回路の試験方法 - Google Patents

遅延回路及び該回路の試験方法 Download PDF

Info

Publication number
WO2008114307A1
WO2008114307A1 PCT/JP2007/000232 JP2007000232W WO2008114307A1 WO 2008114307 A1 WO2008114307 A1 WO 2008114307A1 JP 2007000232 W JP2007000232 W JP 2007000232W WO 2008114307 A1 WO2008114307 A1 WO 2008114307A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
delay circuit
switched
output
time lag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/000232
Other languages
English (en)
French (fr)
Inventor
Koji Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to PCT/JP2007/000232 priority Critical patent/WO2008114307A1/ja
Priority to JP2009504900A priority patent/JPWO2008114307A1/ja
Publication of WO2008114307A1 publication Critical patent/WO2008114307A1/ja
Priority to US12/541,211 priority patent/US20090302917A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)

Abstract

　通常動作と試験動作を選択する信号により遅延回路の動作を切り替え、遅延回路の動作が通常動作に切り替えられた場合には、通常動作入力より設定された遅延時間を経て通常動作出力へ信号を伝送する。また遅延回路の動作が試験動作に切り替えられた場合には、遅延回路の出力を反転して試験動作ループが形成されるとともに遅延時間により決定される周期の発振波形が出力され、それを計数回路で遅延時間により決定される数の計数を行う。
PCT/JP2007/000232 2007-03-16 2007-03-16 遅延回路及び該回路の試験方法 Ceased WO2008114307A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/JP2007/000232 WO2008114307A1 (ja) 2007-03-16 2007-03-16 遅延回路及び該回路の試験方法
JP2009504900A JPWO2008114307A1 (ja) 2007-03-16 2007-03-16 遅延回路及び該回路の試験方法
US12/541,211 US20090302917A1 (en) 2007-03-16 2009-08-14 Delay circuit and test method for delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/000232 WO2008114307A1 (ja) 2007-03-16 2007-03-16 遅延回路及び該回路の試験方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/541,211 Continuation US20090302917A1 (en) 2007-03-16 2009-08-14 Delay circuit and test method for delay circuit

Publications (1)

Publication Number Publication Date
WO2008114307A1 true WO2008114307A1 (ja) 2008-09-25

Family

ID=39765428

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/000232 Ceased WO2008114307A1 (ja) 2007-03-16 2007-03-16 遅延回路及び該回路の試験方法

Country Status (3)

Country Link
US (1) US20090302917A1 (ja)
JP (1) JPWO2008114307A1 (ja)
WO (1) WO2008114307A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011069756A (ja) * 2009-09-28 2011-04-07 Hitachi Ltd 半導体集積回路
JP2020010422A (ja) * 2018-07-03 2020-01-16 ローム株式会社 信号伝達装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2979506B1 (fr) * 2011-08-30 2013-08-30 Bull Sas Procede de synchronisation d'une grappe de serveurs et grappe de serveurs mettant en oeuvre ce procede
US9083201B2 (en) * 2011-09-14 2015-07-14 Hamilton Sundstrand Corporation Load shedding circuit for RAM air turbines
KR20160029378A (ko) * 2014-09-05 2016-03-15 에스케이하이닉스 주식회사 반도체 장치
JP6610216B2 (ja) * 2015-12-02 2019-11-27 富士通株式会社 遅延回路および遅延回路の試験方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199415A (ja) * 1984-10-15 1986-05-17 テクトロニツクス・インコーポレイテツド 周波数カウンタ装置
JPH04299274A (ja) * 1991-03-28 1992-10-22 Nec Corp 半導体集積回路
JPH08181541A (ja) * 1994-12-22 1996-07-12 Advantest Corp デジタル周波数シンセサイザ
JPH1197990A (ja) * 1997-09-24 1999-04-09 Advantest Corp 可変遅延回路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5828717A (en) * 1995-03-28 1998-10-27 Matsushita Electric Industrial Co. Ltd. Time counting circuit and counter circuit
JPH08292242A (ja) * 1995-04-24 1996-11-05 Advantest Corp 遅延時間安定化回路
JP3309782B2 (ja) * 1997-06-10 2002-07-29 日本電気株式会社 半導体集積回路
JP2001339282A (ja) * 2000-05-30 2001-12-07 Advantest Corp 可変遅延回路及び半導体回路試験装置
US6680874B1 (en) * 2002-08-29 2004-01-20 Micron Technology, Inc. Delay lock loop circuit useful in a synchronous system and associated methods
US7254505B2 (en) * 2005-06-29 2007-08-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and apparatus for calibrating delay lines
JP2007017158A (ja) * 2005-07-05 2007-01-25 Sharp Corp テスト回路、遅延回路、クロック発生回路、及び、イメージセンサ
JP2007235908A (ja) * 2006-02-02 2007-09-13 Sharp Corp リング発振回路、遅延時間測定回路、テスト回路、クロック発生回路、イメージセンサ、パルス発生回路、半導体集積回路、及び、そのテスト方法
JP5183269B2 (ja) * 2008-03-28 2013-04-17 株式会社アドバンテスト バーニア遅延回路、それを用いた時間デジタル変換器および試験装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6199415A (ja) * 1984-10-15 1986-05-17 テクトロニツクス・インコーポレイテツド 周波数カウンタ装置
JPH04299274A (ja) * 1991-03-28 1992-10-22 Nec Corp 半導体集積回路
JPH08181541A (ja) * 1994-12-22 1996-07-12 Advantest Corp デジタル周波数シンセサイザ
JPH1197990A (ja) * 1997-09-24 1999-04-09 Advantest Corp 可変遅延回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011069756A (ja) * 2009-09-28 2011-04-07 Hitachi Ltd 半導体集積回路
JP2020010422A (ja) * 2018-07-03 2020-01-16 ローム株式会社 信号伝達装置
JP7068075B2 (ja) 2018-07-03 2022-05-16 ローム株式会社 信号伝達装置

Also Published As

Publication number Publication date
US20090302917A1 (en) 2009-12-10
JPWO2008114307A1 (ja) 2010-06-24

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