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WO2008114654A1 - 試験装置および電子デバイス - Google Patents

試験装置および電子デバイス Download PDF

Info

Publication number
WO2008114654A1
WO2008114654A1 PCT/JP2008/054407 JP2008054407W WO2008114654A1 WO 2008114654 A1 WO2008114654 A1 WO 2008114654A1 JP 2008054407 W JP2008054407 W JP 2008054407W WO 2008114654 A1 WO2008114654 A1 WO 2008114654A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
sequence
memory
chache
tester
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/054407
Other languages
English (en)
French (fr)
Inventor
Tatsuya Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to DE112008000737T priority Critical patent/DE112008000737T5/de
Priority to JP2009505149A priority patent/JPWO2008114654A1/ja
Publication of WO2008114654A1 publication Critical patent/WO2008114654A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31919—Storing and outputting test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/31813—Test pattern generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

　被試験デバイスを試験する試験装置であって、被試験デバイスを試験するための試験シーケンスを定める試験命令列を記憶するメインメモリと、試験命令列をキャッシングするシーケンスキャッシュメモリと、メインメモリに記憶された試験命令列を読み出して、シーケンスキャッシュメモリに記述順序に従って書き込む転送部と、シーケンスキャッシュメモリにキャッシングされた試験命令列から順次に命令を読み出して実行し、実行した命令に対応する試験パターンを出力するパターン発生部と、試験パターンに応じた試験信号を生成し、被試験デバイスに供給する試験信号出力部とを備える試験装置を提供する。
PCT/JP2008/054407 2007-03-21 2008-03-11 試験装置および電子デバイス Ceased WO2008114654A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112008000737T DE112008000737T5 (de) 2007-03-21 2008-03-11 Prüfgerät und elektronische Vorrichtung
JP2009505149A JPWO2008114654A1 (ja) 2007-03-21 2008-03-11 試験装置および電子デバイス

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/689,483 US7725794B2 (en) 2007-03-21 2007-03-21 Instruction address generation for test apparatus and electrical device
US11/689,483 2007-03-21

Publications (1)

Publication Number Publication Date
WO2008114654A1 true WO2008114654A1 (ja) 2008-09-25

Family

ID=39765762

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/054407 Ceased WO2008114654A1 (ja) 2007-03-21 2008-03-11 試験装置および電子デバイス

Country Status (6)

Country Link
US (1) US7725794B2 (ja)
JP (1) JPWO2008114654A1 (ja)
KR (1) KR20090129474A (ja)
DE (1) DE112008000737T5 (ja)
TW (1) TWI365992B (ja)
WO (1) WO2008114654A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011154026A (ja) * 2010-01-26 2011-08-11 Advantest Corp 試験装置および試験方法
JP2015526700A (ja) * 2012-06-05 2015-09-10 ライトポイント・コーポレイションＬｉｔｅＰｏｉｎｔ Ｃｏｒｐｏｒａｔｉｏｎ ユーザーが定義した計測器コマンドシーケンスを複数のハードウェア及び分析モジュールを用いて実行するためのシステム及び方法
CN114184813A (zh) * 2021-11-26 2022-03-15 苏州安智汽车零部件有限公司 一种测试工装控制系统及方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008234822A (ja) * 2007-02-21 2008-10-02 Hitachi High-Technologies Corp 磁気ディスクの検査方法および磁気ディスク検査装置
KR20120069404A (ko) 2010-12-20 2012-06-28 삼성전자주식회사 테스터 및 이를 포함하는 테스트 시스템
US9134377B2 (en) * 2013-03-14 2015-09-15 Teradyne, Inc. Method and apparatus for device testing using multiple processing paths
US9740411B2 (en) * 2014-09-04 2017-08-22 National Instruments Corporation Configuring circuitry with memory access constraints for a program
KR20170023439A (ko) * 2015-08-24 2017-03-06 삼성전자주식회사 메모리 테스트 시스템 및 메모리 시스템
US10139449B2 (en) 2016-01-26 2018-11-27 Teradyne, Inc. Automatic test system with focused test hardware
US10242750B2 (en) * 2017-05-31 2019-03-26 Sandisk Technologies Llc High-speed data path testing techniques for non-volatile memory
CN111208383A (zh) * 2018-11-20 2020-05-29 Oppo（重庆）智能科技有限公司 设备点检方法及装置、设备自动测试线、存储介质
US11852680B1 (en) * 2022-08-09 2023-12-26 Nanya Technology Corporation Test device and test method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63216151A (ja) * 1987-03-04 1988-09-08 Fujitsu Ltd 記憶装置の試験機
JP2000206210A (ja) * 1999-01-19 2000-07-28 Advantest Corp パタ―ン発生器、パタ―ン発生方法及び試験装置
JP2002521698A (ja) * 1998-07-30 2002-07-16 クリーダンス システムズ コーポレイション アルゴリズミックパターン発生器
WO2004109307A1 (ja) * 2003-06-09 2004-12-16 Advantest Corporation パターン発生器、及び試験装置
JP2006252361A (ja) * 2005-03-14 2006-09-21 Matsushita Electric Ind Co Ltd 半導体集積回路

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5249286A (en) * 1990-05-29 1993-09-28 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
US5210850A (en) * 1990-06-15 1993-05-11 Compaq Computer Corporation Memory address space determination using programmable limit registers with single-ended comparators
US5487162A (en) * 1992-02-25 1996-01-23 Matsushita Electric Industrial Co., Ltd. Cache lock information feeding system using an address translator
JPH1078476A (ja) 1996-09-02 1998-03-24 Advantest Corp 半導体試験装置用パターン発生器
US6836868B1 (en) * 2000-10-31 2004-12-28 Credence Systems Corporation High-speed algorithmic pattern generator
US20050198442A1 (en) * 2004-03-02 2005-09-08 Mandler Alberto R. Conditionally accessible cache memory
JP4486383B2 (ja) * 2004-03-08 2010-06-23 株式会社アドバンテスト パターン発生器、及び試験装置
US7756695B2 (en) * 2006-08-11 2010-07-13 International Business Machines Corporation Accelerated simulation and verification of a system under test (SUT) using cache and replacement management tables

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63216151A (ja) * 1987-03-04 1988-09-08 Fujitsu Ltd 記憶装置の試験機
JP2002521698A (ja) * 1998-07-30 2002-07-16 クリーダンス システムズ コーポレイション アルゴリズミックパターン発生器
JP2000206210A (ja) * 1999-01-19 2000-07-28 Advantest Corp パタ―ン発生器、パタ―ン発生方法及び試験装置
WO2004109307A1 (ja) * 2003-06-09 2004-12-16 Advantest Corporation パターン発生器、及び試験装置
JP2006252361A (ja) * 2005-03-14 2006-09-21 Matsushita Electric Ind Co Ltd 半導体集積回路

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011154026A (ja) * 2010-01-26 2011-08-11 Advantest Corp 試験装置および試験方法
JP2015526700A (ja) * 2012-06-05 2015-09-10 ライトポイント・コーポレイションＬｉｔｅＰｏｉｎｔ Ｃｏｒｐｏｒａｔｉｏｎ ユーザーが定義した計測器コマンドシーケンスを複数のハードウェア及び分析モジュールを用いて実行するためのシステム及び方法
CN114184813A (zh) * 2021-11-26 2022-03-15 苏州安智汽车零部件有限公司 一种测试工装控制系统及方法
CN114184813B (zh) * 2021-11-26 2024-04-16 苏州安智汽车零部件有限公司 一种测试工装控制系统及方法

Also Published As

Publication number Publication date
JPWO2008114654A1 (ja) 2010-07-01
US7725794B2 (en) 2010-05-25
KR20090129474A (ko) 2009-12-16
DE112008000737T5 (de) 2010-01-14
TW200844461A (en) 2008-11-16
US20080235539A1 (en) 2008-09-25
TWI365992B (en) 2012-06-11

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