WO2008110994A2

WO2008110994A2 - Integrated circuit with power-down circuit portions

Info

Publication number: WO2008110994A2
Application number: PCT/IB2008/050896
Authority: WO
Inventors: Zeljko Mrcarica
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2007-03-13
Filing date: 2008-03-12
Publication date: 2008-09-18
Anticipated expiration: 2009-09-13
Also published as: WO2008110994A3

Abstract

An integrated circuit (100) is disclosed comprising a plurality of circuit portions (120, 140) including a first circuit portion (120) coupled to switchable power means (VDD2, VSS) for selectively switching the first circuit portion (120) between a powered down state and a powered up state. The first circuit portion (120) has a plurality of inputs (124) and a plurality of outputs (122), with each output (122) being coupled to an input (144) of another circuit portion(140) via a signal path (130) comprising an output buffer (126) arranged to adopt a high impedance state in the powered down state. Each signal path (130) to a further circuit portion (140) further comprises, between its output buffer (126) and its associated input (144), a clamp (132) coupled to further power means (VDD) for clamping the signal path (130) to a fixed logic value during said powered down state. This arrangement provides well-defined values on the signal lines (130) connected to the outputs (122) of a powered down circuit portion (120) without the need for additional control logic.

Description

DESCRIPTION

INTEGRATED CIRCUIT WITH POWER-DOWN CIRCUIT PORTIONS

The present invention relates to an integrated circuit (IC) comprising a plurality of circuit portions including a first circuit portion coupled to switchable power means for selectively switching the first circuit portion between a powered down state and a powered up state, the first circuit portion having a plurality of outputs, each output being coupled to an input of another circuit portion via a signal path.

The present invention further relates to a circuit portion for such an integrated circuit.

In contemporary IC design, many efforts have been made to reduce the power consumption of the IC. This is for instance relevant to ICs that are integrated in battery-powered electronic devices, because the energy efficiency of the incorporated IC has a direct correlation with the lifetime of the battery of the electronic device. For such devices, leakage power of inactive circuits or circuit portions is especially important, since most of the time those circuits or portions are in standby mode, i.e. not active. A popular design methodology to reduce the leakage power consumption of an IC is to disable those circuit portions of the IC that are not involved with the current task of the IC. There are several ways that this may be implemented; each circuit portion may have its own power supply, with the power supply being disabled during an inactive period of the circuit portion, or the circuit portions may be coupled to the same power supply via respective power switches that may be disabled if the circuit portion is not required to be active, and so on.

A well-known implication of powering down circuit portions of an IC is that the outputs of such a powered-down circuit portion may assume undefined logic values. This can jeopardize the correct operation of the IC, for instance if such an output is coupled to an input of an active circuit portion, where the undefined value can cause erroneous behaviour. It is therefore necessary to ensure that the outputs of a powered-down circuit portion maintain a well-defined value during its powered-down state. A possible implementation of a protection against the occurrence of such undefined logic values involves the addition of a logic gate to each of the outputs of a circuit portion that may be powered down. An example of such an implementation is given in: http://www.edn ■Com/index.asp?lavout=article&articleid=CA6301624, which was retrieved from the internet on Thursday March 1 , 2007. The logic gates are typically added for isolation of circuit portions. The output of the circuit portion is coupled to one input of the logic gate and a control signal being coupled to the other input of the logic gate. For instance, the logic gate may be an AND gate, with the control signal being a logic '0' during power- down mode of the circuit portion, and a logic "T in active mode of the circuit portion. The logic '0' state of the control signal ensures that the output of the AND gate produces a logic '0' regardless of the logic value of the output of the powered-down circuit portion.

The drawback of this approach is that a large number of logic gates as well as dedicated control logic for generating the control signals of the logic gates is required. In addition, the control logic has to have awareness of the powered states of the circuit portions it controls, which adds complexity and overhead to the design of the IC.

The present invention seeks to provide an integrated circuit according to the opening paragraph that does not require control logic for ensuring that the logic values on the outputs of a powered-down circuit portion cannot jeopardize the correct operation of another part of the IC.

According to an aspect of the present invention, there is provided an IC according to the opening paragraph wherein each signal path comprises an output buffer, which may be integrated in the circuit portion, arranged to adopt a high impedance state in the powered down state, each signal path further comprising between its output buffer and its associated input a clamp coupled to further power means for clamping the signal path to a fixed logic value in said powered down state. The invention is based on the realization that the clamp on the signal line, e.g. a weak pull-up or pull-down transistor, ensures that the signal line to which the clamp is coupled in maintains at the clamp value, while the buffer that switches to a high-impedance state in a powered down mode ensures that the output is conductively isolated from the signal line. The latter is important to ensure that no leakage currents can flow from the clamped signal line through the powered-down circuit portion, because the occurrence of such leakage currents, which is typically expected to occur when using clamps, would defeat the object of the powering down of the circuit portion, i.e. the reduction of unnecessary power consumption by the IC. Optionally, each input of the first circuit portion is coupled to an output of another voltage island via a signal path comprising an input buffer, which may be integrated in the first circuit portion, each input buffer being arranged to be powered down together with the first circuit portion.

The clamps used on the signal lines may be clamps that ensure that the last known logic value on the output before power-down is maintained on the signal line, or may be clamps that pull the signal line to a logic high or a logic low during the powered down state. Preferably, the clamps are monostable clamps to ensure that the clamps have minimal interference with the signal line when the first circuit portion is an active mode. A preferred embodiment of a monostable clamp for pulling the signal line to a logic low comprises an inverter having its input coupled to the output of the first circuit portion and having its output coupled to the input of an nMOS transistor having its drain coupled to the signal line and its source coupled to a low potential source of the further power means. This has the advantage that the clamp is disabled when the output is actively driven by the first circuit portion at a logic high. A preferred embodiment of a monostable clamp for pulling the signal line to a logic high comprises an inverter having its input coupled to the output of the first circuit portion and having its output coupled to the input of an pMOS transistor having its source coupled to a high potential source of the further power means and its drain coupled to the signal line. This has the advantage that the clamp is disabled when the output is actively driven by the first circuit portion at a logic low.

The invention is described in more detail and by way of non-limiting examples with reference to the accompanying drawings, wherein:

Fig. 1 depicts an embodiment of an IC according to the present invention;

Fig. 2 depicts another embodiment of an IC according to the present invention; Fig. 3 depicts a possible embodiment of an output buffer that adopts a high impedance state when powered down;

Fig. 4 shows an example of a monostable pull-down clamp connected in parallel to its signal line;

Fig. 5 shows an example of a monostable pull-down clamp connected in series with its signal line;

Fig. 6 shows an example of a monostable pull-up clamp connected in parallel to its signal line;

Fig. 7 shows an example of a monostable pull-up clamp connected in series with its signal line; Fig. 8 shows an example of a monostable clamp keeping a last known value connected in parallel to its signal line;

Fig. 9 shows an example of a monostable clamp keeping a last known value connected in series to its signal line; and

Fig. 10 shows an electronic device comprising an IC according to the present invention. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts. Fig. 1 shows a first embodiment of an IC 100 of the present invention including a first circuit portion 120 and further circuit portions 140, as well as a data communication bus 160. In general, a circuit portion is defined as any functional unit of an IC that can communicate with another functional unit of the IC. The first circuit portion 120 is selectably connected to power supply lines VDD2 and VSS, i.e. the first circuit portion 120 can be selected to be disconnected from its power supply, as indicated by the switch in the supply line VDD2. It will be appreciated that a switch implementation is shown by way of non-limiting example only; other ways of powering down the first circuit portion 120 are equally feasible. The first circuit portion 120 has a number of outputs 122 that are connected to the inputs 144 of further circuit portions 140 via signal paths 130 including high-impedance buffers 126, i.e. buffer elements that provide a high-impedance output in a powered-down state. The high impedance buffers 126 should be disconnected from their power supply when the first circuit portion 120 is powered down. Preferably, the high impedance buffers 126 are fed by the same power supply rails, i.e. power supply lines VDD2 and VSS, as the first circuit portion 120.

The signal paths 130 include a clamp 132 coupled to the signal line in between the output buffer 126 and input 144. In Fig. 1 , the clamps 132 are coupled in parallel with the inputs 144. In operation, as soon as the first circuit portion 120 is powered down, the clamps 132, which may be specially designed weak pull-up or weak pull-down transistors, as will be explained in more detail later, or which are memory elements, ensure that the signal paths 130 will exhibit a well-defined logic value throughout the powered-down period of the first circuit portion 120. The clamps 132 are typically connected to a power supply that is always enabled, or that is disabled The high-impedance buffers 126 in the signal paths 130 ensure that there is no substantial leakage current path from the clamps 132 to the first circuit portion 120. In short, the combination of the clamps 132 and the high-impedance buffers 126 makes it possible to use tie-off cells, e.g. pull-up or pull-down transistors, in a power- efficient manner. It is usually also required that the circuit portion 120 does not disturb a data communication bus when it is in the powered down mode. Therefore, the output 122 that is coupled to the bus 160 also comprises a buffer 126 that switches to a high-impedance state. However, it usually is not necessary to clamp the signal line to the bus 160 to a given logic value. The first circuit portion 120 further has a plurality of inputs 124, which may be respectively coupled to various outputs 142 of further circuit portions 140 or to the data communication bus 160. Optionally, the inputs 124 may receive the incoming signals through an input buffer 128 that is disconnected from its power supply whenever the first circuit portion 120 is disconnected from its power supply. Preferably, the input buffers 128 are connected to the same power supply as the first circuit portion 120. This arrangement is advantageous in situations where a leakage current path exists through the inputs 124 in a powered-down mode of the first circuit portion 120, which for instance is the case when the input is conductively coupled to electrostatic discharge protection arrangements or to antenna protection diodes, which for instance may share the VDD2 supply line with the first circuit portion 120. In such cases, a logic "T on the supply line to an input 124 of a powered down first circuit portion 120 activates a leakage current path via the aforementioned protective measures. The presence of a simple input buffer 128 in this signal path that powers down together with the first circuit portion 120 prevents that this leakage path can become active.

Because the output buffers 126 and optional input buffers 128 are preferably powered by the same power supply as the first circuit portion 120, these buffers may be included in the design of the first circuit portion 120, as indicated by the dashed line around the first circuit portion 120 in Fig. 1. This is for instance advantageous if the first circuit portion 120 is sold as a separate component, e.g. an IP block, or an IC to be included in a larger IC, e.g. a multi- chip module or a system-in-package.

The further circuit portions 140 shown in Fig.1 are coupled to power supply lines VDD1 and VSS and VDD3 and VSS respectively. It will be appreciated that this is by way of non-limiting example only. The further circuit portions 140 may be coupled to different power supplies or may share a power supply. The further circuit portions 140 themselves may be selectively disconnectable from their respective power supplies or may be permanently powered-up when the IC 100 is powered up. If the further circuit portions 140 operate at voltages different to the operational voltage of the first circuit portion 120, the signal lines 130 typically will comprise voltage level-shifter circuits (not shown). The clamps 132 may be integrated in these level-shifter circuits.

Fig. 2 shows an alternative embodiment of an IC 100 according to the present invention, in which the clamps 132 are serially connected between the high-impedance output buffers 126 and the inputs 142 in the respective signal paths 130. This requires a modification to the clamps 132 compared to the parallel arrangement shown in Fig. 1 , as will be discussed in more detail below.

High-impedance buffers 126 as shown in Fig. 1 and 2 are known as such, and are also known as fail-safe buffers. An example of such a buffer in CMOS technology is given in Fig. 3. When powered up, the nMOS transistor 252 and pMOS transistor 256 drive the n-wells (indicated by black squares 250) of pMOS transistors 254, 258 and 260 as well as the pMOS transistor of the inverter 280 to the high voltage potential of the power supply, e.g. V_dcι. When powered up, the transmission gate 240 is open and the output of inverter 280 is functionally driven, i.e. by output 122 via the inverter 220. The pMOS transistors 254, 258 and 260 are switched off.

When the high-impedance buffer 126 is powered down, e.g. disconnected from power supply VDD2, pMOS transistor 258 connects the n- well to the value of the output signal on output 290. When the output 290, i.e. the signal line 130, is high, thus creating the conditions under which a potential leakage current may occur, the n-well is also high and the drain-bulk parasitic diode of the buffer towards the n-well is not directly polarized. In addition, the transmission gate 240 is switched off, and because pMOS transistor 260 connects the gate of the pMOS transistor in the inverter 280 to the voltage level on the output pin 290, the pMOS transistor of the inverter 280 is also switched off. Consequently, all potential leakage paths through the output 290 of the high-impedance buffer 126 are disabled, causing the buffer 126 to exhibit the high-impedance behaviour in its powered-down state.

Fig. 4 shows an embodiment of a monostable weak pull-down clamp 400 according to the present invention as an embodiment of a clamp 132 that is connected to the signal path 130 in parallel with input 144 of a further circuit portion 140. The pull-down clamp 400 comprises a nMOS transistor 420 that has its source and drain respectively connected to the ground and the signal line 130. The gate of the nMOS transistor 420 is connected to the signal line 130 via an inverter 410. When the first circuit portion is powered up, e.g. exhibits a logic high on the output 122, the clamp 400 is effectively disabled because the inverter 410 will force the gate of nMOS transistor 420 to a logic low, thus disabling the nMOS transistor 420. Consequently, the pull-down clamp 400 does not interfere with a logic high on the signal line 130 in active mode of the first circuit portion 120. When the first circuit portion 120 is powered down with a logic high on its output 122, the buffer 126 goes to the high impedance state, the leakage current through the nMOS transistor 420 will lower the voltage on the signal line 430, which willcause the gate of the nMOS transistor 420 to become activated. This will accelerate the driving of the signal line 130 to a logic low. With the signal line 130 at the logic low, the nMOS transistor 420 is fully enabled, thus clamping the signal line 130 at the logic low.

It is pointed out that the pull-down clamp 400 will have an impact on the switching behaviour of the signal line 130 in active mode of the first circuit portion 120, especially when the output 122 switches from a logic low to a logic high. However, this transition is very quick, thus causing the nMOS transistor 420 to disable quickly, which means that the additional currents through the nMOS transistor 420 during this transition are very modest and have no significant impact on the power consumption of the IC 100.

Fig. 5 shows a monostable pull-down clamp 500 that is serially connected between the high-impedance buffer 126 and the input 144. The pull-down clamp 500 differs from the pull-down clamp 400 in that the inverter 410 is placed in the signal line 130 and that the clamp comprises a further inverter 510 in the signal line 130 that ensures that the input 144 is provided with the correct logic value, with the gate of the nMOS transistor 420 being coupled to a signal line node between the inverter 410 and the further inverter 510.

Fig. 6 shows an embodiment of a monostable weak pull-up clamp 600 according to the present invention as an embodiment of a clamp 132 that is connected to the signal path 130 in parallel with input 144 of a further circuit portion 140. The pull-up clamp 400 comprises a pMOS transistor 620 that has its source and drain respectively connected to Vdd and the signal line 130. The gate of the pMOS transistor 620 is connected to the signal line 130 via an inverter 610. When the first circuit portion is powered up, and exhibits a logic low on the output 122, the clamp 600 is effectively disabled because the inverter 610 will force the gate of pMOS transistor 620 to a logic high, thus disabling the pMOS transistor 620. Consequently, the pull-up clamp 600 does not interfere with the logic low on the signal line 130 in active mode of the first circuit portion 120.

When the first circuit portion 120 is powered down and has a logic low on its output 122, the leakage current through the pMOS transistor 620 will increase the voltage on the signal line 430, which will cause the gate of the pMOS transistor 620 to become activated. This will accelerate the driving of the signal line 130 to a logic high. With the signal line 130 at the logic high, the pMOS transistor 620 is fully enabled, thus clamping the signal line 130 at the logic high. It is pointed out that the pull-up clamp 600 will have an impact on the switching behaviour of the signal line 130 in active mode of the first circuit portion 120, especially when the output 124 switches from a logic high to a logic low. However, this transition is very quick, thus causing the pMOS transistor 620 to disable quickly, which means that the additional currents through the pMOS transistor 620 during this transition are very modest and have no significant impact on the power consumption of the IC 100. Fig. 7 shows a monostable pull-up clamp 700 that is serially connected between the high-impedance buffer 126 and the input 144. The pull-up clamp 700 differs from the pull-up clamp 600 in that the inverter 610 is placed in the signal line 130 and that the clamp comprises a further inverter 710 in the signal line 130 that ensures that the input 144 is provided with the correct logic value, with the gate of the pMOS transistor 620 being coupled to a signal line node between the inverter 610 and the further inverter 710.

For completeness sake, it is pointed out that a monostable clamp is stable, i.e. does not exhibit currents in excess of a predefined threshold, in one of the two binary logic states only. Fig. 8 shows an embodiment of a bistable memory clamp 800 as an embodiment of a clamp 132 that is connected to the signal path 130 in parallel with input 144 of a further circuit portion 140. The memory clamp 800 clamps the signal line 130 to the last known value of the output 122 before disabling the first circuit portion 120. To this end, the memory clamp 800 comprises a pair of cross-coupled inverters 810 and 820 that share a node of the signal line 130. Because the inverters 810 and 820 are coupled to a permanent power supply source, the memory clamp 800 acts as a memory element for the output 122. The clamp is designed in such a way that any change in the logic value on output 122 driven by internal logic of the first circuit portion 120 will override the value stored in the memory clamp 800. It is emphasized that such clamps are known per se, but are typically used in a different functional context, e.g. as bus-keeper cells.

Fig. 9 shows a bistable memory clamp 900 that is serially connected between the high-impedance buffer 126 and the input 144. The memory clamp 900 differs from the memory clamp 800 in that the inverter 810 is placed in the signal line 130 and that the clamp comprises a further inverter 910 in the signal line 130 that ensures that the input 144 is provided with the correct logic value.

Fig. 10 shows an embodiment of an electronic device 1000 according to the present invention. The electronic device 1000 has a power supply 1020, which may be a battery, coupled to the IC 100 according to the present invention. The electronic device 1000 further comprises a user-interface 1040 that is coupled to the power supply 1020 and the IC 100. The user-defined operations may cause the IC portion 120 to be switched off, thus activating the clamps on the signal lines 130 as previously described. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to an advantage.

Claims

1. An integrated circuit (100) comprising a plurality of circuit portions (120, 140) including a first circuit portion (120) coupled to switchable power means (VDD2, VSS) for selectively switching the first circuit portion (120) between a powered down state and a powered up state, the first circuit portion (120) having a plurality of inputs (124) and a plurality of outputs (122), each output (122) being coupled to an input (144) of another circuit portion (140) via a signal path (130) comprising an output buffer (126) arranged to adopt a high impedance state in the powered down state, each signal path (130) further comprising, between its output buffer (126) and its associated input (144), a clamp (132) coupled to further power means (VDD) for clamping the signal path (130) to a fixed logic value during said powered down state.

2. An integrated circuit (100) as claimed in claim 1 , wherein the output buffers (126) are integrated in the first circuit portion (120).

3. An integrated circuit as claimed in claim 1 , wherein at least one clamp is integrated in a circuit portion (140) coupled to an output of the first circuit portion.

4. An integrated circuit (100) as claimed in claim 1 or 2, wherein each input (124) of the first circuit portion (120) is coupled to an output (142) of another circuit portion (140) via a signal path comprising an input buffer (128), each input buffer (128) being arranged to be powered down together with the first circuit portion (120).

5. An integrated circuit (100) as claimed in claim 3 or 4, wherein the input buffers (128) are integrated in the first circuit portion.

6. An integrated circuit (100) as claimed in claim 1 or 2, wherein each clamp (132) is coupled to its signal path (130) in parallel with the input (144) associated with said signal path (130).

7. An integrated circuit (100) as claimed in claim 1 or 2, wherein each clamp (132) is coupled in series between the output buffer (126) and the input (140).

8. An integrated circuit (100) as claimed in claim 1 or 2, wherein at least one clamp (132) is a monostable clamp (400, 500, 600, 700).

9. An integrated circuit (100) as claimed in claim 8, wherein the at least one clamp (400, 500) is arranged to clamp its signal line to a logic low, said clamp comprising: an inverter (410) having its input coupled to the output (122) of the first circuit portion (120) and having its output coupled to the input of an nMOS transistor (420) having its drain coupled to the signal line (130) and its source coupled to a low potential source of the further power means.

10. An integrated circuit (100) as claimed in claim 8, wherein the at least one clamp (600, 700) is arranged to drive its signal line to a logic high, said clamp comprising: an inverter (610) having its input coupled to the output (122) of the first circuit portion (120) and having its output coupled to the input of an pMOS transistor (620) having its source coupled to a high potential source (VDD) of the further power means and its drain coupled to the signal line (130).

11. An integrated circuit (100) as claimed in claim 1 or 2, wherein at least one signal path comprises a level shifter circuit including the clamp (132).

12. A circuit portion (120) for use in the integrated circuit (100) of claim 1 , the circuit portion (120) comprising a plurality of inputs (124) and a plurality of outputs (122), each output (122) comprising an output buffer (126) arranged to adopt a high impedance state in a powered down state of the circuit portion (120).

13. A circuit portion (120) as claimed in claim 12, wherein each input (124) comprises an input buffer (128) being arranged to be powered down together with the circuit portion (120).

14. An electronic device (1000) comprising: an integrated circuit (100) as claimed in claim 1 ; and a power supply (1020) coupled to the integrated circuit (100).