[go: up one dir, main page]

WO2008110994A3 - Integrated circuit with power-down circuit portions - Google Patents

Integrated circuit with power-down circuit portions Download PDF

Info

Publication number
WO2008110994A3
WO2008110994A3 PCT/IB2008/050896 IB2008050896W WO2008110994A3 WO 2008110994 A3 WO2008110994 A3 WO 2008110994A3 IB 2008050896 W IB2008050896 W IB 2008050896W WO 2008110994 A3 WO2008110994 A3 WO 2008110994A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit portion
powered down
circuit
coupled
signal path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2008/050896
Other languages
French (fr)
Other versions
WO2008110994A2 (en
Inventor
Zeljko Mrcarica
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of WO2008110994A2 publication Critical patent/WO2008110994A2/en
Publication of WO2008110994A3 publication Critical patent/WO2008110994A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit (100) is disclosed comprising a plurality of circuit portions (120, 140) including a first circuit portion (120) coupled to switchable power means (VDD2, VSS) for selectively switching the first circuit portion (120) between a powered down state and a powered up state. The first circuit portion (120) has a plurality of inputs (124) and a plurality of outputs (122), with each output (122) being coupled to an input (144) of another circuit portion(140) via a signal path (130) comprising an output buffer (126) arranged to adopt a high impedance state in the powered down state. Each signal path (130) to a further circuit portion (140) further comprises, between its output buffer (126) and its associated input (144), a clamp (132) coupled to further power means (VDD) for clamping the signal path (130) to a fixed logic value during said powered down state. This arrangement provides well-defined values on the signal lines (130) connected to the outputs (122) of a powered down circuit portion (120) without the need for additional control logic.
PCT/IB2008/050896 2007-03-13 2008-03-12 Integrated circuit with power-down circuit portions Ceased WO2008110994A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP07104014 2007-03-13
EP07104014.1 2007-03-13

Publications (2)

Publication Number Publication Date
WO2008110994A2 WO2008110994A2 (en) 2008-09-18
WO2008110994A3 true WO2008110994A3 (en) 2009-01-29

Family

ID=39760176

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2008/050896 Ceased WO2008110994A2 (en) 2007-03-13 2008-03-12 Integrated circuit with power-down circuit portions

Country Status (1)

Country Link
WO (1) WO2008110994A2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654862A (en) * 1995-04-24 1997-08-05 Rockwell International Corporation Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654862A (en) * 1995-04-24 1997-08-05 Rockwell International Corporation Method and apparatus for coupling multiple independent on-chip Vdd busses to an ESD core clamp

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KAIJIAN SHI: "Dual threshold voltages and power-gating design flows offer good results", EDN: ELECTRONICS DESIGN, STRATEGY NEWS, 2 February 2006 (2006-02-02), pages 65 - 70, XP002503531 *

Also Published As

Publication number Publication date
WO2008110994A2 (en) 2008-09-18

Similar Documents

Publication Publication Date Title
US7071756B1 (en) Clock multiplexing system
US7759973B1 (en) Integrated circuit having embedded differential clock tree
JP2007504752A5 (en)
WO2002089329A3 (en) Fpga logic element with variable-length shift register capability
WO2008042709A3 (en) Enhanced doherty amplifier with asymmetrical semiconductors
WO2009046135A3 (en) Power supply system for low power mcu
US7129765B2 (en) Differential clock tree in an integrated circuit
GB2446318A (en) Polarity driven dynamic on-die termination
WO2009059172A3 (en) Built in self test for input/output characterization
WO2001086813A3 (en) Fpga lookup table with dual ended writes for ram and shift register modes
US20180026632A1 (en) Ultra-low power cross-point electronic switch apparatus and method
WO2009088695A3 (en) Extending drive capability in integrated circuits utilizing programmable-voltage output circuits
WO2004075403A3 (en) Electronic circuit with array of programmable logic cells
US20110267106A1 (en) Low-power routing multiplexers
TW200631319A (en) Dual-voltage three-state buffer circuit with simplified tri-state level shifter
TW200705265A (en) A method and system for elastic signal pipelining
WO2005078729A3 (en) High voltage driver circuit with fast reading operation
WO2008110994A3 (en) Integrated circuit with power-down circuit portions
US7142033B2 (en) Differential clocking scheme in an integrated circuit having digital multiplexers
DE60132038D1 (en) Load equalization in digital delay circuits with interpolation
TWI343706B (en) Isolation circuit
Jeong et al. 0.37 mW/Gb/s low power SLVS transmitter for battery powered applications
EP1833166A8 (en) High-frequency electronic switch, bust wave generation device using the same, and short pulse radar using the same
CN106357265A (en) Small-area high-speed six-input searching table structure
AU2003235769A1 (en) A crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08719654

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08719654

Country of ref document: EP

Kind code of ref document: A2