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WO2008012871A1 - Dispositif à mémoire à semi-conducteur rémanente - Google Patents

Dispositif à mémoire à semi-conducteur rémanente Download PDF

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Publication number
WO2008012871A1
WO2008012871A1 PCT/JP2006/314649 JP2006314649W WO2008012871A1 WO 2008012871 A1 WO2008012871 A1 WO 2008012871A1 JP 2006314649 W JP2006314649 W JP 2006314649W WO 2008012871 A1 WO2008012871 A1 WO 2008012871A1
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WO
WIPO (PCT)
Prior art keywords
voltage
circuit
resistance
memory element
nonvolatile semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2006/314649
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English (en)
Japanese (ja)
Inventor
Yoshihiro Sato
Hiroshi Iwasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2008526625A priority Critical patent/JP5012802B2/ja
Priority to PCT/JP2006/314649 priority patent/WO2008012871A1/fr
Publication of WO2008012871A1 publication Critical patent/WO2008012871A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • Nonvolatile semiconductor memory device includes
  • the present invention relates to a nonvolatile semiconductor memory device using a resistance memory element whose resistance state is changed by applying an electrical stimulus.
  • the nonvolatile semiconductor memory device is called a RRAM (Resistance Random Access Memory), and uses a resistance memory element whose resistance state is changed by applying an electrical stimulus from the outside as a memory cell. Then, the high resistance state and the low resistance state of the resistance memory element are associated with, for example, information “0” or “1”.
  • RRAM Resistance Random Access Memory
  • a resistance memory element As a typical example of a resistance memory element, an oxide material containing a transition metal is known.
  • a resistance memory element having the above-described characteristics changes from a high resistance state to a low resistance state.
  • the resistance value changes greatly, and the resistance value changes abruptly. Therefore, in order to prevent the phenomenon that an excessive current flows through the resistance memory element when writing data, the RRAM needs to limit the current (current compliance) at a predetermined timing.
  • Patent Document 1 the voltage value at one end of the resistance memory element is monitored, and the monitored result is input to the sense amplifier circuit.
  • a plurality of resistance elements are used to A reference voltage of the sense amplifier circuit is created, and writing is stopped when the resistance value of the resistance memory element changes to the resistance value of the predetermined reference resistance.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-234707
  • the present invention has been made in view of the above-described problems, and can be surely written in a short time and has a writing circuit having a simple circuit configuration.
  • An object is to provide a storage device.
  • the above problems can be solved by a novel circuit configuration using the characteristic that the resistance state of the resistance memory element changes during writing (not in flash memory or the like).
  • the present invention has been found and the present invention has been made.
  • a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage (within the writing circuit) that changes according to the change in the resistance state, the voltage is received by a monitor circuit having a predetermined threshold, and the resistance change is instantaneously triggered by the change in the voltage.
  • the solution to the problem is realized by limiting the power supply to the device.
  • a nonvolatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by applying a voltage, and supplies power to the resistance memory element. And a voltage applying circuit for generating a first voltage at one end of the resistance memory element, and a predetermined threshold voltage, and detecting that the first voltage has reached the predetermined threshold voltage. There is provided a non-volatile semiconductor memory device having a monitor circuit and a cutoff circuit for restricting power supply from the voltage applying circuit to the resistance memory element based on the detection of the monitor circuit.
  • a high resistance state and a low resistance state by application of a voltage A non-volatile semiconductor memory device having a resistance memory element that is switched between when the resistance memory element is in a high-resistance state, the power source is supplied to the resistance memory element, and a first end of the resistance memory element is A first voltage applying circuit for generating a voltage; and a power supply to the resistance memory element when the resistance memory element is in a low resistance state, and a second voltage lower than the first voltage at one end of the resistance memory element.
  • a second voltage applying circuit for generating the first voltage a first monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the first threshold voltage; A second monitor circuit having a predetermined threshold voltage and detecting that the first voltage has reached the second threshold voltage; and based on the detection of the first monitor circuit.
  • a second cutoff circuit that cuts off the voltage application to the resistance memory element based on the detection of the second monitor circuit.
  • a non-volatile semiconductor memory device is provided.
  • a non-volatile semiconductor memory device having a resistance memory element that switches between a high resistance state and a low resistance state by application of a voltage, and a power source is supplied to the resistance memory element. And a voltage application circuit for generating a first voltage at a predetermined location of a memory cell including the resistance memory element, and a predetermined threshold voltage, the first voltage being a predetermined threshold! /, Value There is provided a non-volatile semiconductor memory device that includes a monitor circuit that detects that the voltage has been reached, and that limits power supply from the voltage application circuit to the resistance memory element based on the detection of the monitor circuit .
  • the present invention at the time of writing, a high voltage is applied to the resistance memory element to change its resistance state. Then, paying attention to the voltage that changes according to the change in the resistance state (in the write circuit), the current supply to the resistance memory element is instantaneously limited by using the predetermined change in the voltage as a trigger, Thus, reliable writing can be performed, and such writing processing can be realized with a simple circuit.
  • FIG. 1 is a graph showing the current-voltage characteristics of a resistance memory element using a unipolar resistance memory material.
  • FIG. 2 is a diagram showing a basic configuration of a memory cell in a nonvolatile semiconductor memory device
  • FIG. 3 is a circuit diagram showing a memory cell array 20 in which memory cells 10 are arranged in a matrix.
  • FIG. 4 is a block diagram illustrating a schematic configuration of a peripheral circuit according to the first embodiment.
  • FIG. 5 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.
  • FIG. 6 is a timing chart illustrating a write operation of the set driver circuit according to the first embodiment.
  • FIG. 7 is a circuit diagram illustrating an example of a reset driver circuit according to the first embodiment.
  • FIG. 8 is a timing chart showing a write operation of the reset driver circuit according to the first embodiment.
  • FIG. 9 is a graph showing the relationship between the ratio of the gate width of nMOS to the gate width of pMOS and the threshold voltage of the input section in the input section of the monitor circuit having a CMOS structure.
  • Fig. 1 is a graph showing the current-voltage characteristics of a resistance memory element using a unipolar resistance memory material. This graph shows the case of using TiO, which is a typical example of a unipolar resistive memory material.
  • the initial state of the resistance memory element be point a.
  • the current gradually increases along curve A.
  • the resistance memory element switches (sets) to the low resistance state as well as the high resistance state force. Accordingly, the absolute value of the current increases rapidly, and the current-voltage characteristic transitions from the high resistance state of curve A to the low resistance state shown by curves C and D.
  • the current value from point b to point c is constant at 2mA (straight line B), but this is due to current limitation. That is, the resistance memory element has already transitioned to the low resistance state at the time point b.
  • the current limitation is removed at the time point c. Then, as the voltage is gradually decreased from point c, the current changes along the curve C in the direction of the arrow, and its absolute value gradually decreases. Conversely, when the applied voltage is gradually increased again, the current changes along the curve D in the direction of the arrow, and its absolute value gradually increases.
  • the resistance memory element switches (resets) from the low resistance state to the high resistance state.
  • the absolute value of the current sharply decreases, and the current-voltage characteristics transition from the d point to the e point.
  • the current-voltage characteristics follow curve A in the high resistance state if the applied voltage is lower than the voltage at point b (about 1.5V). Changes linearly and maintains a high resistance state. Similarly, in the low resistance state, if the applied voltage is lower than the voltage at point d (approximately 0.7V), the current-voltage characteristics change along curve C, and the low resistance state is maintained.
  • FIG. 2A is a circuit diagram showing a memory cell in the nonvolatile semiconductor memory device
  • FIG. 2B is a schematic sectional view showing a structure of the memory cell in the nonvolatile semiconductor memory device.
  • FIG. 2 shows a configuration common to the conventional nonvolatile semiconductor memory device and the nonvolatile semiconductor memory device of this embodiment.
  • the memory cell 10 of the nonvolatile semiconductor memory device includes a resistance memory element 12 and a cell selection transistor 14 as shown in FIG.
  • the resistance memory element 12 has one end connected to the bit line BL and the other end connected to the drain D of the cell selection transistor 14.
  • the source S of the cell selection transistor 14 is connected to the source line SL, and the gate G is connected to the word line WL.
  • the resistance memory element 12 has a resistance memory material 12b sandwiched between a pair of electrodes (12a, 12c).
  • the resistance memory material 12b is, for example, a unipolar resistance memory material having a TiO force.
  • the bit line BL extends parallel to the paper surface, and the source line SL and the word line WL extend toward the back, that is, perpendicular to the paper surface.
  • FIG. 3 is an example of a circuit diagram showing a memory cell array 20 in which the memory cells 10 shown in FIG. 2 are arranged in a matrix.
  • the plurality of memory cells 10 are arranged adjacent to each other in the column direction (vertical direction in the drawing) and the row direction (horizontal direction in the drawing).
  • a plurality of word lines WL1, * WL1, WL2, * WL2 ',... are arranged in the row direction, and are connected to the memory cells 10 arranged in the row direction.
  • source lines SL1, SL2,... are arranged and connected to the memory cells 10 arranged in the row direction.
  • the number of source lines equal to or greater than the number of word lines is provided in relation to the amount of power supply noise, etc., in which one source line is provided for every two word lines. It's okay.
  • a plurality of bit lines BL1, BL2, BL3, BL4-... Are arranged in the column direction, and are connected to the memory cells 10 arranged in the column direction.
  • Each bit line BL is provided with a bit line selection transistor 16 having a function as a variable resistance element.
  • FIG. 4 is a block diagram illustrating a schematic configuration of the peripheral circuit according to the first embodiment.
  • the peripheral circuit for the memory cell array 20 described above includes a set driver circuit 30 and a reset driver circuit 40 that write data to the memory cell 10, and data reading from the memory cell 10.
  • the reading circuit 28 for performing the above and the control circuit 26 for controlling these circuits are also configured.
  • the memory cell array 20 includes a word line selector 22 for selecting the word line WL and a bit line selector for selecting the bit line BL. 24 is also included.
  • the memory cell portion in the memory cell array 20 corresponds to, for example, a circuit similar to the circuit shown in FIG. 3 described above. In FIG. 4, for convenience of illustration, this memory cell portion is included in the circuit. The wiring is partially omitted.
  • the memory cell 10 is selected by the word line selector 22 and the bit line selector 24.
  • the word line selector 22 and the bit line selector 24 are also connected to the address line 25. Address setting to the address line 25 is performed by the control circuit 26.
  • the set driver circuit 30 includes a voltage application circuit 32 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, a monitor circuit 34 that detects the voltage of the bit line, and a monitor circuit 34. In response to this notification, the power supply to the memory cell 10 is cut off.
  • the set driver circuit 30 has a precharge circuit 38 that sets the voltage of the bit line BL to a predetermined value before writing.
  • the precharge circuit 38 avoids a malfunction in the writing process.
  • the reset driver circuit 40 includes a voltage application circuit 42 that applies a predetermined voltage (and current) to the memory cell 10 selected at the time of writing, and a monitor circuit 4 that detects the voltage of the bit line.
  • shut-off circuit 46 which receives the notification from the monitor circuit 44 and shuts off the power supply to the memory cell 10, is also configured.
  • the reset driver circuit 40 includes a precharge circuit 48 that sets the voltage of the bit line BL to a predetermined value before writing.
  • the precharge circuit 48 avoids malfunctions in the write process.
  • the control circuit 26 includes a CPU (Central Processing Unit) 26a, a memory 26b that stores a control program for the CPU 26a, a bus 26c that transmits signals between them, and the like.
  • a CPU Central Processing Unit
  • memory 26b that stores a control program for the CPU 26a
  • bus 26c that transmits signals between them, and the like.
  • the control circuit 26 has the above-described configuration, and controls the write operation in the set driver circuit 30 and the reset driver circuit 40 via (via) the control signals 27a and 27b.
  • the read operation in the read circuit 28 is controlled by the control signal 27c.
  • the control circuit 26 also controls the memory cell array 20 by the control signal 27d.
  • the read circuit 28 includes a sense amplifier (not shown), and the voltage of the bit line BL is measured by the sense amplifier to recognize the storage state of the selected memory cell.
  • FIG. 5 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.
  • the memory cell array 20 is arranged between the bit line BL and the reference voltage Vss.
  • the resistance memory element 12 and the cell selection transistor 14 are connected in series. Specifically, one end of the resistance memory element 12 is connected to the bit line BL, and the other end is connected to the drain D of TR11.
  • the source S of TR11 is connected to the reference voltage Vss, and the gate G of TR11 is connected to the word line WL.
  • the resistance value of the resistance memory element 12 is several k ⁇ in the low resistance state, and several ten ⁇ to 1000 kQ in the high resistance state. Unlike a normal resistor, the resistance memory element 12 has a very small area dependency on the resistance value.
  • the cell selection transistors 14 connected in series to the resistance memory element 12 need to be provided in the same number as the resistance memory elements 12, it is desirable that the area be as small as possible.
  • the cell selection transistor 14 having a small area
  • the cell selection transistor 14 having an on-resistance of about 2 k ⁇ .
  • the resistance value in the low resistance state is about 4 k ⁇ (and the maximum current during the reset operation) so that the necessary voltage is applied to the cell selection transistor 14. It is desirable to use a resistance memory element 12 that has a current of about several hundred A.
  • the set voltage application circuit 32 includes a current mirror circuit having TR32 and TR33.
  • the current mirror circuit is a stable power supply connected to the power supply Vdd.
  • the end opposite to the side connected to the power supply Vdd is connected to the drain D of the bit line BL and TR31 as shown in the figure.
  • the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS, and the transistors (TR32, TR33 constituting the current mirror circuit). ) Is preferably pMOS.
  • TR31 is provided between the set voltage application circuit 32 and a cutoff circuit 36 described later, and enables the operation of the set driver circuit 30 at the time of writing.
  • the drain D of TR31 is connected to the source S of TR32, that is, the node N1, and the source 3 of Ding 1 ⁇ 31 is connected to the cutoff circuit 36 (specifically, the drain D of TR34).
  • TR31 gate G allows write Connected to the set write enable signal SetWE. When performing the writing process, set the SetWE signal in advance to a high level (for example, approximately 1.5 to 1.7 V).
  • the cutoff circuit 36 is provided between the aforementioned TR31 and the reference voltage Vss.
  • the cutoff circuit 36 includes, for example, a transistor TR34 disposed between TR31 and the reference voltage Vss, and its drain D is connected to the source S of TR31.
  • the source S of TR34 is connected to the reference voltage Vss, and the output of the monitor circuit 34 is connected to the gate G of TR34.
  • the reference voltage Vss may be set to a ground (GND) level, for example.
  • the transistor TR 34 has, for example, an nMOS structure.
  • the monitor circuit 34 includes, for example, two inverters IN11 and IN12 connected in series as shown in the drawing.
  • the input of inverter IN11 is connected to bit line BL, and its output is connected to the input of inverter IN12.
  • the output of the inverter IN12 is connected to the gate G of the transistor TR34 constituting the cutoff circuit 36.
  • the threshold voltage (threshold voltage) is set to a value that can be recognized as the transition to the low resistance state. To do.
  • the threshold value of this IN11 is, for example, 1. OV to l. 2V. The optimum value depends on the material of the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. decide. There is no particular limitation on the subsequent inverter IN12.
  • threshold! /, Value voltage and “threshold voltage” are used as synonymous terms.
  • the inverter IN11 has a CMOS structure input section (not shown) in which, for example, a pMOS transistor and an nMOS transistor are also formed.
  • the threshold voltage of this input section becomes the threshold voltage of the monitor circuit 34.
  • FIG. 9 is a graph showing the relationship between the ratio of the nMOS gate width to the pMOS gate width and the threshold voltage of the input section in the input section of the monitor circuit having a CMOS structure. It is fu.
  • the threshold voltage can be controlled by changing the ratio of the gate width of the nMOS and the gate width of the pMOS. Specifically, by setting the ratio of the gate width of the nMOS to the gate width of the pMOS greater than 1, that is, by making the gate width of the pMOS wider than the gate width of the nMOS, the threshold voltage is changed from 1.0 V to 1. It can be 2 V.
  • the threshold voltage should be about 1. IV. Is possible.
  • the precharge circuit 38 is provided between the power supply Vdd and the bit line BL.
  • the precharge circuit 38 is disposed between, for example, the bit line BL and the power supply Vdd, has a transistor TR35 having a pMOS structure, and the drain D of TR35 is connected to the power supply Vdd.
  • the gate G of TR35 is connected to the control signal PrSET from the control circuit 26, and the source S of TR35 is connected to the bit line BL.
  • FIG. 6 is a timing chart illustrating the write operation of the set driver circuit according to the first embodiment.
  • Step 1 First, the bit line BL is precharged.
  • the set precharge signal PrSET is set to Low level to turn on TR35 so that the bit line BL has substantially the same voltage value as the power supply Vdd.
  • the voltage of the power supply Vdd is about 1.8V, for example.
  • the precharge circuit 38 determines one end of the resistance memory element 12 at a predetermined voltage before applying a voltage to the resistance memory element 12.
  • Step 2 Next, the SetWE signal is enabled in this state. That is, the SetWE signal is set to High level to turn on TR31. At this time, already after step 1 precharge Since TR34 is in the on state, when TR31 is turned on, the voltage value of node N1 drops significantly, and a large current easily flows through the path of L1.
  • Step 3 Next, precharge of the bit line BL is stopped.
  • the set precharge signal PrSET is returned to the high level (for example, about 1.5V to 1.8V), and TR35 is turned off.
  • the precharge circuit 38 turns on the internal transistor TR35 to set one end of the resistance memory element 12 to a predetermined voltage, and then turns off the transistor 35 to stop the precharge.
  • Step 4 Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address for the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on. At the same time as TR11 is turned on, a high voltage (for example, about 1.6 V) that can be set to the resistance memory element 12 is applied. The voltage applied to the resistance memory element is shown in the graph “VR” in FIG.
  • Step 5 Next, the resistance memory element 12 is set. That is, when a high voltage that can be set is applied for a predetermined time (several ns to 50 ns), the resistance memory element 12 enters the set state, and the resistance memory element 12 rapidly changes to the low resistance state in addition to the high resistance state force. To do.
  • the voltage application circuit 32 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and then (switches the resistance state).
  • the resistance state is switched after a predetermined time has elapsed (after a voltage capable of being applied) is applied.
  • Step 6 Next, the set state is detected by the monitor circuit. That is, resistance memory element When the child 12 transitions to the low resistance state, the voltage of the bit line BL rapidly decreases accordingly. When the voltage value of the bit line BL becomes lower than the threshold voltage of the inverter IN11 in the monitor circuit 34 (for example, about 1. OV to l.2V), the monitor circuit 34 is activated.
  • the threshold voltage of the inverter IN11 in the monitor circuit 34 for example, about 1. OV to l.2V
  • the resistance memory element 12 is in the middle of transition to the low resistance state, that is, after the resistance state starts to be switched. It is desirable to set so that the voltage value of the bit line BL reaches the threshold voltage value of the inverter IN11 before the switching is completed.
  • the monitor circuit 34 changes (inverts) the logic of an internal logic element when the voltage of the bit line BL reaches a predetermined threshold voltage value. In other words, when the voltage value is low level, it changes from low level to high level, and when the voltage value is high level, it changes from high level to low level.
  • Step 7 Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 34 detects the set of the resistance memory element 12, and changes the output signal StatSET power Low level (for example, about 0V to 0.5V) of the monitor circuit. This StatSET can notify the completion of setting to the outside. When the StatSET signal goes low, TR34 in the cutoff circuit 36 turns off and the current in the L1 path is cut off.
  • the monitor circuit 34 detects the set of the resistance memory element 12, and changes the output signal StatSET power Low level (for example, about 0V to 0.5V) of the monitor circuit.
  • This StatSET can notify the completion of setting to the outside.
  • TR34 in the cutoff circuit 36 turns off and the current in the L1 path is cut off.
  • the current mirror circuit in the set voltage application circuit 32 is activated, and the current flowing through the path L2 is interrupted.
  • the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L1 is cut off is several ns to several tens ns.
  • the cutoff circuit 36 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element.
  • the current limiting circuit is the current mirror circuit
  • the blocking circuit 36 limits the amount of current supplied to the resistance memory element by blocking one current path in the current mirror circuit.
  • the voltage value applied to the resistance memory element 12 is a value at which the resistance state does not change (for example, 0.6 V The following). Therefore, when writing is performed in the steps as described above, the resistance state of the resistance memory element 12 remains unchanged. The set completion is immediately notified to the outside while maintaining the low resistance state.
  • FIG. 7 is a circuit diagram illustrating an example of a set driver circuit according to the first embodiment.
  • the reset voltage application circuit 42 is configured by a current mirror circuit having TR42 and TR43.
  • the current mirror circuit is a stable power supply connected to the power supply Vdd.
  • the end opposite to the side connected to the power supply Vdd is connected to the drain D of the bit line BL and TR41 as shown in the figure.
  • the cell selection transistor 14 (TR11) in the memory cell 10 is an nMOS and the transistors (TR42, TR43) constituting the current mirror circuit. ) Is preferably pMOS.
  • TR41 is provided between the reset voltage application circuit 42 and a cutoff circuit 46 described later, and enables the operation of the reset driver circuit 40 at the time of writing.
  • the drain D of TR41 is connected to the source S of TR42, ie, the node N2, and the source 3 of Ding 1 ⁇ 41 is connected to the cutoff circuit 46 (specifically, the drain D of TR44).
  • the gate G of TR41 is connected to a reset write enable signal ResetWE that permits writing. Write process In this case, this ResetWE signal is set to a high level (for example, about 1.5 to 1.7 V) in advance.
  • the cutoff circuit 46 is provided between the aforementioned TR41 and the reference voltage Vss.
  • the cutoff circuit 46 includes, for example, a transistor TR44 disposed between TR41 and the reference voltage Vss, and its drain D is connected to the source S of TR41.
  • the source S of TR44 is connected to the reference voltage Vss, and the output of the monitor circuit 44 is connected to the gate G of TR44.
  • the transistor TR44 has, for example, an nMOS structure.
  • the monitor circuit 44 has, for example, one inverter IN21 and a flip-flop circuit FF as shown in the figure.
  • the input of inverter IN21 is connected to bit line BL, and its output is connected to one input of flip-flop circuit FF.
  • the inverter IN21 is set to a value at which the threshold voltage can be recognized as having transitioned to the high resistance state.
  • the threshold voltage of IN21 is, for example, 1.0 V to 1.2 V, but the optimum value is determined according to the material constituting the resistance memory element 12 and the characteristics of the peripheral circuit of the resistance memory element 12. To do.
  • the inverter IN21 has, for example, a pMOS structure transistor and an nMOS structure transistor, and a CMOS structure input section (not shown).
  • the threshold voltage voltage monitor circuit 44 threshold of the input section is provided. Become a voltage. Note that. Since the relationship between the CMOS structure form of the inverter IN21 and the threshold voltage is the same as that of the monitor circuit in the set driver circuit, description thereof is omitted here.
  • the flip-flop circuit FF is composed of, for example, two NAND circuits (NA1, NA2). The output of this flip-flop circuit FF is connected to the gate G of TR44 in the cutoff circuit 46. The output of the inverter IN21 is connected to one input of the flip-flop circuit FF, and the X-StartRESET signal is connected to the other input. X—Star tRESET signal sets the output (StatRESET signal) of flip-flop circuit FF to High level.
  • the flip-flop circuit FF has completed the write operation by the reset driver circuit 40. After that, when the voltage of the bit line BL drops, TR44 of the cutoff circuit 46 is turned on again due to the voltage change, and the reset driver circuit 40 is prevented from restarting.
  • the monitor circuit 44 functions as a stable operation circuit that prevents the logic from changing again after the voltage of the bit line BL reaches a predetermined threshold voltage and the internal logic changes. It has a function. Further, the monitor circuit 44 has a function of enabling the unlocking of the logic from the outside as required by the X-StartRESET signal.
  • the precharge circuit 48 is provided between the bit line BL and the reference voltage Vss. It is done.
  • the precharge circuit 48 is disposed between the bit line BL and the reference voltage Vss, and includes a transistor TR45 having an nMOS structure, and the drain D of TR45 is connected to the bit line BL.
  • the TR45 gate G is connected to the control signal PrRES ET from the control circuit 26, and the TR45 source S is connected to the reference voltage Vss.
  • FIG. 8 is a timing chart illustrating the write operation of the reset driver circuit according to the first embodiment.
  • Step 1 First, precharge the bit line BL. That is, the reset precharge signal PrRESET is set to a high level (for example, about 1.5 to 1.8 V) to turn on TR45 so that the bit line BL has substantially the same voltage value as the reference voltage Vss. As described above, the precharge circuit 48 determines one end of the resistance memory element 12 at a predetermined voltage before the voltage is applied to the resistance memory element 12, and prevents malfunction of the circuit.
  • a high level for example, about 1.5 to 1.8 V
  • Step 2 Next, the memory cell 10 to be written is selected. That is, the control circuit 26 designates an address for the address line 25 and enables the word line WL of the memory cell 10. As a result, the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on.
  • the control circuit 26 designates an address for the address line 25 and enables the word line WL of the memory cell 10.
  • the word line WL becomes a high level (for example, 1.5 to 1.7 V), and the cell selection transistor TR11 is turned on.
  • Step 3 Next, the ResetWE signal is enabled. That is, the ResetWE signal for enabling the reset driver circuit 40 is set to a high level (for example, about 1.5 to 1.7 V) to turn on TR41. At this time, the transistor TR45 of the precharge circuit 48, the TR44 of the cutoff circuit 46, and the TR11 of the memory cell 10 are already in the ON state by the processing of Step 1 and Step 2, so that TR41 is turned on. The current mirror circuit is activated and a large current begins to flow through the L4 path.
  • a high level for example, about 1.5 to 1.7 V
  • the transistor TR45 of the precharge circuit 48 is on. Current flows through the precharge circuit 48 side, and almost no current flows through the LO path on the memory cell 10 side. Therefore, at this time, the voltage of the bit line BL is hardly changed, and the voltage value of the bit line BL is maintained substantially the same value (about OV to 0.5 V) as the reference voltage Vss. As a result, no high voltage is applied to the resistance memory element 12, and the resistance memory element 12 maintains a low resistance state.
  • Step 4 Next, precharge of the bit line BL is stopped.
  • the PrRESET signal is returned to the low level, TR45 is turned off, and the precharge is stopped.
  • the precharge is stopped and the X-StartRESET signal is changed from low level to high level.
  • TR11 is turned on, a high voltage (approximately 0.9 V) that can be set to the resistance memory element 12 is applied. The voltage applied to the resistance memory element is shown in the graph “VR J” in FIG.
  • Step 5 Next, the resistance memory element 12 is reset.
  • the resistance memory element 12 is reset, and the resistance memory element 12 rapidly changes from the low resistance state to the high resistance state.
  • the time required for the resistance memory element 12 to reset (the predetermined time) varies depending on conditions, and is usually several hundred ns to several tens of ms, but here, for example, 800 ns as shown in FIG.
  • the voltage application circuit 42 applies a voltage capable of switching the resistance state of the resistance memory element 12 to both ends of the resistance memory element 12, and (the resistance state can be switched). After a predetermined time (after the voltage is applied), the resistance state is switched.
  • Step 6 Next, the reset state is detected by the monitor circuit. That is, when the resistance memory element 12 transitions to the high resistance state, the voltage of the bit line BL rises accordingly. When the voltage value of the bit line BL becomes higher than the threshold voltage of the inverter IN21 in the monitor circuit 44 (for example, about 1. OV to l.2V), the monitor circuit 44 is activated. At this time, the StatRESET signal can be used to notify the outside that the reset has been completed.
  • the threshold voltage of the inverter IN21 in the monitor circuit 44 for example, about 1. OV to l.2V
  • the resistance state starts to switch during the transition of the resistance memory element 12 to the low resistance state. And before the switching is over, the bit line BL It is desirable to set so that the voltage value of reaches the threshold voltage of inverter IN21.
  • the logic of the internal logic element changes (inverts).
  • Step 7 Next, power supply to the resistance memory element 12 is cut off. That is, the monitor circuit 44 detects the reset of the resistance memory element 12, and the output signal StatRESET of the monitor circuit changes from the high level to the low level (for example, about OV to 0.5V). When the StatRESE T signal changes to Low level, TR44 in the cutoff circuit 46 is turned off, and the current in the L3 path is cut off.
  • the current mirror circuit in the voltage application circuit 42 is activated, and the current flowing through the path L4 is interrupted.
  • the time from when the resistance state of the resistance memory element 12 is switched to when the current in the path L4 is cut off is several ns to several tens ns.
  • the cutoff circuit 46 limits the current of the current limiting circuit that limits the amount of current supplied to the resistance memory element.
  • the current limiting circuit is, for example, the current mirror circuit as shown in FIG. 7, and the cutoff circuit 46 cuts off one of the current paths in the current mirror circuit to thereby supply the current amount to the resistance memory element. Limit.
  • the resistance memory element 12 when the resistance memory element 12 is in a high resistance state from the beginning, the voltage of the bit line BL is monitored immediately after applying a high voltage to the resistance memory element 12 in Step 4. It becomes higher than the threshold voltage value of circuit 21. Therefore, it can be realized by adjusting the power supply to the resistance memory element 12 to be instantaneously cut off in a time shorter than the time when the resistance state of the resistance memory element 12 changes (for example, several ns). It is. Also, immediately notify the outside of the reset completion.
  • the write circuit to the resistance memory element is combined with an element mainly composed of a field effect transistor (MOS FET: Metal Oxide Semiconductor Field Effect Transistor). Therefore, it is possible to easily manufacture a non-volatile memory device by using the conventional process for forming CMOS.
  • MOS FET Metal Oxide Semiconductor Field Effect Transistor

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

[PROBLEMS] Fournir un dispositif à mémoire à semi-conducteur rémanente comportant un circuit d'écriture de circuit simple par lequel l'écriture peut être effectuée de manière fiable en un temps court. [MEANS FOR SOLVING PROBLEMS] Le dispositif à mémoire à semi-conducteur rémanente possède un élément d'enregistrement à résistance dans lequel la commutation est réalisée entre un état de résistance élevée et un état de résistance faible en appliquant une tension. Le dispositif à mémoire à semi-conducteur rémanente comprend un circuit d'application de tension pour délivrer du courant à l'élément d'enregistrement à résistance et générer une première tension à une extrémité de celui-ci, un circuit de contrôle ayant une tension de seuil prédéterminée et détectant le fait que la première tension ait atteint la tension de seuil prédéterminée, et un circuit d'interruption pour limiter le courant délivré du circuit d'application de tension à l'élément d'enregistrement à résistance sur la base de la détection du circuit de contrôle.
PCT/JP2006/314649 2006-07-25 2006-07-25 Dispositif à mémoire à semi-conducteur rémanente Ceased WO2008012871A1 (fr)

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