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WO2008084765A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2008084765A1
WO2008084765A1 PCT/JP2008/050007 JP2008050007W WO2008084765A1 WO 2008084765 A1 WO2008084765 A1 WO 2008084765A1 JP 2008050007 W JP2008050007 W JP 2008050007W WO 2008084765 A1 WO2008084765 A1 WO 2008084765A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
semiconductor substrate
semiconductor device
insulating film
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2008/050007
Other languages
English (en)
French (fr)
Inventor
Shinya Yamakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2007329564A external-priority patent/JP5326274B2/ja
Application filed by Sony Corp filed Critical Sony Corp
Priority to CN2008800001064A priority Critical patent/CN101542699B/zh
Priority to US12/282,112 priority patent/US8441033B2/en
Publication of WO2008084765A1 publication Critical patent/WO2008084765A1/ja
Anticipated expiration legal-status Critical
Priority to US13/084,194 priority patent/US8518813B2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/025—Manufacture or treatment forming recessed gates, e.g. by using local oxidation
    • H10D64/027—Manufacture or treatment forming recessed gates, e.g. by using local oxidation by etching at gate locations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Recrystallisation Techniques (AREA)

Abstract

　半導体基板とは格子定数の異なる半導体層からチャネル部に対して効果的に応力を印加することが可能でこれによりキャリア移動度の向上を図り高機能化の達成が可能な半導体装置を提供する。半導体基板３上にゲート絶縁膜５を介して設けられたゲート電極７と、ゲート電極７の両脇において半導体基板３の表面を掘り下げた部分にエピタキシャル成長によって形成された半導体層（応力印加層）９とを備えた半導体装置１において、半導体層９は、半導体基板３とは格子定数の異なる層であり、ゲート絶縁膜５およびゲート電極７は、半導体層９間において半導体基板３の表面を掘り下げた部分を埋め込む状態で設けられている。半導体基板３の表面に対するゲート絶縁膜５の深さ位置ｄ２は、半導体層９の深さ位置ｄ１よりも浅いこととする。
PCT/JP2008/050007 2007-01-09 2008-01-04 半導体装置および半導体装置の製造方法 Ceased WO2008084765A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2008800001064A CN101542699B (zh) 2007-01-09 2008-01-04 半导体器件和制造半导体器件的方法
US12/282,112 US8441033B2 (en) 2007-01-09 2008-01-04 Semiconductor device and method of manufacturing semiconductor device
US13/084,194 US8518813B2 (en) 2007-01-09 2011-04-11 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007-000978 2007-01-09
JP2007000978 2007-01-09
JP2007-329564 2007-12-21
JP2007329564A JP5326274B2 (ja) 2007-01-09 2007-12-21 半導体装置および半導体装置の製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US12/282,112 A-371-Of-International US8441033B2 (en) 2007-01-09 2008-01-04 Semiconductor device and method of manufacturing semiconductor device
US13/084,194 Division US8518813B2 (en) 2007-01-09 2011-04-11 Semiconductor device and method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO2008084765A1 true WO2008084765A1 (ja) 2008-07-17

Family

ID=39608654

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/050007 Ceased WO2008084765A1 (ja) 2007-01-09 2008-01-04 半導体装置および半導体装置の製造方法

Country Status (1)

Country Link
WO (1) WO2008084765A1 (ja)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031753A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
JP2004266278A (ja) * 2003-02-28 2004-09-24 Samsung Electronics Co Ltd 上昇されたソース／ドレーン構造を有するｍｏｓトランジスタ及びこの製造方法
WO2004097943A1 (ja) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法
JP2006270051A (ja) * 2005-02-28 2006-10-05 Fujitsu Ltd 半導体装置およびその製造方法
JP2007103654A (ja) * 2005-10-04 2007-04-19 Toshiba Corp 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004031753A (ja) * 2002-06-27 2004-01-29 Renesas Technology Corp 半導体装置の製造方法
JP2004266278A (ja) * 2003-02-28 2004-09-24 Samsung Electronics Co Ltd 上昇されたソース／ドレーン構造を有するｍｏｓトランジスタ及びこの製造方法
WO2004097943A1 (ja) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
JP2006270051A (ja) * 2005-02-28 2006-10-05 Fujitsu Ltd 半導体装置およびその製造方法
JP2006261283A (ja) * 2005-03-16 2006-09-28 Sony Corp 半導体装置およびその製造方法
JP2007103654A (ja) * 2005-10-04 2007-04-19 Toshiba Corp 半導体装置およびその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
TATESHITA Y. ET AL.: "High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates", INTERNATIONAL ELECTRON DEVICES MEETING, 2006, IEDM'06, 11 December 2006 (2006-12-11) *
WANG J. ET AL.: "Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascence Gata Process", 2007 SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 12 June 2007 (2007-06-12), pages 46 - 47 *

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