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WO2008117431A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2008117431A1
WO2008117431A1 PCT/JP2007/056369 JP2007056369W WO2008117431A1 WO 2008117431 A1 WO2008117431 A1 WO 2008117431A1 JP 2007056369 W JP2007056369 W JP 2007056369W WO 2008117431 A1 WO2008117431 A1 WO 2008117431A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
manufacturing
field effect
effect transistor
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2007/056369
Other languages
English (en)
French (fr)
Inventor
Tamotsu Owada
Hirofumi Watatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Semiconductor Ltd filed Critical Fujitsu Ltd
Priority to JP2009506144A priority Critical patent/JP5310543B2/ja
Priority to PCT/JP2007/056369 priority patent/WO2008117431A1/ja
Publication of WO2008117431A1 publication Critical patent/WO2008117431A1/ja
Anticipated expiration legal-status Critical
Priority to US12/567,972 priority patent/US8604552B2/en
Priority to US13/598,010 priority patent/US20120322272A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H10P14/69433—
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10P14/6532—
    • H10P14/6538—
    • H10W20/075—
    • H10W20/095—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10P14/6336—
    • H10P14/6682—

Landscapes

  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

（課題）チャネル領域に引っ張りストレスを与える応力膜が分断することを抑制し、信頼性の高い半導体装置及びその製造方法を提供する。 （解決手段）本発明は、高いキャリア移動特性を有し、電界効果トランジスタ上に応力膜を有する半導体装置及びその製造方法に関するものであり、上記課題を解決するために、シリコン基板にｎチャネル型電界効果トランジスタを形成する工程と、前記電界効果トランジスタを覆う絶縁膜を成膜する第１の工程と、前記絶縁膜を収縮させる第２の工程とを有し、前記第１の工程と前記第２の工程とを複数回繰り返す。  
PCT/JP2007/056369 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法 Ceased WO2008117431A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009506144A JP5310543B2 (ja) 2007-03-27 2007-03-27 半導体装置の製造方法
PCT/JP2007/056369 WO2008117431A1 (ja) 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法
US12/567,972 US8604552B2 (en) 2007-03-27 2009-09-28 Semiconductor device and method for fabricating semiconductor device
US13/598,010 US20120322272A1 (en) 2007-03-27 2012-08-29 Semiconductor device and method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056369 WO2008117431A1 (ja) 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/567,972 Continuation US8604552B2 (en) 2007-03-27 2009-09-28 Semiconductor device and method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
WO2008117431A1 true WO2008117431A1 (ja) 2008-10-02

Family

ID=39788174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/056369 Ceased WO2008117431A1 (ja) 2007-03-27 2007-03-27 半導体装置および半導体装置の製造方法

Country Status (3)

Country Link
US (2) US8604552B2 (ja)
JP (1) JP5310543B2 (ja)
WO (1) WO2008117431A1 (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
JP2012164869A (ja) * 2011-02-08 2012-08-30 Renesas Electronics Corp 半導体装置およびその製造方法
JP2013511850A (ja) * 2009-11-19 2013-04-04 クアルコム，インコーポレイテッド 歪み材料を有する半導体デバイス
CN103904055A (zh) * 2014-03-20 2014-07-02 上海华力微电子有限公司 一种接触孔刻蚀阻挡层结构及其制备方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110012229A1 (en) * 2009-07-14 2011-01-20 United Microelectronics Corp. Semiconductor device with capacitor and method of fabricating the same
CN102386087B (zh) * 2010-08-27 2016-03-16 中芯国际集成电路制造(上海)有限公司 一种改进的金属前介质层的构造方法
CN103346080A (zh) * 2013-07-09 2013-10-09 上海华力微电子有限公司 减少金属硅化物掩模层缺陷的方法
FR3076077B1 (fr) * 2017-12-22 2020-02-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation de transistors a canaux contraints

Citations (1)

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Publication number Priority date Publication date Assignee Title
JP2006024784A (ja) * 2004-07-08 2006-01-26 Fujitsu Ltd 半導体装置およびｃｍｏｓ集積回路装置

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US6287951B1 (en) * 1998-12-07 2001-09-11 Motorola Inc. Process for forming a combination hardmask and antireflective layer
US6362508B1 (en) * 2000-04-03 2002-03-26 Tower Semiconductor Ltd. Triple layer pre-metal dielectric structure for CMOS memory devices
JP2005057301A (ja) 2000-12-08 2005-03-03 Renesas Technology Corp 半導体装置及びその製造方法
JP2003086708A (ja) 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
JP3532188B1 (ja) 2002-10-21 2004-05-31 沖電気工業株式会社 半導体装置及びその製造方法
US7053400B2 (en) * 2004-05-05 2006-05-30 Advanced Micro Devices, Inc. Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
US20060105106A1 (en) * 2004-11-16 2006-05-18 Applied Materials, Inc. Tensile and compressive stressed materials for semiconductors
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US7300891B2 (en) * 2005-03-29 2007-11-27 Tokyo Electron, Ltd. Method and system for increasing tensile stress in a thin film using multi-frequency electromagnetic radiation
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US20070249069A1 (en) * 2006-04-25 2007-10-25 David Alvarez Semiconductor devices and methods of manufacturing thereof
US20080138983A1 (en) * 2006-12-06 2008-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming tensile stress films for NFET performance enhancement
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306132A (ja) * 2007-06-11 2008-12-18 Renesas Technology Corp 半導体装置の製造方法
JP2013511850A (ja) * 2009-11-19 2013-04-04 クアルコム，インコーポレイテッド 歪み材料を有する半導体デバイス
KR101350846B1 (ko) * 2009-11-19 2014-01-13 퀄컴 인코포레이티드 스트레인 물질을 가지는 반도체 디바이스
JP2012164869A (ja) * 2011-02-08 2012-08-30 Renesas Electronics Corp 半導体装置およびその製造方法
CN103904055A (zh) * 2014-03-20 2014-07-02 上海华力微电子有限公司 一种接触孔刻蚀阻挡层结构及其制备方法

Also Published As

Publication number Publication date
JPWO2008117431A1 (ja) 2010-07-08
US20100012991A1 (en) 2010-01-21
US20120322272A1 (en) 2012-12-20
US8604552B2 (en) 2013-12-10
JP5310543B2 (ja) 2013-10-09

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