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WO2006014574A2 - Dispositifs varactor metal-isolant - Google Patents

Dispositifs varactor metal-isolant Download PDF

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Publication number
WO2006014574A2
WO2006014574A2 PCT/US2005/024207 US2005024207W WO2006014574A2 WO 2006014574 A2 WO2006014574 A2 WO 2006014574A2 US 2005024207 W US2005024207 W US 2005024207W WO 2006014574 A2 WO2006014574 A2 WO 2006014574A2
Authority
WO
WIPO (PCT)
Prior art keywords
insulator
layer
conducting
given voltage
varactor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/024207
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English (en)
Other versions
WO2006014574A8 (fr
WO2006014574A3 (fr
WO2006014574A9 (fr
Inventor
Michael J. Estes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Colorado Boulder
Original Assignee
University of Colorado Boulder
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/113,587 external-priority patent/US7173275B2/en
Application filed by University of Colorado Boulder filed Critical University of Colorado Boulder
Priority to EP05769417A priority Critical patent/EP1779440A4/fr
Priority to JP2007520523A priority patent/JP2008506265A/ja
Publication of WO2006014574A2 publication Critical patent/WO2006014574A2/fr
Publication of WO2006014574A9 publication Critical patent/WO2006014574A9/fr
Anticipated expiration legal-status Critical
Publication of WO2006014574A3 publication Critical patent/WO2006014574A3/fr
Publication of WO2006014574A8 publication Critical patent/WO2006014574A8/fr
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/70—Tunnel-effect diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/64—Variable-capacitance diodes, e.g. varactors 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
    • H10D84/215—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors of only varactors

Definitions

  • FIGURES Ia and Ib are energy band diagrams for a MIIM device of the present invention, showing an unbiased and a biased state, respectively.
  • FIGURE 2a is an energy band diagram for the MUM device of Figures Ia and Ib, shown here to illustrate further details with respect to the biased state.
  • FIGURE 2b is a plot of charge against lateral distance for the biased device of Figure 2a.
  • FIGURE 2c is a plot of electric field strength against lateral distance for the biased device of Figure 2a.
  • FIGURE 3 includes a plot of capacitance against bias voltage for an exemplary MUM varactor device that is produced in accordance with the present invention, including an inset plot of an energy band diagram of this exemplary MUM.
  • FIGURES 4a and 4b are energy band diagrams for a MUM device of the present invention, showing an unbiased and a biased state, respectively, wherein the device is configured for use without ' a need for a zero bias voltage.
  • FIGURES 5a and 5b are energy band diagrams for a first alternative MlM device of the present invention, showing an unbiased and a biased state, respectively.
  • FIGURES 6a and 6b are energy band diagrams for a second alternative M]HM device of the present invention, showing an unbiased and a biased state, respectively.
  • FIGURE 7 is a schematic diagram of a small signal model derived from the MIIM device structure.
  • the varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers.
  • an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool therein which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage.
  • the insulator arrangement includes at least two distinct layers. [0017] In another feature, the insulator arrangement includes a single layer of material. [0018] In a related feature, at least one of the layers of the insulator is an amorphous material.
  • a MUM device can be configured to set a threshold bias voltage, at least approximately, to zero volts so as to provide for use of the varactor without a need for a bias voltage.
  • varactor a variable capacitor in which the capacitance of the 2-terminal device varies as a function of voltage across the device.
  • the disclosed varactor has several advantages over competing semiconductor- based varactors, including:
  • the basic varactor of this disclosure has a structure of metal-insulator- insulator-metal (MUM) of the type originally disclosed by Eliasson and Moddel in U.S. Patent No. 6,534,784 (hereinafter, the 784 patent) which is incorporated herein by reference in its entirety and commonly owned with the present application.
  • MUM metal-insulator- insulator-metal
  • a first metal layer M 1 and a second metal layer M 2 are positioned in a spaced-apart relationship.
  • An insulator arrangement 20 is disposed between first and second metal layers Mi and M 2 .
  • insulator arrangement 20 includes a first insulator layer Ij and a second insulator layer I 2 .
  • first insulator I 1 is configured to have a very high barrier height (»1 eV) and second insulator I 2 to have a low barrier height (nominally ⁇ 0.3 eV),
  • second metal (M 2 ) may readily tunnel across I 2 but not across I 1 .
  • potential well 30 is formed in I 2 proximate to a boundary 32 between I 1 and I 2 . It is further recognized that this charge pooling causes a change in capacitance that is dependent on an applied voltage, forming a varactor device.
  • FIGS. 2a-c to understand the operation of the MIIM varactor and to estimate the capacitance as a function of applied voltage, one may start by solving the electrostatics problem of charge and field distribution that is illustrated.
  • Figures 2a-c are plots against distance x, of potential E, charge p, and electric field intensity ⁇ , respectively.
  • a MUM structure including aforedescribed Mi, Ii, I 2 , and M 2 , having a first (higher) Ii barrier of thickness d,, electron affinity ⁇ h and dielectric constant S 1 , and a second (lower) I 2 barrier of thickness d 2 , electron affinity ⁇ 2 , and dielectric constant ⁇ 2 .
  • These barriers are bounded by metal Mi on the left side with work function ⁇ Mh and metal M 2 on the right side with work function ⁇ m-
  • the barrier heights shown in Figure 2, which are all taken as positive numbers, are given by
  • flE is the Fermi distribution of electrons. Note that we have used the energy convention shown in Figure 2a, where the Fermi level of the first metal is taken as zero, and potential energy E increases positively as we move down the vertical axis. Knowing the charge density in barrier I 2 as a function of potential, we can use the Poisson equation, with appropriate boundary conditions, to solve for a potential distribution, V ⁇ x), a charge density in the barrier I 2 , Q c , and the charge densities at the two metal interfaces, Q 1 and Q 2 . It is noted that Figure 2b plots charge density as a function of x, in order to illustrate these various charge density values. From the bias voltage dependence of the anode Mi charge, Qj(Vb), we may then calculate capacitance as dQildV b .
  • V V + hV' +—V"
  • h is the finite element width (dx) and the ⁇ is determined by the slope of V(x). If V ⁇ x)>Q, the sign is negative, otherwise the sign is positive.
  • Figure 3 includes a coordinate system, generally indicated by the reference number 40, showing capacitance plotted against voltage for a given MUM device.
  • Plots are provided for four different temperatures: 150° K, 200° K, 250° K and 300° K, indicated by the reference numbers 45, 46, 47 and 48, respectively.
  • Va x is approximately 0.25 V. In some practical applications, it may be advantageous to have Va 1 -O so that the maximum change in capacitance occurs at zero bias and no bias supply is required, as will be described in further detail immediately hereinafter.
  • Figures 4a and 4b are energy band diagrams that are generally indicated by the reference numbers 50 and 60, respectively, for a highly advantageous "zero- bias" MUM device wherein V th is moved to zero volts such that no bias supply voltage is needed in order to operate the varactor.
  • Ih order to accomplish this, ⁇ 2 is set to equal zero by choosing ⁇ MT ⁇ X I - That is, the work function OfM 2 is equal to the electron affinity ⁇ 2 of I 2 .
  • First and second metal layers are indicated as M 1 and M 2 , respectively, while an insulator is indicated as I.
  • a negative barrier height is formed by selecting electron affinity ⁇ of insulator I and metal M 2 , having work function ⁇ such that ⁇ > ⁇ M2 (18)
  • a negative barrier height is produced at a boundary 64 between insulator I and metal M 2 .
  • the negative barrier between insulator I and metal M 2 forms a charge well 66 whose width is modulated by the applied voltage, as can be seen by comparing Figures 5a and 5b, resulting in a change in capacitance responsive to the applied voltage.
  • First and second metal layers are indicated as M 1 and M 2 , respectively, while an insulator layer arrangement is indicated as 74, including a first insulator layer I 1 . a second insulator layer I 2 and a third insulator layer I 3 .
  • the device is configured to produce a charge well 76, in I 2 , proximate to a boundary 78 between I 1 and I 2 .
  • a varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers.
  • an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage.
  • the insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material.
  • a zero- bias voltage version of the varactor is also described.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un varactor qui comprend une première et une seconde couche conductrice, espacées l'une de l'autre de façon à permettre l'application d'une tension donnée aux bornes desdites couches conductrices; et un dispositif isolant comprenant au moins une couche isolante, placée entre les première seconde couches conductrices et qui coopère avec celles-ci de manière à produire un réserve de charge, laquelle change en fonction de la tension donnée, de sorte que la capacité du dispositif entre les première et seconde couches conductrices change selon la tension donnée. Le dispositif isolant peut comprendre une couche, deux couches distinctes ou plus de deux couches distinctes. Une ou plusieurs des couches peu(ven)t être faite(s) d'une matière amorphe. Une version du varactor à tension de polarisation nulle est également décrite.
PCT/US2005/024207 2004-07-08 2005-07-07 Dispositifs varactor metal-isolant Ceased WO2006014574A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05769417A EP1779440A4 (fr) 2004-07-08 2005-07-07 Dispositifs varactor metal-isolant
JP2007520523A JP2008506265A (ja) 2004-07-08 2005-07-08 金属−絶縁体バラクタデバイス

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US58649304P 2004-07-08 2004-07-08
US60/586,493 2004-07-08
US11/113,587 US7173275B2 (en) 2001-05-21 2005-04-25 Thin-film transistors based on tunneling structures and applications
US11/113,587 2005-04-25

Publications (4)

Publication Number Publication Date
WO2006014574A2 true WO2006014574A2 (fr) 2006-02-09
WO2006014574A9 WO2006014574A9 (fr) 2006-03-30
WO2006014574A3 WO2006014574A3 (fr) 2007-01-25
WO2006014574A8 WO2006014574A8 (fr) 2007-04-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/024207 Ceased WO2006014574A2 (fr) 2004-07-08 2005-07-07 Dispositifs varactor metal-isolant

Country Status (4)

Country Link
EP (1) EP1779440A4 (fr)
JP (1) JP2008506265A (fr)
KR (1) KR20070083457A (fr)
WO (1) WO2006014574A2 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3613011A (en) * 1969-01-08 1971-10-12 Gen Motors Corp Varactor tone control apparatus
US4510516A (en) * 1982-02-01 1985-04-09 Bartelink Dirk J Three-electrode MOS electron device
US5019530A (en) * 1990-04-20 1991-05-28 International Business Machines Corporation Method of making metal-insulator-metal junction structures with adjustable barrier heights
US5895934A (en) * 1997-08-13 1999-04-20 The United States Of America As Represented By The Secretary Of The Army Negative differential resistance device based on tunneling through microclusters, and method therefor
US6534784B2 (en) * 2001-05-21 2003-03-18 The Regents Of The University Of Colorado Metal-oxide electron tunneling device for solar energy conversion
US6944052B2 (en) * 2002-11-26 2005-09-13 Freescale Semiconductor, Inc. Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP1779440A4 *

Also Published As

Publication number Publication date
EP1779440A4 (fr) 2009-04-15
KR20070083457A (ko) 2007-08-24
WO2006014574A8 (fr) 2007-04-05
EP1779440A2 (fr) 2007-05-02
JP2008506265A (ja) 2008-02-28
WO2006014574A3 (fr) 2007-01-25
WO2006014574A9 (fr) 2006-03-30

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