WO2006014574A2 - Metal-insulator varactor devices - Google Patents

Abstract

A varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage. The insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material. A zero-bias voltage version of the varactor is also described.

Description

METAL-INSULATOR VARACTOR DEVICES

Related Applications

[0001] The present application is a Continuation-in-Part of U.S. Patent Application Serial no. 11/113,587 entitled, THIN-FILM TRANSISTORS BASED ON TUNNELING STRUCTURES AND APPLICATIONS, filed on April 25, 2005, and also claims priority from U.S. Provisional Application Serial no. 60/586,493 entitled METAL-INSULATOR VARACTOR DEVICES, filed on July 8, 2004. The 11/113,587 Application is itself a Continuation-in-Part of U.S. Patent Application Serial no. 10/877,874, entitled HIGH SPEED ELECTRON TUNNELING DEVICES, filed on June 26, 2004, and which also claims priority from U.S. Provisional Application Serial No. 60/565,700, entitled

PRACTICAL THIN-FILM TRANSISTORS BASED ON METAL-INSULATOR TUNNELING STRUCTURES AND THEIR APPLICATIONS. The 10/887,874 Application is itself a Continuation of U.S. Patent Application Serial no. 10/347,534, entitled HIGH SPEED ELECTRON TUNNELING DEVICES, filed on January 20, 2003, which is itself a Continuation of U.S. Patent Application Serial no. 09/860,972, entitled HIGH SPEED ELECTRON TUNNELING DEVICE AND APPLICATIONS, filed on May 21 , 2001 , all of which are incorporated herein by reference in their entirety.

Background

[0002] An electronic component that varies in capacitance, responsive to a bias voltage, is used in many modern-day electronic designs and is likely to be of continuing utility for the foreseeable future. Such devices are often referred to as "varactors". High speed varactors (i.e. - varactors whose capacitance can change very quickly with high frequency changes in voltage) find use as low-loss frequency multipliers as well as tuning elements in high-frequency circuits.

[0003] The state-of-the-art in the design of a varactor typically employs semiconductor materials to produce a p-n junction that is biased so as to vary the capacitance of the junction. While the use of a semiconductor-based design has been effective for its intended purpose, the present application discloses a new design which is intended to provide significant advantages over the use of a typical prior art p-n junction design, for example, with respect to device speed, as well as providing still further advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present invention may be understood by reference to the following detailed description taken in conjunction with the drawings briefly described below. It is noted that, for purposes of illustrative clarity, certain elements in the drawings may not be drawn to scale. Furthermore, descriptive nomenclature such as, for example, vertical, horizontal and the like applied to the various figures is used for illustrative purposes only and is in no way intended as limiting useful orientations of the structure or device described.

[0005] FIGURES Ia and Ib are energy band diagrams for a MIIM device of the present invention, showing an unbiased and a biased state, respectively. [0006] FIGURE 2a is an energy band diagram for the MUM device of Figures Ia and Ib, shown here to illustrate further details with respect to the biased state.

[0007] FIGURE 2b is a plot of charge against lateral distance for the biased device of Figure 2a.

[0008] FIGURE 2c is a plot of electric field strength against lateral distance for the biased device of Figure 2a. [0009] FIGURE 3 includes a plot of capacitance against bias voltage for an exemplary MUM varactor device that is produced in accordance with the present invention, including an inset plot of an energy band diagram of this exemplary MUM.

[0010] FIGURES 4a and 4b are energy band diagrams for a MUM device of the present invention, showing an unbiased and a biased state, respectively, wherein the device is configured for use without^' a need for a zero bias voltage.

[0011] FIGURES 5a and 5b are energy band diagrams for a first alternative MlM device of the present invention, showing an unbiased and a biased state, respectively.

[0012] FIGURES 6a and 6b are energy band diagrams for a second alternative M]HM device of the present invention, showing an unbiased and a biased state, respectively. [0013] FIGURE 7 is a schematic diagram of a small signal model derived from the MIIM device structure.

Summary

[0014] As will be described in more detail hereinafter, there is disclosed herein, a highly advantageous varactor and associated method. [0015] In one aspect of the invention, the varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool therein which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage.

[0016] In one feature, the insulator arrangement includes at least two distinct layers. [0017] In another feature, the insulator arrangement includes a single layer of material. [0018] In a related feature, at least one of the layers of the insulator is an amorphous material.

[0019] In another aspect of the present invention, a MUM device can be configured to set a threshold bias voltage, at least approximately, to zero volts so as to provide for use of the varactor without a need for a bias voltage.

Detailed Description [0020] The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art and the generic principles herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein including alternatives, modifications and equivalents, as defined within the scope of the appended claims. It is noted that the drawings are not to scale and are diagrammatic in nature in a way that is thought to best illustrate features of interest. Further, like reference numbers are applied to like components, whenever practical, throughout the present disclosure.

[0021] Disclosed is a highly advantageous metal-insulator device structure forming a variable capacitor (hereinafter varactor) in which the capacitance of the 2-terminal device varies as a function of voltage across the device. The disclosed varactor has several advantages over competing semiconductor- based varactors, including:

1. Large change in capacitance;

2. High capacitance per unit area; 3. High differential capacitance; and

4. Compatibility with a wide variety of substrate materials.

[0022] In one implementation, the basic varactor of this disclosure has a structure of metal-insulator- insulator-metal (MUM) of the type originally disclosed by Eliasson and Moddel in U.S. Patent No. 6,534,784 (hereinafter, the 784 patent) which is incorporated herein by reference in its entirety and commonly owned with the present application. In this regard, it should be appreciated that the device of the 784 patent was specifically directed to solar energy conversion.

[0023] Turning now to Figures Ia and Ib, energy band diagrams for an MUM varactor are illustrated and generally indicated by the reference numerals 10 and 12, respectively. Figure Ia shows the device at zero bias, indicated as V=O, while Figure Ib shows the device under positive applied bias voltage

(forward bias), indicated as V=V⁺. In these figures, a first metal layer M₁ and a second metal layer M₂ are positioned in a spaced-apart relationship. An insulator arrangement 20 is disposed between first and second metal layers Mi and M₂. In the present example, insulator arrangement 20 includes a first insulator layer Ij and a second insulator layer I₂. What distinguishes the varactor devices of this disclosure from the MUM tunneling devices of the 784 patent resides in causing the device to function as a capacitor, as opposed to a nonlinear resistor or diode. In the MUM diodes of the 784 patent, insulator materials and thicknesses are chosen to allow electrons to tunnel across the device from one metal to the other. It is noted that this unexpected and surprising behavior was discovered in conjunction with device characterization and design using complex modeling techniques that were directed toward development of nonlinear devices. With this remarkable discovery in hand, modifications were made, which are considered as neither trivial or obvious, in causing the MEM structure to function in a completely different way and as a completely different kind of device. In particular, first insulator I₁ is configured to have a very high barrier height (»1 eV) and second insulator I₂ to have a low barrier height (nominally <0.3 eV), Thus, it is recognized that electrons from the second metal (M₂) may readily tunnel across I₂ but not across I₁. Under forward bias, therefore, free electron charge pools up in a generally triangular potential well 30, between the two insulators. More specifically, potential well 30 is formed in I₂ proximate to a boundary 32 between I₁ and I₂. It is further recognized that this charge pooling causes a change in capacitance that is dependent on an applied voltage, forming a varactor device.

[0024] In the following sections, a theoretical calculation of capacitance, for the MUM varactor of Figures Ia and Ib, is described as a function of (i) applied voltage, (ii) C(V), (in) alternative varactor configurations and (iv) factors affecting varactor frequency response and performance. Theory - Calculating C(V)

[0025] It is noted that the following analysis is presented with the intention of enhancing the readers' understanding, however, there is no intention to be bound by the theoretical concepts that are presented.

[0026] Turning to Figures 2a-c, to understand the operation of the MIIM varactor and to estimate the capacitance as a function of applied voltage, one may start by solving the electrostatics problem of charge and field distribution that is illustrated. Figures 2a-c are plots against distance x, of potential E, charge p, and electric field intensity ε, respectively. We start with a MUM structure including aforedescribed Mi, Ii, I₂, and M₂, having a first (higher) Ii barrier of thickness d,, electron affinity χ_h and dielectric constant S₁, and a second (lower) I₂ barrier of thickness d₂, electron affinity χ₂, and dielectric constant ε₂. These barriers are bounded by metal Mi on the left side with work function Φ_Mh and metal M₂ on the right side with work function Φm- The barrier heights shown in Figure 2, which are all taken as positive numbers, are given by

[0027] Finally, we apply a voltage across Mi and M₂ of the MDM having magnitude V_b. For this analysis we make several significant assumptions. First, we assume that the first (higher) barrier is high enough and/or wide enough that electron tunneling through it is negligible. Otherwise, we have to account for tunneling rates between first metal M₁ and the charge pool and between the charge pool and second metal M₂. In such a three level system, the electron density and quasi-Fermi energy of the charge pool will vary as the tunneling rates vary, a complication we will avoid for this initial analysis. Similarly, we assume that the free charge density in the first barrier is completely negligible. Second, we assume that the density of states in the second (lower) barrier material is not modified by quantum mechanical reflections. In other words, we neglect quantum confinement and the formation of a triangular quantum well. This assumption is likely accurate, since typical barrier materials would be amorphous oxides, where lack of long-range electron coherence would likely destroy any quantum confinement effects. Third, despite the amorphous nature of these barriers, we will neglect band tail states in the density of states and simply use a parabolic band model with an effective electron mass of unity, where the density of states is given by

"^M- f)^'" ⁽⁴⁾' where % is Planck's constant, m is the electron mass and E is the energy ahove the conduction band edge.

[0028] To calculate the free electron charge density at any point x in the second (lower) I₂ barrier, all we need to know is the potential, VQc), of the barrier. The charge density is then

J_(2mΫ ^∞r isV(x)+E) dE (5)

-qV(x) + 1

where flE) is the Fermi distribution of electrons. Note that we have used the energy convention shown in Figure 2a, where the Fermi level of the first metal is taken as zero, and potential energy E increases positively as we move down the vertical axis. Knowing the charge density in barrier I₂ as a function of potential, we can use the Poisson equation, with appropriate boundary conditions, to solve for a potential distribution, V{x), a charge density in the barrier I₂, Q_c, and the charge densities at the two metal interfaces, Q₁ and Q₂. It is noted that Figure 2b plots charge density as a function of x, in order to illustrate these various charge density values. From the bias voltage dependence of the anode Mi charge, Qj(Vb), we may then calculate capacitance as dQildV_b.

[0029] The Poisson relationship for charge and potential in barrier I₂ is thus given by

Multiplying both sides of Equation 6 above by 2 ^• dV/dx, we obtain

Integrating both sides, we obtain

V

= -2-2- Uv)dV + C (8)

S₂ -CO

[0030] Now, using boundary conditions at the I₂-M₂ interface, we may solve for the integration constant, C. We will call this point (i.e., the I₂-M₂ interface) x=0 and use the convention that x increases positively towards the left in the view of Figures 2a-c and towards Ii . We know the potential at x=0: it is simply -φ₂. If we assume that φ₂»kT so that the charge density at this point is negligible, then the electric field at x=0 is given by QJs₂. Our boundary conditions at x=0 are then

F(O) = -^₂ (9)

With these boundary conditions, the integration constant becomes

.

The expression for electric field is then

[0031] Since the Poisson equation is a highly nonlinear second order differential equation, we must use numerical methods to solve for V(x) and Q₀. Since we know dV/dx, the well-known Taylor Method works well (See, for example, Schaum's Outline of Theory and Problems of Differential Equations,

McGraw Hill (1973), which is incorporated herein by reference). We breakup the second barrier into finite elements along the x-axis. Starting at x=0, where we know V(x) and V'(x), we can then work towards x=d₂- We must assume a value for Q₂ to start the process. Later, we will use boundary conditions to find the correct value of Q₂ for the given bias voltage. Using Taylor's method, successive values of the potential are given by

V = V + hV' +—V"

where h is the finite element width (dx) and the ± is determined by the slope of V(x). If V\x)>Q, the sign is negative, otherwise the sign is positive.

[0032] Having solved for V(x) from our assumed value of Q₂, we can now solve for Q_c as

[0033] The boundary condition that enables us to solve for the correct value of Q₂ for a given bias voltage is given by

Qc = -Q₂ - Q_x

where φ_c=V_nmax, To solve for Qi(Y_b), we can equate the two previous equations for Q_c and solve for Q₂. [0034] Having now found Q₂(V_b), we can insert this back into Equationl5 for Q₁ to find Qi(V_b). Finally, the differential capacitance of the MOM is found by

CU(H = -^- (16) .

[0035] Figure 3 includes a coordinate system, generally indicated by the reference number 40, showing capacitance plotted against voltage for a given MUM device. An inset coordinate system 42 illustrates an energy band diagram 44 showing energy in electron volts versus distance in angstroms for the given MUM device in which: dj = 2 nm, d₂ = 8 nm, S₁ = 1Os₀, ε₂ = 60 ε₀, φi - 1.0 eV, φ₂ = 0.1 eV and φu = 0.9 eV. Plots are provided for four different temperatures: 150° K, 200° K, 250° K and 300° K, indicated by the reference numbers 45, 46, 47 and 48, respectively.

[0036] Ia view of Figure 3, a general trend is clear. At negative bias voltages, and at voltages below the threshold voltage, Va₁, the capacitance of the MEM approaches the geometric capacitance of two dielectrics in series, Ij and I₂. Above threshold, the capacitance approaches that of the first (higher) Ii barrier alone. As temperature decreases towards T=O K, the varactor switches between these two capacitance values more and more abruptly. The threshold voltage is the positive applied voltage at which the insulator well is at the Fermi energy level of M₂ and is given by

For the MEM structure of Figure 3, Va_x is approximately 0.25 V. In some practical applications, it may be advantageous to have Va₁-O so that the maximum change in capacitance occurs at zero bias and no bias supply is required, as will be described in further detail immediately hereinafter.

[0037] Attention is now directed to Figures 4a and 4b, which are energy band diagrams that are generally indicated by the reference numbers 50 and 60, respectively, for a highly advantageous "zero- bias" MUM device wherein V_th is moved to zero volts such that no bias supply voltage is needed in order to operate the varactor. Figure 4a illustrates the energy band configuration with a bias of V=O, while Figure 4b illustrates the energy band configuration for a bias OfV=V⁺. Ih order to accomplish this, φ₂ is set to equal zero by choosing Φ_MT^X_I- That is, the work function OfM₂ is equal to the electron affinity χ₂ of I₂. This change can be seen clearly by comparing Figure 4b with Figure 2a, since Figure 2a illustrates a nonzero value of φ₂. Further, φj is set to equal φ_i2, as is shown in Figure 4b. [0038] From the foregoing analysis and in consideration of all of the aforedescribed devices and examples, we see that to maximize the capacitance swing, we must choose the first barrier I₁ layer to be very thin and very high and the second barrier layer I₂ to be fairly wide and low. It may be advantageous to have ε₂ < S₁ , where possible, in order to distribute the electric field more strongly in favor of the charge storage region. Of course, practical limitations on materials and on device speed (discussed below) will bound the achievable performance.

Alternative Varactor Configurations

[0039] It should be appreciated that alternative metal-insulator varactor structures are contemplated and the present invention is not limited to the aforedescribed MUM structure. Such alternative structures will be described immediately hereinafter. [0040] Attention is now directed to Figures 5a and 5b which illustrate energy band diagrams of a metal-insulator-metal (MIM) varactor at a bias of V=O, generally indicated by the reference number 60 and at a bias OfV=V⁺, generally indicated by the reference number 62. First and second metal layers are indicated as M₁ and M₂, respectively, while an insulator is indicated as I. In producing the MIM varactor, a negative barrier height is formed by selecting electron affinity χ of insulator I and metal M₂, having work function Φ^ such that χ>Φ_M2 (18)

[0041] Accordingly, a negative barrier height is produced at a boundary 64 between insulator I and metal M₂. In this MIM structure, the negative barrier between insulator I and metal M₂ forms a charge well 66 whose width is modulated by the applied voltage, as can be seen by comparing Figures 5a and 5b, resulting in a change in capacitance responsive to the applied voltage.

[0042] Another alternative varactor structure is illustrated by Figures 6a and 6b, showing energy band diagrams of a metal-insulator-metal (MTTTM) varactor at a bias of V=O, generally indicated by the reference number 70 and at a bias OfV=V⁺, generally indicated by the reference number 72. First and second metal layers are indicated as M₁ and M₂, respectively, while an insulator layer arrangement is indicated as 74, including a first insulator layer I₁. a second insulator layer I₂ and a third insulator layer I₃. The device is configured to produce a charge well 76, in I₂, proximate to a boundary 78 between I₁ and I₂. It is noted that the device of Figures 6a and 6b is representative of a zero bias device. Since the MIIIM structure is quite similar in operation and spirit with respect to the MDM varactor, a detailed analysis will not be provided for purposes of brevity. Moreover, it is believed that one having ordinary skill in the art can readily produce the MH]M device in view of the foregoing descriptions. •

FrequencyResponseandPerformance

[0043] The speed or frequency response of the varactors described herein will be determined by how fast charge can be transferred in and out of the charge pool. Ih the discussion that follows, we will confine ourselves to the MDM varactor structure, although it is believed that alternative structures will be well understood with this discussion in hand. [0044] Referring again to Figures Ia and Ib, as increasing positive voltage is applied to the varactor, electrons fill charge pool 30 by tunneling from metal M₂. As the voltage is decreased again, excess charge drains from the pool by two processes: 1) tunneling back into metal M₂; and 2) band transport across the conduction band of insulator I₂ back into metal M₂. The speed at which these electrons may transport back and forth between the charge pool and metal M₂ determines the frequency response of the varactor.

[0045] If we ignore band transport across insulator I₂, which would be excessively slow for the case of an amorphous insulating material, we may calculate tunneling currents between the charge pool and metal M₂ using existing tunneling models, as described, for example, in the Doctoral Thesis of Blake J. Eliasson, entitled METAL-INSULATOR-METAL DIODES FOR SOLAR ENERGY CONVERSION, University of Colorado (2001), which is incorporated herein by reference. This calculation would yield the differential resistance, Rz(V), for tunneling electrons. Ih this notation, voltage V is the voltage between the charge pool and metal M₂. We should note that R₂(V) may not equal R₂(-V), since the tunneling probability may not be symmetric about F=O. Adding the capacitance, C₂, between the charge pool and metal M₂, we may construct the simple small-signal model of Figure 7 from which we may calculate frequency response as

where the various components are labeled consistent with Equation 19.

[0046] With reference to Figure 2a, in conjunction with Figure 7, to design a fast varactor, we must minimize R₂ and C₂. It is recognized that minimizing I₂ thickness (d₂) and barrier height (φ₂) reduces R₂ but increases C₂; however, since R₂ is exponentially dependent on barrier height and thickness while C₂ is only linearly dependent, we will experience a net gain in frequency response by reducing d₂ and φ₂. The penalty for reducing these values is reducing the capacitance swing about V_th (see Figure 3).

[0047] Realistic material considerations will degrade frequency response from the idealized RC- limited value above. In particular, for amorphous insulator materials, we should expect to encounter localized band tail states, deep trap states, and likely even surface states. Electrons in these states, which extend below the insulator's conduction band "edge", will cause a long-term charging of insulator I₂ near the interface with insulator 1, partially shielding the applied voltage and shifting the C(V) curve.

[0048] In broad summary, this writing has set forth the following. A varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage. The insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material. A zero- bias voltage version of the varactor is also described.

[0049] Although each of the aforedescribed physical embodiments have been illustrated with various components having particular respective orientations, it should be understood that the present invention may take on a variety of specific configurations with the various components being located in a wide variety of positions and mutual orientations. For example, as discussed in detail in above incorporated U.S. Patent no. 6,563, 185; other materials may be used in place of metal layers including, but not limited to semiconductors and semi-metals. Furthermore, the methods described herein may be modified in an unlimited number of ways, for example, by reordering the various sequences of which they are made up. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein but may be modified within the scope of the appended claims.

Claims

What is claimed is:

1. A varactor, comprising: first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers; and an insulator arrangement including at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool therein which changes responsive to changes in said given voltage such that a device capacitance value between the first and second conducting layers changes responsive to said given voltage.

2. The varactor of claim 1 wherein increasingly biasing the second conducting layer more positive than the first conducting layer, using said given voltage, produces a corresponding increase in said device capacitance value.

3. The varactor of claim 1 wherein said insulator arrangement includes at least a first insulator layer, adjacent to said first conducting layer, and a second insulator layer, adjacent to said second conducting layer and in a side-by-side relationship with said first insulator layer so as to define a boundary therebetween for producing said charge pool in the second one of said insulator layers proximate to said boundary with the first one of the insulator layers.

4. The varactor of claim 3 wherein said first insulator layer includes a first barrier height and said second insulator layer includes a second barrier height, and the first and second barrier heights are selected to produce tunneling of electrons from said second conducting layer through said second insulator layer, responsive to the given voltage, and to inhibit tunneling of electrons across said first insulator layer to generate said charge pool.

5. The varactor of claim 4 wherein said first barrier height is greater than said second barrier height.

6. The varactor of claim 5 wherein said first barrier height is much greater than 1 eV and said second barrier height is less than 0.3 eV.

7. The varactor of claim 3 wherein said first insulator layer includes a first capacitance value and said second insulator layer includes a second capacitance value such that an application of said given voltage which causes the first conducting layer to be increasingly positive with respect to the second conducting layer, below a given threshold value of said given voltage, causes said device capacitance value to approach a series combination of said first capacitance value and said second capacitance value and application of said given voltage which causes the first conducting layer to be increasingly negative with respect to the second conducting layer, above said given threshold value of said given voltage, causes said device capacitance value to approach said first capacitance value of the first insulator layer.

8. The varactor of claim 7 wherein said varactor is configured in a way which sets said threshold value of said given voltage, at least approximately, to zero volts.

9. The varactor of claim 1 wherein said insulator arrangement includes only one layer of an insulation material between said first and second conducting layers and said insulation material includes an insulator barrier height that cooperates with a second layer work function of said second conducting layer to produce a negative barrier height between the insulation material and the second conducting layer, responsive to said given voltage, such that the charge pool is formed in said insulator material proximate to a boundary with the second conducting layer.

10. The varactor of claim 9 wherein said charge pool includes a width that is modulated by changes in said given voltage.

11. The varactor of claim 1 wherein said insulator arrangement includes at least one layer of an amorphous material.

12. A method for producing a varactor, said method comprising: arranging first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers; and disposing an insulator arrangement, including at least one insulator layer, between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool therein which changes responsive to changes in said given voltage such that a device capacitance value between the first and second conducting layers changes responsive to said given voltage.

13. The method of claim 12 including configuring the insulator arrangement to cooperate with the first and second conducting layers such that increasingly biasing the second conducting layer more positive than the first conducting layer, using said given voltage, produces a corresponding increase in said device capacitance value.

14. The method of claim 12 including configuring said insulator arrangement to include at least a first insulator layer, adjacent to said first conducting layer, and a second insulator layer, adjacent to said second conducting layer and in a side-by-side relationship with said first insulator layer so as to define a boundary therebetween for producing said charge pool in the second one of said insulator layers proximate to said boundary with the first one of the insulator layers.

15. The method of claim 14 including selecting said first insulator layer to include a first barrier height and selecting said second insulator layer to include a second barrier height so as to produce tunneling of electrons from said second conducting layer through said second insulator layer, responsive to the given voltage, and to inhibit tunneling of electrons across said first insulator layer to generate said charge pool.

16. The method of claim 15 wherein said first barrier height is greater than said second barrier height.

17. The method of claim 16 wherein said first barrier height is selected as much greater than

1 eV and said second barrier height is selected as less than 0.3 eV.

18. The method of claim 14 wherein said first insulator layer includes a first capacitance value and said second insulator layer includes a second capacitance value such that an application of said given voltage which causes the first conducting layer to be increasingly positive with respect to the second conducting layer, below a given threshold value of said given voltage, causes said device capacitance value to approach a series combination of said first capacitance value and said second capacitance value and application of said given voltage which causes the first conducting layer to be increasingly negative with respect to the second conducting layer, above said given threshold value of said given voltage, causes said device capacitance value to approach said first capacitance value of the first insulator layer.

19. The method of claim 18 including configuring said varactor is to set said threshold value of said given voltage, at least approximately, to zero volts.

20. The method of claim 12 including configuring said insulator arrangement to include only one layer of an insulation material between said first and second conducting layers and said insulation material includes an insulator barrier height that cooperates with a second layer work function of said second conducting layer to produce a negative barrier height between the insulation material and the second conducting layer, responsive to said given voltage, such that the charge pool is formed in said insulator material proximate to a boundary with the second conducting layer.

21. The method of claim 20 wherein said charge pool includes a width that is modulated by changes in said given voltage.

22. The method of claim l2 including using at least one layer of an amorphous material as part of said insulator arrangement.