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WO2004019668A1 - Substrat perfore, son procede de fabrication et carte de contact a tranche pleine - Google Patents

Substrat perfore, son procede de fabrication et carte de contact a tranche pleine Download PDF

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Publication number
WO2004019668A1
WO2004019668A1 PCT/JP2003/010515 JP0310515W WO2004019668A1 WO 2004019668 A1 WO2004019668 A1 WO 2004019668A1 JP 0310515 W JP0310515 W JP 0310515W WO 2004019668 A1 WO2004019668 A1 WO 2004019668A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
substrate
conductive member
holes
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/010515
Other languages
English (en)
Japanese (ja)
Inventor
Osamu Sugihara
Yoichi Hachitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hoya Corp
Original Assignee
Hoya Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hoya Corp filed Critical Hoya Corp
Priority to JP2004530579A priority Critical patent/JP4071768B2/ja
Publication of WO2004019668A1 publication Critical patent/WO2004019668A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/16—Magnets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H10P74/00—
    • H10W70/095—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0292—Using vibration, e.g. during soldering or screen printing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H10W72/07251—
    • H10W72/20—

Definitions

  • the present invention relates to a hole-formed substrate in which a conductive member is buried in a hole formed with the substrate, a method of manufacturing the same, and the like, and more particularly, to a through-hole formed substrate having a through-hole penetrating the substrate,
  • the present invention relates to a method for manufacturing a double-sided wiring board and a wafer-filled (full-wafer) contact board using the double-sided wiring board.
  • this type of through-hole forming substrate is used for an inspection device for semiconductors and the like.
  • the semiconductor inspection process is performed in a plurality of stages.
  • wafers manufactured in the wafer manufacturing process pre-process
  • wafer manufacturing process pre-process
  • WLBI wafer level burn-in
  • the probe card test is generally a DCZAC test using one chip or a multi-contact probe card (up to 64 chips).
  • a probe force as shown in FIGS. 6A and 6B, an opening 62 is provided at the center of a multilayer wiring board 61 made of glass epoxy resin, and the periphery of the opening 62 is provided.
  • a probe (probe) 63 is provided toward the center of the opening 62 from the probe 62, and the probe 63 is brought into contact with the electrode terminal 42 on the one chip 41 of the wafer 40 to perform a test.
  • one of the membranes 71 made of polyimide or the like is used.
  • a membrane probe card of a type using a membrane 70 with bumps provided with bumps 72 (convex contacts) on the surface as a contact component has also been proposed.
  • the bumps 72 are electrically connected to the wiring 74 via the through holes 73 formed in the membrane 71, and the bumps 72 are formed on the conductive material 75, the pivot mechanism 76, the plate panel 7 It is pressed through 7 and contacted.
  • Burn-in inspection is a high-temperature accelerated test that is usually performed on a chip-by-chip basis, and often involves electrical testing. When performing burn-in inspection on a wafer, it is called wafer level burn-in (WL B I). When conducting burn-in inspection on wafers, it is necessary to commercialize wafer-contact contact boards (burn-in pads).
  • the final inspection includes the final electrical test, a simple on-off test, and a function test at the actual operating frequency of the device. Specifically, one or more bare chips and packaged products are pressed directly against the test head using the handler via the interposer and measured. In some cases, measurement is performed using a high-frequency probe card (up to 64 chips) in the wafer state. Disclosure of the invention
  • the probe card inspection process described above covers from 1 chip to 64 chip multi-measurement, but if this is possible, it is possible to greatly reduce the inspection time and the cost Becomes possible.
  • the inspection time can be greatly reduced, and the inspection cost can be significantly reduced.
  • a glass substrate is used as a core substrate of a multilayer wiring substrate in order to realize contact with all chips on a wafer.
  • the core substrate using this glass substrate is a single-sided wiring in which a wiring layer is formed only on one surface, so the number of wiring layers formed on the surface increases, and fine processing is required, resulting in high costs.
  • the length of the extraction electrode (wiring) becomes longer in terms of characteristics, and as a result, the resistance value increases and the impedance increases.
  • matching and equal length wiring become difficult.
  • the wiring layer is formed on one side of the glass substrate surface. Since it is formed only on the (wafer side), there is an inconvenience that elements such as resistors, capacitors, and fuses cannot be mounted on the wiring layer. This is because, since the device has a thickness, electrodes such as contact bumps provided on the glass substrate cannot contact the pad on the wafer due to the effect of the device having a large thickness. Therefore, it is considered that a probe detection probe using a glass substrate cannot be applied to high frequency applications or DC inspection applications.
  • the wafer-bound contact port for high-frequency applications for inspecting wiring boards such as LSI inspections and MCMs (multi-chip modules) is a through-hole (narrow pitch) that electrically connects the front and back surfaces. It is considered necessary to form a large number of thin, high-precision through holes on the entire surface of the substrate and a board with a multilayered structure.
  • a double-sided wiring board in which a large number of through holes are formed in a glass substrate has not yet been proposed. This is because when using a glass substrate, there are many problems to be solved in terms of accuracy, thermal expansion, and surface flatness, and mechanical strength and workability.
  • a method for manufacturing a double-sided wiring board from a glass substrate a method of drilling one hole in a glass substrate with a drill (for example, Japanese Utility Model Registration No. 30844542) can be considered. If thousands to tens of thousands of holes are formed by a drill, the cost of hundreds of thousands to several millions of yen is required, and it is impossible to realize the cost at all.
  • molten glass is poured into a molding frame with a plurality of linear conductors stretched, or a plurality of linear conductors are sandwiched between two sheet glasses to soften or fluidize the sheet glass.
  • a block body in which a plurality of linear conductors are buried, and cut the block body to obtain a through-hole-formed substrate Japanese Patent Laid-Open No. H10-19001.
  • the wires may actually bend and the position is not determined, and the position accuracy of the through-hole must be ensured. There is a problem that it is difficult.
  • An object of the present invention is to provide a method for manufacturing a hole-formed substrate and a through-hole formed substrate, which can easily and inexpensively realize a wafer-bound contact port for high frequency use.
  • the present invention has the following configuration.
  • the conductive member fixing step may include heating the hole-forming substrate at a temperature equal to or higher than a softening point temperature of the hole-forming substrate and equal to or lower than a temperature at which a substrate shape can be maintained.
  • the conductive member fixing step may include a step of heating the hole formation substrate at a temperature higher than a softening point temperature of the hole formation substrate and lower than a temperature at which a substrate shape can be maintained; Cooling the substrate after heating to thereby thermally shrink the substrate, whereby the conductive member is fixed to each hole.
  • the hole forming substrate is made of glass material, in the conductive member fixing step, so that the viscosity of the glass becomes 1 0 4 -1 0 11 poises, heat the pre-Symbol hole forming substrate
  • a method for manufacturing a hole-formed substrate comprising:
  • a substrate to be processed and a drill jig in which a plurality of drills are implanted are prepared, and a drill jig having the plurality of drills is provided on one surface of the substrate to be processed.
  • a method of manufacturing a hole-formed substrate comprising: forming a plurality of holes at once by vibrating the drill jig in a state where the tools are in contact with each other, and forming the hole-formed substrate.
  • (Structure 6) A method of manufacturing a hole-formed substrate according to structure 5, wherein ultrasonic waves are applied to the drill jig to form a plurality of holes at a time.
  • the step of burying the conductive member may include the step of embedding a linear conductor having a smaller diameter in each hole of the hole forming substrate on the surface of the hole forming substrate in which the hole is formed. After placing, each hole is given by applying vibration to the hole substrate.
  • the hole forming substrate is A conductive member fixing step of fixing the conductive member in each hole by heat treatment together with the embedded conductive member. Further, in the invention according to Configuration 2, the conductive member fixing step is performed at a temperature equal to or higher than a softening temperature of the hole-forming substrate, The method includes a step of fusing the conductive member by heating the substrate to a temperature at which the substrate shape can be maintained, and the conductive member can be sufficiently fixed by fusing.
  • the invention according to the third aspect further includes a step of heat-shrinking the substrate by cooling the hole-formed substrate after heating, and fixing the conductive member.
  • the conductive member can be firmly fixed by the heat shrinkage.
  • the present invention includes the step of fixing the conductive member by fusion and Z or heat shrinkage, so that even if the number of through holes is large, it can be fixed at once, An inexpensive (low-priced) through-hole forming substrate can be realized.
  • a conductive member is inserted or filled into each hole in the hole-formed substrate in which a large number of holes (not necessarily through-holes) are formed, Japanese Patent Application Laid-Open No.
  • the linear conductor wire, etc.
  • the conductive member include a linear conductor (for example, a wire), metal particles, and other conductive materials. In the case of wire, there is no risk of disconnection.
  • the viscosity of the glass at the conductive member fixing step heats the glass material so that 1 0 4 -1 0 11 poises.
  • 1 0 4 poises means working temperature temperature (molding temperature) around the glass, when it from the low viscosity, not keep the board shaped glass is excessively softened.
  • 1 0 11 poises means the viscosity near the yield point of the glass, when it than the viscosity is high, it is difficult to mold the glass.
  • the hole-forming substrate may include a plurality of holes formed by vibrating the drill jig in a state where the drill jig having the plurality of drills is in contact with one surface of the substrate to be processed. Are formed all at once, so a larger number of holes are required than when using a single-blade drill or a single-blade ultrasonic drill to drill holes sequentially. Since the holes are formed together, the cost of a hole-formed substrate having a large number of holes can be realized.
  • the drill jig has a narrow pitch (for example, 3 mm pitch or less) and is thin (for example, the through hole diameter is small). It was found that a substrate having a large number of holes (0.5 ⁇ or less) formed on the entire surface of the substrate could be obtained. In other words, it was found that even if many holes were finely formed at a narrow pitch, there was no breakage at all. This is thought to be due to the fact that the processing is performed with the drill bit inserted in all the holes, and the force acts uniformly. Drilling a new hole at a narrow pitch near an already formed hole may cause damage.
  • a narrow pitch for example, 3 mm pitch or less
  • the through hole diameter is small
  • the drill for applying the ultrasonic wave is formed by forming a large number of drill blades on one surface of the substrate, the number and the number of drills being stably self-supporting with respect to the substrate to be processed. If the drill is not stable and self-supporting, it is difficult to keep the drill horizontal with respect to the substrate to be processed, and it is not possible to realize vertical drilling with high hole diameter accuracy.
  • the drill to which the ultrasonic wave is applied has a large number of drill blades formed and arranged on one surface of the substrate so that the drill blades are not bent by their own weight. If the drill blade is bent by the weight of the drill, drilling with vertical and high hole diameter accuracy cannot be realized.
  • the number of drill bits is preferably 50 or more, more preferably 100 or more.
  • the number of drill blades is preferably 500 or more, and more preferably 100 or more, from the viewpoint of reducing the number of drilling times and the cost of manufacturing a drill.
  • the hole formed by the drill may be a through hole that penetrates the substrate to be processed or a hole that does not penetrate. If it does not penetrate, no linear conductor (eg, wire) or metal particles that enter or fill the hole will fall out of the bottom opening, so no measures to prevent falling off are necessary. If not penetrated, the non-penetrated part is removed by polishing to expose the linear conductor (for example, wire) and metal particles. When penetrating, the diameter of the bottom opening is smaller than the diameter of the linear conductor or metal particle, and the diameter of the linear conductor or metal particle is smaller than that of the bottom opening.
  • the diameter of the bottom opening is smaller than the diameter of the linear conductor or metal particle, and the diameter of the linear conductor or metal particle is smaller than that of the bottom opening.
  • the preferred surface roughness is an arithmetic average roughness Ra of 0.2 m or less, more preferably, a Ra of 0.1 m or less.
  • the arithmetic average roughness Ra described above is measured based on the measurement method defined in JIS B601-1994.
  • the surface of the substrate to be processed is ground or polished. Existing cracks and scratches can be minimized, and cracks (breakage) can be effectively reduced when a large number of holes are formed at once by applying ultrasonic waves. There is an advantage called.
  • an ultrasonic wave an ultrasonic wave having a frequency of several kHz to several hundred kHz can be used.
  • the diameter of the linear conductor is 90% or less of the hole diameter, further 85% or less, and further 80%. It is preferable to set the following.
  • the length of the linear conductor is preferably about the same as the depth of the hole, more preferably slightly longer than the depth of the hole, and more preferably about 1.1 times the depth of the hole.
  • the material of the linear conductor is preferably a material that allows the linear conductor to be automatically and smoothly inserted into all the holes.
  • the surface of the hole-forming substrate to which the conductive member is fixed is polished, and the conductive member is provided on both opposed surfaces.
  • a through-hole-formed substrate in which the front and back surfaces of the substrate are electrically connected by the conductive member is obtained.
  • a step of polishing one or both surfaces of the substrate is provided, whereby the metal surface of the conductive member can be exposed, and the oxide film can be formed. Problems can be avoided. Also, by removing the ends (portions protruding from the holes) of the linear conductor by polishing, complicated work such as adjusting the length of the linear conductor is not required. In addition, the polishing can impart or improve the flatness of the substrate. Furthermore, if the surface of the substrate and the end surface of the conductive member are made flush with each other by polishing, the level of the flush is higher than in the case of flushing with other methods. This is advantageous in terms of connectivity.
  • the polishing amount on one side is preferably 1 mm or less, more preferably 0.5 mm or less from the viewpoint of manufacturing cost.
  • the substrate surface after polishing has a maximum height R max of 2 or less, preferably 0.2 m or less.
  • R max of 2 or less, preferably 0.2 m or less.
  • an inexpensive wiring board can be realized by using the inexpensive through-hole formation substrate according to the ninth aspect and forming a wiring layer on the conductive member exposed on at least one surface.
  • the wiring layer can be a single layer or a multilayer. Further, the wiring layer can be formed on any one surface or both surfaces. Both wiring layers If it is formed on one side, it will be a double-sided wiring board.
  • the wiring layer includes wiring and electrodes.
  • a photolithography method, a built-up method (in the case of a multilayer), a printing method, or other known wiring or multilayer wiring technology is used.
  • the wiring board described in the configuration 10 is particularly suitable as a multilayer wiring board for a wafer-bound contact board when the number of through holes is large (for example, 200 or more).
  • the through-hole-forming substrate which is the base material of the double-sided wiring substrate, needs to have low thermal expansion and high surface flatness. This is for contacting the whole surface with the wafer and conducting and inspecting. It is preferable that the through-hole-forming substrate, which is the base material of the double-sided wiring substrate, has a coefficient of thermal expansion of 15 ppm or less. It is preferable that the surface flatness over the entire through-hole forming substrate, which is the base material of the double-sided wiring substrate, is 40 m or less.
  • the wafer contact board of the present invention it is necessary to use, as a base material of the double-sided wiring board, a through-hole forming substrate in which a large number of narrow through holes with a narrow pitch are formed with high precision over the entire surface. This is in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for probe inspection and specific burn-in inspection).
  • a large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate in order to correspond to an electrode to be inspected such as a semiconductor element.
  • An object of the present invention is to make it possible to manufacture a wafer-contacted contact board in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for a burn-in inspection specific to probe inspection) by contacting the entire surface.
  • a large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate.
  • the conductive pad electrode on the back surface is basically formed near the upper part of the chip on the wafer and has a structure in which conduction to the outside is connected almost vertically or by the shortest path. That is, the back pad is preferably formed at the shortest position with respect to the electrode on each chip.
  • the through-hole-formed substrate may have a standardized conductive through-hole on the entire surface of the substrate so that the type of the device under test can be changed. Is preferably formed at the position. By doing so, it can be manufactured at a low cost.
  • through holes can be formed radially, concentrically, or in an array over the entire surface of the substrate.
  • the substrate size of the wafer-contacting contact port is at least as large as the wafer size.
  • the thickness of the substrate is preferably about 2 to 7 mm in order to obtain mechanical durability and accurately form a through-hole.
  • the number of through holes is determined in relation to the number of chip elements such as resistors and capacitors mounted on the substrate, and is preferably the number of chip elements X 2 (for example, 100 or more). It is preferable that the pitch of the through-holes is 3 mm or less as long as the mechanical durability between the through-holes can be obtained, and the diameter of the through-hole is 0.1 to 0.5 ⁇ .
  • the wafer package contact port includes a wafer package burn-in inspection board, a wafer batch probe inspection board, and a wafer package final inspection port. '
  • a wafer batch contact port manufactured using such a through-hole formed substrate having a large number of through-holes formed on the entire surface of the substrate has not been obtained.
  • it is characterized in that a through-hole forming substrate having a large number of through-holes formed on the entire surface of the substrate is used.
  • the substrate in a substrate having a configuration in which a plurality of conductive members are embedded in a plurality of holes, the substrate is formed of a glass material, and a surface in which the conductive member is embedded has a maximum height.
  • a substrate polished so as to have a surface roughness of 2 ⁇ m or less at R max disconnection of a wiring layer formed on the surface of the substrate can be prevented.
  • the thickness of the wiring layer is equal to or greater than the thickness having a function as the wiring layer and is as small as 5 m or less, the substrate of Configuration 12 is particularly effective.
  • FIG. 1 (1) to 1 (7) are schematic views showing a method of manufacturing a through-hole formed substrate according to an embodiment of the present invention in the order of steps.
  • FIG. 4 is a schematic view showing a manufacturing method of the present invention in the order of steps.
  • FIG. 3 is a graph showing a viscosity curve of the low expansion glass used in the embodiment of the present invention.
  • FIG. 4 is a schematic view illustrating a wafer contact port including a through hole forming substrate according to the present invention.
  • FIG. 5 is a schematic view for explaining another wafer contact contact including the through hole forming substrate according to the present invention.
  • 6 (a) and 6 (b) are a plan view and a cross-sectional view illustrating an example of a probe card.
  • FIG. 7 is a partial cross-sectional view for explaining another probe card. BEST MODE FOR CARRYING OUT THE INVENTION
  • a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared.
  • the surface roughness of the low-expansion glass substrate 1 was Ra, which was 0.2 ⁇ m or less.
  • the surface roughness was measured using a stylus type surface roughness meter (trade name: Tencor ⁇ 2: Tencor Measured by Instruments).
  • the viscosity curve (temperature vs viscosity (log)) of the low expansion glass substrate # 45 has the characteristics shown in FIG. This viscous force one blanking, the temperature range in which the viscosity of the glass becomes 1 0 4 -1 0 11 poises is found to be 710 ° C ⁇ 1 17 5 ° C.
  • 3 x 30 900 holes drilled in a 3 x 30 screw holes with a pitch of 3 mm and a diameter of 0.5 mm. (8 mm in length) is inserted to form a drill jig with drill 3.
  • the drill 3 forming the drill jig 3 is formed of stainless steel, iron, tungsten, or the like.
  • a number of tungsten wires 6 are placed on the glass substrate 1 and subjected to the same ultrasonic vibration as in Fig. 1 (2).
  • the wire 6 is automatically inserted into the hole at once.
  • the wire 6 can be automatically and smoothly inserted into all holes, and it can be recovered and reused, so that it is also environmentally friendly.
  • the glass is softened, and the wire 16 is introduced into the softened glass (at the bottom of the hole) by the weight of the force plate 7, and further melts with the glass hole into which the wire 16 is inserted.
  • the wire 6 is attached and fixed.
  • step (6) Cooling glass substrate
  • the diameter of the wire 16 is smaller than the diameter of the through hole.
  • the through-hole shrinks and the wire 6 is firmly fixed. Then wire The attached glass substrate is cooled to room temperature (Fig. 1 (6)).
  • Step (7) Double-side polishing (a step of exposing both ends of the wire to the surface of the glass substrate) Both surfaces of the glass substrate with wires are polished flat, and the wires 6 are completely exposed to the front and back surfaces of the glass substrate.
  • the exposed surface of the wire 16 and the front and back surfaces of the glass substrate 1 need to be polished so that they substantially coincide with each other.
  • the surface roughness at this time was less than 0.2 m at the maximum height Rmax.
  • the thickness of the through-hole formed substrate 10 was about 4 mm.
  • a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared.
  • the surface roughness of the surface of the low expansion glass substrate 1 was Ra, which was 0.2 ⁇ m or less.
  • the surface roughness was measured by a stylus type surface roughness meter (Tencor P2). )
  • metal fine particles 8 were used instead of the wires.
  • the fine metal particles 8 are vibrated, the fine metal particles 8 are automatically and collectively inserted into the holes (FIG. 2 (4)).
  • metal fine particles 8 metal fine particles of solder, tungsten, copper, nickel, gold, silver, or the like, or fine particles of an alloy thereof, or metal particles of nickel or the like whose surface is plated with gold can be used.
  • the metal fine particles 8 it is desirable that the metal fine particles 8 have a particle diameter of 1/10 or less of the hole diameter.
  • the packing density of the metal fine particles in the hole can be increased.
  • metal fine particles 8 instead of the metal fine particles 8, a method in which metal particles or the like are dispersed in a dispersant (adhesive, resin, or the like) may be used to fill the holes. In this case, when the drilled hole is completely penetrated, the metal particles dispersed in the dispersant can be completely filled in the hole.
  • a dispersant adheresive, resin, or the like
  • the metal microparticles 8 After confirming that the metal microparticles 8 are inserted into all the holes, remove the extra metal microparticles 8 and place a flat polished carbon Place the 2 0 0 ° C or more is material of the plate 7, it is placed on a glass substrate of a flat table, in a nitrogen atmosphere 1 0 5 0 ° C (the temperature at which the viscosity of the glass becomes 1 0 5 poises) (Fig. 2 (5)). During heating, the metal microparticles 8 may be melted or may not be melted, as long as they are fixed in the through holes.
  • the metal microparticles 8 are sufficiently fixed by fusion, and the metal microparticles 8 are firmly fixed by heat shrinkage due to cooling after heating because the diameter of the metal microparticles 8 is small even in the through hole. Is done.
  • step (5) pressurizing the metal fine particles may be omitted.
  • Step (6) After that, unnecessary metal fine particles are removed, and the glass substrate filled with the metal fine particles in the through-hole is cooled to room temperature (FIG. 2 (6)).
  • Both sides of the glass substrate filled with metal fine particles 8 in through holes are polished flat Then, both ends of the metal fine particles 8 are completely exposed on the front and back surfaces of the glass substrate 1.
  • the front and back surfaces of the polished glass substrate 1 had a maximum height R max of 0.2 m or less.
  • the front and back surfaces are washed to obtain a through-hole-formed substrate 10 in which the front and back surfaces of the glass substrate 1 are electrically connected via the fine metal particles 8 inserted into the through-hole (FIG. 7))).
  • the thickness of the through-hole-formed substrate 10 was about 4 mm.
  • the substrate can be flattened.
  • a wiring layer is formed on both surfaces thereof to produce a double-sided wiring board.
  • the design is such that the wiring passes over the used through-holes, and the design does not allow the wiring to pass over the unused through-holes.
  • the wiring it is preferable to design the wiring so that the wiring that needs to be conductive between the front and back is connected through the nearest through hole. Also, it is preferable to design the through-hole formation position (and number) and wiring so that the wiring length on the front and back sides is as short as possible.
  • Through-hole forming substrate (core substrate) Wiring layers are formed on both sides of A or B by the spattering method or the plating method. Specifically, a Cr film is formed by sputtering at a thickness of about 300 angstroms, a Cu film is formed at a thickness of about 2.5 urn, and a Ni film is formed at a thickness of about 0.3 zm. A Cr / Cu / Ni wiring layer is formed.
  • a predetermined photolithography process resist coating, exposure, development, etching
  • the CrZCuZNi wiring layer is patterned.
  • a photosensitive polyimide precursor is applied on the first wiring pattern with a thickness of 10 m using a spinner or the like to form a polyimide insulating film, and a contact hole is formed in the polyimide insulating film.
  • the contact holes were formed by baking the coated photosensitive polyimide precursor at 80 ° C. for 30 minutes, exposing and developing using a predetermined mask.
  • a CrZCuZNi wiring layer is formed on the polyimide insulating film in which the contact hole is formed in the same manner as described above, and the CrZCuZNi wiring layer is patterned in the same manner as described above to form a second-layer wiring pattern.
  • a multilayer double-sided wiring board in which two-layer wiring patterns were formed on both sides of the through-hole forming substrate.
  • the film material of the wiring layer of the multilayer double-sided wiring board, the material of the insulating layer, the number of wiring layers and insulating layers, the film thickness, and the method of manufacturing the multilayer double-sided wiring board are not limited to those described above.
  • a Cr / CuZN i / Au multilayer structure As the film material of the wiring layer, a Cr / CuZN i / Au multilayer structure, a CuZN i / Au multilayer structure, or the like may be used in addition to the above-mentioned CrZCuZNi.
  • Examples of the material of the insulating layer include an acrylic resin and an epoxy resin in addition to the polyimide described above. Among them, polyimide having a low expansion coefficient and excellent in heat resistance and chemical resistance is preferable.
  • the wiring layer and the wiring pattern are formed simultaneously on both sides in the above description, but the wiring layer and the wiring pattern may be formed one by one while protecting the back surface.
  • the wafer contact board of Production Example 1 was composed of a multilayer double-sided wiring board, an anisotropic conductive rubber sheet, and a membrane with bumps (Fig. 4).
  • the multilayer double-sided wiring board (having a size of 20 Omm ⁇ or more) is a core substrate A or 3600 through-holes formed in an array on the entire surface of the substrate by the above method. It is manufactured by forming a multilayer wiring layer on both sides using B, and the wiring on both sides is electrically contacted by conductive members (wires, metal fine particles, etc.) inserted in through holes. ing.
  • the pad portion is electrically connected to the tester using, for example, a pogo pin (an extensible pin containing a panel).
  • a pogo pin an extensible pin containing a panel
  • the wiring on the front side of the multilayer double-sided wiring board consists of wiring for passing electric signals, elements (chip resistors, chip capacitors, etc.) and pad electrodes corresponding to the pad electrodes formed on the wafer to be inspected. And are formed. Then, a bumped membrane formed by forming an isolated pad and an isolated bump on the front and back surfaces of a polyimide film or the like via an anisotropic conductive sheet with cushioning properties in the middle layer (isolated pad on the front and back surfaces Z via hole between isolated bumps) It is electrically connected to the pad electrode on the wafer via the bump.
  • the multilayer double-sided wiring board shown in Fig. 4 has the number of holes and the required through-holes so that the through holes are evenly drilled per chip corresponding to the chips formed on the wafer.
  • a plurality of pads are formed on the back side with a wider pitch and fewer pads than the pads on the front side corresponding to the pads formed on the wafer, but through holes are formed on the entire back side It is characteristic that it is done.
  • the pad electrode on the back surface connected through the through hole corresponding to each chip on the front side is basically formed near the upper part of the wafer chip, and conduction to the outside is connected almost vertically or by the shortest path.
  • This core substrate has conductive through holes throughout the substrate (a conductive member is inserted into the through hole so that the front and back surfaces of the substrate can be electrically connected so that the type of device under test can be changed). Are formed at predetermined positions and standardized. By doing so, it is possible to manufacture at low cost.
  • the through holes are formed radially, concentrically or in an array on the entire surface of the core substrate, all of which are filled with wires, fine metal particles, or conductive paste, solder metal, or metal plating. .
  • Board hole If there is a gap between 2003/010515 and its conductive material (for example, when filled with fine metal particles), the gap may be sealed with a non-conductive material such as resin.
  • the core substrate material must be heat-resistant because it is used at high temperatures, and it must have excellent positional accuracy at low and high temperatures. Therefore, the coefficient of thermal expansion must be 15 ppm or less. The difference in the coefficient of thermal expansion must be 13.82 ppm or less), preferably 10 ppm or less, more preferably 5 ppm or less.
  • Such materials include, for example, ceramics such as Si, alumina, SiC, and SiN, Pyrex, quartz glass, aluminoborosilicate glass, and Corning 705, 11 ⁇ Low-expansion glass such as Eighty-four, forty-five and forty-five.
  • the core substrate material does not necessarily need to be an insulating material.
  • the inside of the through hole should be insulated with oxide, resin, etc. Therefore, it is necessary to embed the conductive material inside the through hole.
  • an insulating substrate is not used, it is necessary to form wiring after insulating the surface, but conversely, by grounding the core substrate itself using the conductivity of the core substrate, A multilayer wiring board having excellent high-frequency characteristics and low-noise characteristics can be obtained. In this case, it goes without saying that the GRD of the wiring is conducted to the conductive portion inside the core substrate (the portion in which the conductive material is embedded without insulating the inside of the through hole).
  • the core substrate material is a photosensitive glass
  • the photosensitive glass substrate is exposed through a mask so that a latent image is formed in a portion where a large number of holes are formed, and the exposed portion is crystallized.
  • the crystallized region may be dissolved and removed to form a large number of holes to form a core substrate.
  • narrower holes small through-hole diameters
  • the anisotropic conductive sheet is formed so as to have conductivity in the vertical direction, and may have a structure in which wires are buried in an elastic body such as rubber in the vertical direction, and conductive particles such as metal may be used.
  • a structure embedded on one side or locally may be adopted.
  • an isolated copper pad is formed on the back surface of a polyimide film, and a metal pad formed by a photolithography method may be formed on the front surface thereof. But it may be The isolated pad on the PC leakage 003/010515 surface and the pad or bump on the front side are electrically connected through the inside of the film.
  • the structure of the flexible film may be reversed.
  • the bumped membrane has flexibility, but does not have to have cushioning.
  • the wafer contact board of Fabrication Example 2 consists of a multilayer double-sided wiring board and a small contact probe with spring properties (Fig. 5).
  • the pad electrode on the front side of the multilayer double-sided wiring board in the wafer contact node 20 is a small contact probe ( ⁇ material or structural) that has spring properties (material or structural). ) Can be connected to the pad electrode on the wafer via the above.
  • the wire material such as a needle having a paneling property is mechanically and electrically bonded to the pad electrode on the front side of the multilayer double-sided wiring board by soldering, heat fusion, or other methods.
  • the metal wires may be joined by applying a wire-to-bonding technique, or the joining may be carried out by using a technique such as a fine solder formed by applying a micromachine technique.
  • the pad electrode on the front side of the multilayer double-sided wiring board may be configured to be directly connected to the pad electrode on the wafer.
  • the pad electrode on the front side of the multilayer double-sided wiring board may be configured to be connected to the pad electrode on the wafer via an anisotropic member such as an anisotropic elastic sheet that can be repeatedly contacted.
  • a bump made of a soft material such as a conductive compressive material (eg, solder pole, Au, etc.) is formed on the pad electrode on the front side of the multilayer double-sided wiring board or on the pad electrode itself.
  • a contact one-time contact or a member that is not durable repeatedly is formed, or formed separately (sandwiched) and connected to the electrodes of the device under test, elements, etc. You can also. Other items are the same as those in the first example of the wafer-bound contact port.
  • the temperature is reduced to a temperature not lower than the softening temperature of the substrate and not higher than the temperature at which the shape of the substrate can be maintained.
  • the conductive member can be sufficiently fixed by fusion.
  • the conductive member can be firmly fixed by heat shrinkage due to cooling after heating.
  • sealing is performed without gaps by fusion and heat shrinkage, corrosion resistance and the like can be improved.
  • the conductive member is fixed by fusion and / or heat shrinkage, it can be fixed at a time even if the number of through holes is large. Further, by inserting the wire by vibration, extremely low cost of the wire inserting process can be achieved.
  • a large number of drills are arranged at regular intervals on one surface of a substrate to be processed, and ultrasonic waves are applied to the drills to form a large number of holes on the substrate to be processed. Since the holes are collectively formed, the cost of a through-hole forming substrate having a large number of holes can be realized. Therefore, an inexpensive double-sided wiring board can be realized using this inexpensive through-hole formed substrate.
  • a through-hole formed substrate with high precision, low thermal expansion, and excellent surface flatness, in which a large number of narrow and fine through holes with high positional accuracy are formed on the entire surface of the substrate, is inexpensive Can be realized.
  • a wafer-bound contact board for high-frequency applications can be realized.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

La présente invention a trait à un substrat perforé obtenu par l'alésage d'une pluralité de trous (5) dans un substrat en verre (1) par la vibration d'un gabarit de perçage présentant une pluralité de forets (3). Suite au remplissage de chaque trou du substrat perforé avec organe conducteur, on soumet le substrat perforé à un traitement thermique à une température égale ou supérieure à la température de ramollissement du substrat en verre et à laquelle le substrat peut préserver sa forme, de sorte que l'organe conducteur soit fixé dans chaque trou. On peut faire suivre le traitement thermique d'un traitement de refroidissement en vue d'une rétreinte thermique du substrat. Suite à la fixation de l'organe conducteur dans le substrat perforé, on effectue un polissage des surfaces du substrat perforé afin d'exposer l'organe conducteur à partir des faces arrière et avant du substrat. On peut obtenir un substrat câblé en dotant chaque face du substrat poli d'une couche de câblage.
PCT/JP2003/010515 2002-08-21 2003-08-20 Substrat perfore, son procede de fabrication et carte de contact a tranche pleine Ceased WO2004019668A1 (fr)

Priority Applications (1)

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JP2004530579A JP4071768B2 (ja) 2002-08-21 2003-08-20 ホール形成基板及びその製造方法並びにウェハ一括コンタクトボード

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JP2002240839 2002-08-21
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WO2006129848A1 (fr) * 2005-06-03 2006-12-07 Intelligent Cosmos Research Institute Procede de production de panneau de cablage encastre dans du verre, panneau de cablage encastre dans du verre et carte de sonde et element d’encapsulation utilisant ce panneau
JP2012019106A (ja) * 2010-07-08 2012-01-26 Seiko Instruments Inc 貫通電極付きガラス基板の製造方法及び電子部品の製造方法
JP2012019107A (ja) * 2010-07-08 2012-01-26 Seiko Instruments Inc 貫通電極付きガラス基板の製造方法及び電子部品の製造方法
JP2022548213A (ja) * 2019-09-12 2022-11-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 剛性プローブのためのコンプライアント有機基板アセンブリ

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KR20030064004A (ko) * 2002-01-25 2003-07-31 김용현 약욕제
KR101817328B1 (ko) * 2011-02-01 2018-02-22 삼성전자주식회사 반도체 모듈 제조 방법
DE102019201347B3 (de) 2019-02-01 2020-06-18 Lpkf Laser & Electronics Ag Herstellung von metallischen Leiterbahnen an Glas
KR102224955B1 (ko) * 2020-03-25 2021-03-09 (주)비티비엘 배터리의 고체전해질막의 제조방법 및 그에 의한 고체전해질막

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EP1085326A2 (fr) * 1999-09-13 2001-03-21 Hoya Corporation Plaquette multicouche de circuits imprimés, procédé de fabrication et plaquette de contact pour un wafer
WO2001039561A1 (fr) * 1999-11-26 2001-05-31 Matsushita Electric Industrial Co., Ltd. Panneau de connexion et procede de production associe
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JP2001230545A (ja) * 2000-02-15 2001-08-24 Ngk Insulators Ltd プリント回路用基板材の製造方法及びワイヤ構造体の製造装置
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JPH0384452U (fr) * 1989-12-19 1991-08-27
JPH04111799A (ja) * 1990-08-31 1992-04-13 Ikegai Corp 超音波加工機
JPH10190190A (ja) * 1996-10-31 1998-07-21 Hoya Corp 基板およびその製造方法
EP1079676A2 (fr) * 1999-08-26 2001-02-28 Sony Chemicals Corporation Procédés de fabrication de panneaux à circuit flexibles, et les panneaux à circuit flexibles obtenus
EP1085326A2 (fr) * 1999-09-13 2001-03-21 Hoya Corporation Plaquette multicouche de circuits imprimés, procédé de fabrication et plaquette de contact pour un wafer
JP2001177011A (ja) * 1999-10-05 2001-06-29 Fujitsu Ltd 実装基板の製造方法及びそれにより製造された実装基板
WO2001039561A1 (fr) * 1999-11-26 2001-05-31 Matsushita Electric Industrial Co., Ltd. Panneau de connexion et procede de production associe
JP2001160678A (ja) * 1999-12-01 2001-06-12 Hoya Corp 表裏導通基板の製造方法及び半導体実装基板の製造方法
JP2001230545A (ja) * 2000-02-15 2001-08-24 Ngk Insulators Ltd プリント回路用基板材の製造方法及びワイヤ構造体の製造装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006129848A1 (fr) * 2005-06-03 2006-12-07 Intelligent Cosmos Research Institute Procede de production de panneau de cablage encastre dans du verre, panneau de cablage encastre dans du verre et carte de sonde et element d’encapsulation utilisant ce panneau
JP2012019106A (ja) * 2010-07-08 2012-01-26 Seiko Instruments Inc 貫通電極付きガラス基板の製造方法及び電子部品の製造方法
JP2012019107A (ja) * 2010-07-08 2012-01-26 Seiko Instruments Inc 貫通電極付きガラス基板の製造方法及び電子部品の製造方法
JP2022548213A (ja) * 2019-09-12 2022-11-17 インターナショナル・ビジネス・マシーンズ・コーポレーション 剛性プローブのためのコンプライアント有機基板アセンブリ
JP7475436B2 (ja) 2019-09-12 2024-04-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 剛性プローブのためのコンプライアント有機基板アセンブリ

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