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WO2004019668A1 - Perforated substrate, method for manufacturing same and full wafer contact board - Google Patents

Perforated substrate, method for manufacturing same and full wafer contact board Download PDF

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Publication number
WO2004019668A1
WO2004019668A1 PCT/JP2003/010515 JP0310515W WO2004019668A1 WO 2004019668 A1 WO2004019668 A1 WO 2004019668A1 JP 0310515 W JP0310515 W JP 0310515W WO 2004019668 A1 WO2004019668 A1 WO 2004019668A1
Authority
WO
WIPO (PCT)
Prior art keywords
hole
substrate
conductive member
holes
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2003/010515
Other languages
French (fr)
Japanese (ja)
Inventor
Osamu Sugihara
Yoichi Hachitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hoya Corp
Original Assignee
Hoya Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hoya Corp filed Critical Hoya Corp
Priority to JP2004530579A priority Critical patent/JP4071768B2/en
Publication of WO2004019668A1 publication Critical patent/WO2004019668A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/16Magnets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • H10P74/00
    • H10W70/095
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10416Metallic blocks or heatsinks completely inserted in a PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01Tools for processing; Objects used during processing
    • H05K2203/0104Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108Male die used for patterning, punching or transferring
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025Abrading, e.g. grinding or sand blasting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0292Using vibration, e.g. during soldering or screen printing
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H10W72/07251
    • H10W72/20

Definitions

  • the present invention relates to a hole-formed substrate in which a conductive member is buried in a hole formed with the substrate, a method of manufacturing the same, and the like, and more particularly, to a through-hole formed substrate having a through-hole penetrating the substrate,
  • the present invention relates to a method for manufacturing a double-sided wiring board and a wafer-filled (full-wafer) contact board using the double-sided wiring board.
  • this type of through-hole forming substrate is used for an inspection device for semiconductors and the like.
  • the semiconductor inspection process is performed in a plurality of stages.
  • wafers manufactured in the wafer manufacturing process pre-process
  • wafer manufacturing process pre-process
  • WLBI wafer level burn-in
  • the probe card test is generally a DCZAC test using one chip or a multi-contact probe card (up to 64 chips).
  • a probe force as shown in FIGS. 6A and 6B, an opening 62 is provided at the center of a multilayer wiring board 61 made of glass epoxy resin, and the periphery of the opening 62 is provided.
  • a probe (probe) 63 is provided toward the center of the opening 62 from the probe 62, and the probe 63 is brought into contact with the electrode terminal 42 on the one chip 41 of the wafer 40 to perform a test.
  • one of the membranes 71 made of polyimide or the like is used.
  • a membrane probe card of a type using a membrane 70 with bumps provided with bumps 72 (convex contacts) on the surface as a contact component has also been proposed.
  • the bumps 72 are electrically connected to the wiring 74 via the through holes 73 formed in the membrane 71, and the bumps 72 are formed on the conductive material 75, the pivot mechanism 76, the plate panel 7 It is pressed through 7 and contacted.
  • Burn-in inspection is a high-temperature accelerated test that is usually performed on a chip-by-chip basis, and often involves electrical testing. When performing burn-in inspection on a wafer, it is called wafer level burn-in (WL B I). When conducting burn-in inspection on wafers, it is necessary to commercialize wafer-contact contact boards (burn-in pads).
  • the final inspection includes the final electrical test, a simple on-off test, and a function test at the actual operating frequency of the device. Specifically, one or more bare chips and packaged products are pressed directly against the test head using the handler via the interposer and measured. In some cases, measurement is performed using a high-frequency probe card (up to 64 chips) in the wafer state. Disclosure of the invention
  • the probe card inspection process described above covers from 1 chip to 64 chip multi-measurement, but if this is possible, it is possible to greatly reduce the inspection time and the cost Becomes possible.
  • the inspection time can be greatly reduced, and the inspection cost can be significantly reduced.
  • a glass substrate is used as a core substrate of a multilayer wiring substrate in order to realize contact with all chips on a wafer.
  • the core substrate using this glass substrate is a single-sided wiring in which a wiring layer is formed only on one surface, so the number of wiring layers formed on the surface increases, and fine processing is required, resulting in high costs.
  • the length of the extraction electrode (wiring) becomes longer in terms of characteristics, and as a result, the resistance value increases and the impedance increases.
  • matching and equal length wiring become difficult.
  • the wiring layer is formed on one side of the glass substrate surface. Since it is formed only on the (wafer side), there is an inconvenience that elements such as resistors, capacitors, and fuses cannot be mounted on the wiring layer. This is because, since the device has a thickness, electrodes such as contact bumps provided on the glass substrate cannot contact the pad on the wafer due to the effect of the device having a large thickness. Therefore, it is considered that a probe detection probe using a glass substrate cannot be applied to high frequency applications or DC inspection applications.
  • the wafer-bound contact port for high-frequency applications for inspecting wiring boards such as LSI inspections and MCMs (multi-chip modules) is a through-hole (narrow pitch) that electrically connects the front and back surfaces. It is considered necessary to form a large number of thin, high-precision through holes on the entire surface of the substrate and a board with a multilayered structure.
  • a double-sided wiring board in which a large number of through holes are formed in a glass substrate has not yet been proposed. This is because when using a glass substrate, there are many problems to be solved in terms of accuracy, thermal expansion, and surface flatness, and mechanical strength and workability.
  • a method for manufacturing a double-sided wiring board from a glass substrate a method of drilling one hole in a glass substrate with a drill (for example, Japanese Utility Model Registration No. 30844542) can be considered. If thousands to tens of thousands of holes are formed by a drill, the cost of hundreds of thousands to several millions of yen is required, and it is impossible to realize the cost at all.
  • molten glass is poured into a molding frame with a plurality of linear conductors stretched, or a plurality of linear conductors are sandwiched between two sheet glasses to soften or fluidize the sheet glass.
  • a block body in which a plurality of linear conductors are buried, and cut the block body to obtain a through-hole-formed substrate Japanese Patent Laid-Open No. H10-19001.
  • the wires may actually bend and the position is not determined, and the position accuracy of the through-hole must be ensured. There is a problem that it is difficult.
  • An object of the present invention is to provide a method for manufacturing a hole-formed substrate and a through-hole formed substrate, which can easily and inexpensively realize a wafer-bound contact port for high frequency use.
  • the present invention has the following configuration.
  • the conductive member fixing step may include heating the hole-forming substrate at a temperature equal to or higher than a softening point temperature of the hole-forming substrate and equal to or lower than a temperature at which a substrate shape can be maintained.
  • the conductive member fixing step may include a step of heating the hole formation substrate at a temperature higher than a softening point temperature of the hole formation substrate and lower than a temperature at which a substrate shape can be maintained; Cooling the substrate after heating to thereby thermally shrink the substrate, whereby the conductive member is fixed to each hole.
  • the hole forming substrate is made of glass material, in the conductive member fixing step, so that the viscosity of the glass becomes 1 0 4 -1 0 11 poises, heat the pre-Symbol hole forming substrate
  • a method for manufacturing a hole-formed substrate comprising:
  • a substrate to be processed and a drill jig in which a plurality of drills are implanted are prepared, and a drill jig having the plurality of drills is provided on one surface of the substrate to be processed.
  • a method of manufacturing a hole-formed substrate comprising: forming a plurality of holes at once by vibrating the drill jig in a state where the tools are in contact with each other, and forming the hole-formed substrate.
  • (Structure 6) A method of manufacturing a hole-formed substrate according to structure 5, wherein ultrasonic waves are applied to the drill jig to form a plurality of holes at a time.
  • the step of burying the conductive member may include the step of embedding a linear conductor having a smaller diameter in each hole of the hole forming substrate on the surface of the hole forming substrate in which the hole is formed. After placing, each hole is given by applying vibration to the hole substrate.
  • the hole forming substrate is A conductive member fixing step of fixing the conductive member in each hole by heat treatment together with the embedded conductive member. Further, in the invention according to Configuration 2, the conductive member fixing step is performed at a temperature equal to or higher than a softening temperature of the hole-forming substrate, The method includes a step of fusing the conductive member by heating the substrate to a temperature at which the substrate shape can be maintained, and the conductive member can be sufficiently fixed by fusing.
  • the invention according to the third aspect further includes a step of heat-shrinking the substrate by cooling the hole-formed substrate after heating, and fixing the conductive member.
  • the conductive member can be firmly fixed by the heat shrinkage.
  • the present invention includes the step of fixing the conductive member by fusion and Z or heat shrinkage, so that even if the number of through holes is large, it can be fixed at once, An inexpensive (low-priced) through-hole forming substrate can be realized.
  • a conductive member is inserted or filled into each hole in the hole-formed substrate in which a large number of holes (not necessarily through-holes) are formed, Japanese Patent Application Laid-Open No.
  • the linear conductor wire, etc.
  • the conductive member include a linear conductor (for example, a wire), metal particles, and other conductive materials. In the case of wire, there is no risk of disconnection.
  • the viscosity of the glass at the conductive member fixing step heats the glass material so that 1 0 4 -1 0 11 poises.
  • 1 0 4 poises means working temperature temperature (molding temperature) around the glass, when it from the low viscosity, not keep the board shaped glass is excessively softened.
  • 1 0 11 poises means the viscosity near the yield point of the glass, when it than the viscosity is high, it is difficult to mold the glass.
  • the hole-forming substrate may include a plurality of holes formed by vibrating the drill jig in a state where the drill jig having the plurality of drills is in contact with one surface of the substrate to be processed. Are formed all at once, so a larger number of holes are required than when using a single-blade drill or a single-blade ultrasonic drill to drill holes sequentially. Since the holes are formed together, the cost of a hole-formed substrate having a large number of holes can be realized.
  • the drill jig has a narrow pitch (for example, 3 mm pitch or less) and is thin (for example, the through hole diameter is small). It was found that a substrate having a large number of holes (0.5 ⁇ or less) formed on the entire surface of the substrate could be obtained. In other words, it was found that even if many holes were finely formed at a narrow pitch, there was no breakage at all. This is thought to be due to the fact that the processing is performed with the drill bit inserted in all the holes, and the force acts uniformly. Drilling a new hole at a narrow pitch near an already formed hole may cause damage.
  • a narrow pitch for example, 3 mm pitch or less
  • the through hole diameter is small
  • the drill for applying the ultrasonic wave is formed by forming a large number of drill blades on one surface of the substrate, the number and the number of drills being stably self-supporting with respect to the substrate to be processed. If the drill is not stable and self-supporting, it is difficult to keep the drill horizontal with respect to the substrate to be processed, and it is not possible to realize vertical drilling with high hole diameter accuracy.
  • the drill to which the ultrasonic wave is applied has a large number of drill blades formed and arranged on one surface of the substrate so that the drill blades are not bent by their own weight. If the drill blade is bent by the weight of the drill, drilling with vertical and high hole diameter accuracy cannot be realized.
  • the number of drill bits is preferably 50 or more, more preferably 100 or more.
  • the number of drill blades is preferably 500 or more, and more preferably 100 or more, from the viewpoint of reducing the number of drilling times and the cost of manufacturing a drill.
  • the hole formed by the drill may be a through hole that penetrates the substrate to be processed or a hole that does not penetrate. If it does not penetrate, no linear conductor (eg, wire) or metal particles that enter or fill the hole will fall out of the bottom opening, so no measures to prevent falling off are necessary. If not penetrated, the non-penetrated part is removed by polishing to expose the linear conductor (for example, wire) and metal particles. When penetrating, the diameter of the bottom opening is smaller than the diameter of the linear conductor or metal particle, and the diameter of the linear conductor or metal particle is smaller than that of the bottom opening.
  • the diameter of the bottom opening is smaller than the diameter of the linear conductor or metal particle, and the diameter of the linear conductor or metal particle is smaller than that of the bottom opening.
  • the preferred surface roughness is an arithmetic average roughness Ra of 0.2 m or less, more preferably, a Ra of 0.1 m or less.
  • the arithmetic average roughness Ra described above is measured based on the measurement method defined in JIS B601-1994.
  • the surface of the substrate to be processed is ground or polished. Existing cracks and scratches can be minimized, and cracks (breakage) can be effectively reduced when a large number of holes are formed at once by applying ultrasonic waves. There is an advantage called.
  • an ultrasonic wave an ultrasonic wave having a frequency of several kHz to several hundred kHz can be used.
  • the diameter of the linear conductor is 90% or less of the hole diameter, further 85% or less, and further 80%. It is preferable to set the following.
  • the length of the linear conductor is preferably about the same as the depth of the hole, more preferably slightly longer than the depth of the hole, and more preferably about 1.1 times the depth of the hole.
  • the material of the linear conductor is preferably a material that allows the linear conductor to be automatically and smoothly inserted into all the holes.
  • the surface of the hole-forming substrate to which the conductive member is fixed is polished, and the conductive member is provided on both opposed surfaces.
  • a through-hole-formed substrate in which the front and back surfaces of the substrate are electrically connected by the conductive member is obtained.
  • a step of polishing one or both surfaces of the substrate is provided, whereby the metal surface of the conductive member can be exposed, and the oxide film can be formed. Problems can be avoided. Also, by removing the ends (portions protruding from the holes) of the linear conductor by polishing, complicated work such as adjusting the length of the linear conductor is not required. In addition, the polishing can impart or improve the flatness of the substrate. Furthermore, if the surface of the substrate and the end surface of the conductive member are made flush with each other by polishing, the level of the flush is higher than in the case of flushing with other methods. This is advantageous in terms of connectivity.
  • the polishing amount on one side is preferably 1 mm or less, more preferably 0.5 mm or less from the viewpoint of manufacturing cost.
  • the substrate surface after polishing has a maximum height R max of 2 or less, preferably 0.2 m or less.
  • R max of 2 or less, preferably 0.2 m or less.
  • an inexpensive wiring board can be realized by using the inexpensive through-hole formation substrate according to the ninth aspect and forming a wiring layer on the conductive member exposed on at least one surface.
  • the wiring layer can be a single layer or a multilayer. Further, the wiring layer can be formed on any one surface or both surfaces. Both wiring layers If it is formed on one side, it will be a double-sided wiring board.
  • the wiring layer includes wiring and electrodes.
  • a photolithography method, a built-up method (in the case of a multilayer), a printing method, or other known wiring or multilayer wiring technology is used.
  • the wiring board described in the configuration 10 is particularly suitable as a multilayer wiring board for a wafer-bound contact board when the number of through holes is large (for example, 200 or more).
  • the through-hole-forming substrate which is the base material of the double-sided wiring substrate, needs to have low thermal expansion and high surface flatness. This is for contacting the whole surface with the wafer and conducting and inspecting. It is preferable that the through-hole-forming substrate, which is the base material of the double-sided wiring substrate, has a coefficient of thermal expansion of 15 ppm or less. It is preferable that the surface flatness over the entire through-hole forming substrate, which is the base material of the double-sided wiring substrate, is 40 m or less.
  • the wafer contact board of the present invention it is necessary to use, as a base material of the double-sided wiring board, a through-hole forming substrate in which a large number of narrow through holes with a narrow pitch are formed with high precision over the entire surface. This is in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for probe inspection and specific burn-in inspection).
  • a large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate in order to correspond to an electrode to be inspected such as a semiconductor element.
  • An object of the present invention is to make it possible to manufacture a wafer-contacted contact board in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for a burn-in inspection specific to probe inspection) by contacting the entire surface.
  • a large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate.
  • the conductive pad electrode on the back surface is basically formed near the upper part of the chip on the wafer and has a structure in which conduction to the outside is connected almost vertically or by the shortest path. That is, the back pad is preferably formed at the shortest position with respect to the electrode on each chip.
  • the through-hole-formed substrate may have a standardized conductive through-hole on the entire surface of the substrate so that the type of the device under test can be changed. Is preferably formed at the position. By doing so, it can be manufactured at a low cost.
  • through holes can be formed radially, concentrically, or in an array over the entire surface of the substrate.
  • the substrate size of the wafer-contacting contact port is at least as large as the wafer size.
  • the thickness of the substrate is preferably about 2 to 7 mm in order to obtain mechanical durability and accurately form a through-hole.
  • the number of through holes is determined in relation to the number of chip elements such as resistors and capacitors mounted on the substrate, and is preferably the number of chip elements X 2 (for example, 100 or more). It is preferable that the pitch of the through-holes is 3 mm or less as long as the mechanical durability between the through-holes can be obtained, and the diameter of the through-hole is 0.1 to 0.5 ⁇ .
  • the wafer package contact port includes a wafer package burn-in inspection board, a wafer batch probe inspection board, and a wafer package final inspection port. '
  • a wafer batch contact port manufactured using such a through-hole formed substrate having a large number of through-holes formed on the entire surface of the substrate has not been obtained.
  • it is characterized in that a through-hole forming substrate having a large number of through-holes formed on the entire surface of the substrate is used.
  • the substrate in a substrate having a configuration in which a plurality of conductive members are embedded in a plurality of holes, the substrate is formed of a glass material, and a surface in which the conductive member is embedded has a maximum height.
  • a substrate polished so as to have a surface roughness of 2 ⁇ m or less at R max disconnection of a wiring layer formed on the surface of the substrate can be prevented.
  • the thickness of the wiring layer is equal to or greater than the thickness having a function as the wiring layer and is as small as 5 m or less, the substrate of Configuration 12 is particularly effective.
  • FIG. 1 (1) to 1 (7) are schematic views showing a method of manufacturing a through-hole formed substrate according to an embodiment of the present invention in the order of steps.
  • FIG. 4 is a schematic view showing a manufacturing method of the present invention in the order of steps.
  • FIG. 3 is a graph showing a viscosity curve of the low expansion glass used in the embodiment of the present invention.
  • FIG. 4 is a schematic view illustrating a wafer contact port including a through hole forming substrate according to the present invention.
  • FIG. 5 is a schematic view for explaining another wafer contact contact including the through hole forming substrate according to the present invention.
  • 6 (a) and 6 (b) are a plan view and a cross-sectional view illustrating an example of a probe card.
  • FIG. 7 is a partial cross-sectional view for explaining another probe card. BEST MODE FOR CARRYING OUT THE INVENTION
  • a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared.
  • the surface roughness of the low-expansion glass substrate 1 was Ra, which was 0.2 ⁇ m or less.
  • the surface roughness was measured using a stylus type surface roughness meter (trade name: Tencor ⁇ 2: Tencor Measured by Instruments).
  • the viscosity curve (temperature vs viscosity (log)) of the low expansion glass substrate # 45 has the characteristics shown in FIG. This viscous force one blanking, the temperature range in which the viscosity of the glass becomes 1 0 4 -1 0 11 poises is found to be 710 ° C ⁇ 1 17 5 ° C.
  • 3 x 30 900 holes drilled in a 3 x 30 screw holes with a pitch of 3 mm and a diameter of 0.5 mm. (8 mm in length) is inserted to form a drill jig with drill 3.
  • the drill 3 forming the drill jig 3 is formed of stainless steel, iron, tungsten, or the like.
  • a number of tungsten wires 6 are placed on the glass substrate 1 and subjected to the same ultrasonic vibration as in Fig. 1 (2).
  • the wire 6 is automatically inserted into the hole at once.
  • the wire 6 can be automatically and smoothly inserted into all holes, and it can be recovered and reused, so that it is also environmentally friendly.
  • the glass is softened, and the wire 16 is introduced into the softened glass (at the bottom of the hole) by the weight of the force plate 7, and further melts with the glass hole into which the wire 16 is inserted.
  • the wire 6 is attached and fixed.
  • step (6) Cooling glass substrate
  • the diameter of the wire 16 is smaller than the diameter of the through hole.
  • the through-hole shrinks and the wire 6 is firmly fixed. Then wire The attached glass substrate is cooled to room temperature (Fig. 1 (6)).
  • Step (7) Double-side polishing (a step of exposing both ends of the wire to the surface of the glass substrate) Both surfaces of the glass substrate with wires are polished flat, and the wires 6 are completely exposed to the front and back surfaces of the glass substrate.
  • the exposed surface of the wire 16 and the front and back surfaces of the glass substrate 1 need to be polished so that they substantially coincide with each other.
  • the surface roughness at this time was less than 0.2 m at the maximum height Rmax.
  • the thickness of the through-hole formed substrate 10 was about 4 mm.
  • a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared.
  • the surface roughness of the surface of the low expansion glass substrate 1 was Ra, which was 0.2 ⁇ m or less.
  • the surface roughness was measured by a stylus type surface roughness meter (Tencor P2). )
  • metal fine particles 8 were used instead of the wires.
  • the fine metal particles 8 are vibrated, the fine metal particles 8 are automatically and collectively inserted into the holes (FIG. 2 (4)).
  • metal fine particles 8 metal fine particles of solder, tungsten, copper, nickel, gold, silver, or the like, or fine particles of an alloy thereof, or metal particles of nickel or the like whose surface is plated with gold can be used.
  • the metal fine particles 8 it is desirable that the metal fine particles 8 have a particle diameter of 1/10 or less of the hole diameter.
  • the packing density of the metal fine particles in the hole can be increased.
  • metal fine particles 8 instead of the metal fine particles 8, a method in which metal particles or the like are dispersed in a dispersant (adhesive, resin, or the like) may be used to fill the holes. In this case, when the drilled hole is completely penetrated, the metal particles dispersed in the dispersant can be completely filled in the hole.
  • a dispersant adheresive, resin, or the like
  • the metal microparticles 8 After confirming that the metal microparticles 8 are inserted into all the holes, remove the extra metal microparticles 8 and place a flat polished carbon Place the 2 0 0 ° C or more is material of the plate 7, it is placed on a glass substrate of a flat table, in a nitrogen atmosphere 1 0 5 0 ° C (the temperature at which the viscosity of the glass becomes 1 0 5 poises) (Fig. 2 (5)). During heating, the metal microparticles 8 may be melted or may not be melted, as long as they are fixed in the through holes.
  • the metal microparticles 8 are sufficiently fixed by fusion, and the metal microparticles 8 are firmly fixed by heat shrinkage due to cooling after heating because the diameter of the metal microparticles 8 is small even in the through hole. Is done.
  • step (5) pressurizing the metal fine particles may be omitted.
  • Step (6) After that, unnecessary metal fine particles are removed, and the glass substrate filled with the metal fine particles in the through-hole is cooled to room temperature (FIG. 2 (6)).
  • Both sides of the glass substrate filled with metal fine particles 8 in through holes are polished flat Then, both ends of the metal fine particles 8 are completely exposed on the front and back surfaces of the glass substrate 1.
  • the front and back surfaces of the polished glass substrate 1 had a maximum height R max of 0.2 m or less.
  • the front and back surfaces are washed to obtain a through-hole-formed substrate 10 in which the front and back surfaces of the glass substrate 1 are electrically connected via the fine metal particles 8 inserted into the through-hole (FIG. 7))).
  • the thickness of the through-hole-formed substrate 10 was about 4 mm.
  • the substrate can be flattened.
  • a wiring layer is formed on both surfaces thereof to produce a double-sided wiring board.
  • the design is such that the wiring passes over the used through-holes, and the design does not allow the wiring to pass over the unused through-holes.
  • the wiring it is preferable to design the wiring so that the wiring that needs to be conductive between the front and back is connected through the nearest through hole. Also, it is preferable to design the through-hole formation position (and number) and wiring so that the wiring length on the front and back sides is as short as possible.
  • Through-hole forming substrate (core substrate) Wiring layers are formed on both sides of A or B by the spattering method or the plating method. Specifically, a Cr film is formed by sputtering at a thickness of about 300 angstroms, a Cu film is formed at a thickness of about 2.5 urn, and a Ni film is formed at a thickness of about 0.3 zm. A Cr / Cu / Ni wiring layer is formed.
  • a predetermined photolithography process resist coating, exposure, development, etching
  • the CrZCuZNi wiring layer is patterned.
  • a photosensitive polyimide precursor is applied on the first wiring pattern with a thickness of 10 m using a spinner or the like to form a polyimide insulating film, and a contact hole is formed in the polyimide insulating film.
  • the contact holes were formed by baking the coated photosensitive polyimide precursor at 80 ° C. for 30 minutes, exposing and developing using a predetermined mask.
  • a CrZCuZNi wiring layer is formed on the polyimide insulating film in which the contact hole is formed in the same manner as described above, and the CrZCuZNi wiring layer is patterned in the same manner as described above to form a second-layer wiring pattern.
  • a multilayer double-sided wiring board in which two-layer wiring patterns were formed on both sides of the through-hole forming substrate.
  • the film material of the wiring layer of the multilayer double-sided wiring board, the material of the insulating layer, the number of wiring layers and insulating layers, the film thickness, and the method of manufacturing the multilayer double-sided wiring board are not limited to those described above.
  • a Cr / CuZN i / Au multilayer structure As the film material of the wiring layer, a Cr / CuZN i / Au multilayer structure, a CuZN i / Au multilayer structure, or the like may be used in addition to the above-mentioned CrZCuZNi.
  • Examples of the material of the insulating layer include an acrylic resin and an epoxy resin in addition to the polyimide described above. Among them, polyimide having a low expansion coefficient and excellent in heat resistance and chemical resistance is preferable.
  • the wiring layer and the wiring pattern are formed simultaneously on both sides in the above description, but the wiring layer and the wiring pattern may be formed one by one while protecting the back surface.
  • the wafer contact board of Production Example 1 was composed of a multilayer double-sided wiring board, an anisotropic conductive rubber sheet, and a membrane with bumps (Fig. 4).
  • the multilayer double-sided wiring board (having a size of 20 Omm ⁇ or more) is a core substrate A or 3600 through-holes formed in an array on the entire surface of the substrate by the above method. It is manufactured by forming a multilayer wiring layer on both sides using B, and the wiring on both sides is electrically contacted by conductive members (wires, metal fine particles, etc.) inserted in through holes. ing.
  • the pad portion is electrically connected to the tester using, for example, a pogo pin (an extensible pin containing a panel).
  • a pogo pin an extensible pin containing a panel
  • the wiring on the front side of the multilayer double-sided wiring board consists of wiring for passing electric signals, elements (chip resistors, chip capacitors, etc.) and pad electrodes corresponding to the pad electrodes formed on the wafer to be inspected. And are formed. Then, a bumped membrane formed by forming an isolated pad and an isolated bump on the front and back surfaces of a polyimide film or the like via an anisotropic conductive sheet with cushioning properties in the middle layer (isolated pad on the front and back surfaces Z via hole between isolated bumps) It is electrically connected to the pad electrode on the wafer via the bump.
  • the multilayer double-sided wiring board shown in Fig. 4 has the number of holes and the required through-holes so that the through holes are evenly drilled per chip corresponding to the chips formed on the wafer.
  • a plurality of pads are formed on the back side with a wider pitch and fewer pads than the pads on the front side corresponding to the pads formed on the wafer, but through holes are formed on the entire back side It is characteristic that it is done.
  • the pad electrode on the back surface connected through the through hole corresponding to each chip on the front side is basically formed near the upper part of the wafer chip, and conduction to the outside is connected almost vertically or by the shortest path.
  • This core substrate has conductive through holes throughout the substrate (a conductive member is inserted into the through hole so that the front and back surfaces of the substrate can be electrically connected so that the type of device under test can be changed). Are formed at predetermined positions and standardized. By doing so, it is possible to manufacture at low cost.
  • the through holes are formed radially, concentrically or in an array on the entire surface of the core substrate, all of which are filled with wires, fine metal particles, or conductive paste, solder metal, or metal plating. .
  • Board hole If there is a gap between 2003/010515 and its conductive material (for example, when filled with fine metal particles), the gap may be sealed with a non-conductive material such as resin.
  • the core substrate material must be heat-resistant because it is used at high temperatures, and it must have excellent positional accuracy at low and high temperatures. Therefore, the coefficient of thermal expansion must be 15 ppm or less. The difference in the coefficient of thermal expansion must be 13.82 ppm or less), preferably 10 ppm or less, more preferably 5 ppm or less.
  • Such materials include, for example, ceramics such as Si, alumina, SiC, and SiN, Pyrex, quartz glass, aluminoborosilicate glass, and Corning 705, 11 ⁇ Low-expansion glass such as Eighty-four, forty-five and forty-five.
  • the core substrate material does not necessarily need to be an insulating material.
  • the inside of the through hole should be insulated with oxide, resin, etc. Therefore, it is necessary to embed the conductive material inside the through hole.
  • an insulating substrate is not used, it is necessary to form wiring after insulating the surface, but conversely, by grounding the core substrate itself using the conductivity of the core substrate, A multilayer wiring board having excellent high-frequency characteristics and low-noise characteristics can be obtained. In this case, it goes without saying that the GRD of the wiring is conducted to the conductive portion inside the core substrate (the portion in which the conductive material is embedded without insulating the inside of the through hole).
  • the core substrate material is a photosensitive glass
  • the photosensitive glass substrate is exposed through a mask so that a latent image is formed in a portion where a large number of holes are formed, and the exposed portion is crystallized.
  • the crystallized region may be dissolved and removed to form a large number of holes to form a core substrate.
  • narrower holes small through-hole diameters
  • the anisotropic conductive sheet is formed so as to have conductivity in the vertical direction, and may have a structure in which wires are buried in an elastic body such as rubber in the vertical direction, and conductive particles such as metal may be used.
  • a structure embedded on one side or locally may be adopted.
  • an isolated copper pad is formed on the back surface of a polyimide film, and a metal pad formed by a photolithography method may be formed on the front surface thereof. But it may be The isolated pad on the PC leakage 003/010515 surface and the pad or bump on the front side are electrically connected through the inside of the film.
  • the structure of the flexible film may be reversed.
  • the bumped membrane has flexibility, but does not have to have cushioning.
  • the wafer contact board of Fabrication Example 2 consists of a multilayer double-sided wiring board and a small contact probe with spring properties (Fig. 5).
  • the pad electrode on the front side of the multilayer double-sided wiring board in the wafer contact node 20 is a small contact probe ( ⁇ material or structural) that has spring properties (material or structural). ) Can be connected to the pad electrode on the wafer via the above.
  • the wire material such as a needle having a paneling property is mechanically and electrically bonded to the pad electrode on the front side of the multilayer double-sided wiring board by soldering, heat fusion, or other methods.
  • the metal wires may be joined by applying a wire-to-bonding technique, or the joining may be carried out by using a technique such as a fine solder formed by applying a micromachine technique.
  • the pad electrode on the front side of the multilayer double-sided wiring board may be configured to be directly connected to the pad electrode on the wafer.
  • the pad electrode on the front side of the multilayer double-sided wiring board may be configured to be connected to the pad electrode on the wafer via an anisotropic member such as an anisotropic elastic sheet that can be repeatedly contacted.
  • a bump made of a soft material such as a conductive compressive material (eg, solder pole, Au, etc.) is formed on the pad electrode on the front side of the multilayer double-sided wiring board or on the pad electrode itself.
  • a contact one-time contact or a member that is not durable repeatedly is formed, or formed separately (sandwiched) and connected to the electrodes of the device under test, elements, etc. You can also. Other items are the same as those in the first example of the wafer-bound contact port.
  • the temperature is reduced to a temperature not lower than the softening temperature of the substrate and not higher than the temperature at which the shape of the substrate can be maintained.
  • the conductive member can be sufficiently fixed by fusion.
  • the conductive member can be firmly fixed by heat shrinkage due to cooling after heating.
  • sealing is performed without gaps by fusion and heat shrinkage, corrosion resistance and the like can be improved.
  • the conductive member is fixed by fusion and / or heat shrinkage, it can be fixed at a time even if the number of through holes is large. Further, by inserting the wire by vibration, extremely low cost of the wire inserting process can be achieved.
  • a large number of drills are arranged at regular intervals on one surface of a substrate to be processed, and ultrasonic waves are applied to the drills to form a large number of holes on the substrate to be processed. Since the holes are collectively formed, the cost of a through-hole forming substrate having a large number of holes can be realized. Therefore, an inexpensive double-sided wiring board can be realized using this inexpensive through-hole formed substrate.
  • a through-hole formed substrate with high precision, low thermal expansion, and excellent surface flatness, in which a large number of narrow and fine through holes with high positional accuracy are formed on the entire surface of the substrate, is inexpensive Can be realized.
  • a wafer-bound contact board for high-frequency applications can be realized.

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Abstract

A perforated substrate is obtained by drilling many holes (5) in a glass substrate (1) by vibrating a drilling jig having a plurality of drills (3). After filling each hole of the perforated substrate with a conductive member, the perforated substrate is subjected to a heat treatment at a temperature which is not lower than the softening temperature of the glass substrate and at which the substrate can keep its shape, so that the conductive member is fixed in each hole. A cooling treatment may be conducted after the heat treatment to thermally shrink the substrate. After fixing the conductive member in the perforated substrate, the surfaces of the perforated substrate are polished to expose the conductive member from the back and front sides of the substrate. A wired substrate can be obtained by providing each side of the polished substrate with a wiring layer.

Description

明 細 書 ホール形成基板及びその製造方法並びにウェハー括コンタクトボード 技術分野  Description Hole forming substrate, method of manufacturing the same, and wafer contact board

本発明は、 基板を形成された穴に導電部材を埋設したホール形成基板及びそ の製造方法等に関し、 特に、 基板を貫通するスルーホールを備えたスルーホー ル形成基板、 当該スルーホール形成基板を用いた両面配線基板、 及び、 両面配 線基板を用いて構成されたウェハー括 (フルウェハ) コンタクトボードの製造 方法に関する。 背景技術  The present invention relates to a hole-formed substrate in which a conductive member is buried in a hole formed with the substrate, a method of manufacturing the same, and the like, and more particularly, to a through-hole formed substrate having a through-hole penetrating the substrate, The present invention relates to a method for manufacturing a double-sided wiring board and a wafer-filled (full-wafer) contact board using the double-sided wiring board. Background art

一般に、 この種のスルーホール形成基板は、 半導体等における検査装置に用 いられている。 ここで、 半導体の検査工程を例にとると、 半導体の検査工程は 複数の段階で行われている。 通常、 ウェハ製造工程 (前工程) で製造されたゥ ェハは、 プローブカード検査後、 カット (ダイシング) され、 続いて、 パッケ —ジングされた後、 バーンィン検査及びファイナル検査が行われている。 また、 ウェハ状態で各種検査を行う方法が近年提案されている。 この場合、 ウェハ製造工程 (前工程) で製造されたウェハは、 プローブカード検査、 ゥェ ハレベルバーンイン (W L B I ) 検査、 及び、 ファイナル検査を受け、 フアイ ナル検査後、 ウェハはカットされている。  Generally, this type of through-hole forming substrate is used for an inspection device for semiconductors and the like. Here, taking the semiconductor inspection process as an example, the semiconductor inspection process is performed in a plurality of stages. Usually, wafers manufactured in the wafer manufacturing process (pre-process) are cut (diced) after probe card inspection, and then packaged, followed by burn-in inspection and final inspection. In recent years, methods for performing various inspections in a wafer state have been proposed. In this case, the wafer manufactured in the wafer manufacturing process (pre-process) undergoes probe card inspection, wafer level burn-in (WLBI) inspection, and final inspection. After the final inspection, the wafer is cut.

前述した検査のうち、 プロ一ブカード検査は、 一般に、 1チップもしくはマ ルチコンタクトプローブカード (6 4チップまで) を用いた D C ZA C検査で ある。 このようなプローブ力一ドには、 図 6 ( a ) 及び (b ) に示すように、 ガラスエポキシ樹脂からなる多層配線基板 6 1の中心部に開口 6 2を設け、 開 口 6 2の周囲から開口 6 2の中心に向かって触針 (プロ一ブ) 6 3を設け、 こ のプローブ 6 3をウェハ 4 0の 1チップ 4 1上の電極端子 4 2に接触させて検 查を行うタイプのプローブカードがある。  Of the above-mentioned tests, the probe card test is generally a DCZAC test using one chip or a multi-contact probe card (up to 64 chips). In such a probe force, as shown in FIGS. 6A and 6B, an opening 62 is provided at the center of a multilayer wiring board 61 made of glass epoxy resin, and the periphery of the opening 62 is provided. A probe (probe) 63 is provided toward the center of the opening 62 from the probe 62, and the probe 63 is brought into contact with the electrode terminal 42 on the one chip 41 of the wafer 40 to perform a test. There is a probe card.

また、 図 7に示すように、 ポリイミドなどからなるメンブレン 7 1の一方の 面にバンプ 7 2 (凸状の接点) を設けたバンプ付きメンブレン 7 0をコンタク ト部品として使用するタイプのメンブレンプローブカードも提案されている。 図 7において、 バンプ 7 2はメンブレン 7 1に形成したスル一ホールを 7 3介 して配線 7 4と導通され、 バンプ 7 2の形成部分は弹性材 7 5、 ピポット機構 7 6、 板パネ 7 7を介して押圧されコンタクトされる。 Also, as shown in FIG. 7, one of the membranes 71 made of polyimide or the like is used. A membrane probe card of a type using a membrane 70 with bumps provided with bumps 72 (convex contacts) on the surface as a contact component has also been proposed. In FIG. 7, the bumps 72 are electrically connected to the wiring 74 via the through holes 73 formed in the membrane 71, and the bumps 72 are formed on the conductive material 75, the pivot mechanism 76, the plate panel 7 It is pressed through 7 and contacted.

バーンイン検査は、 通常チップ単位で行う高温加速テストを指し、 電気的試 験を行う場合も多い。 ウェハー括でバーンイン検査を行う場合ウェハレベルパ ーンイン (WL B I ) という。 ウェハー括でバーンイン検査を行う場合、 ゥェ ハー括コンタクトボード (バーンインポ一ド) の実用化が必要である。  Burn-in inspection is a high-temperature accelerated test that is usually performed on a chip-by-chip basis, and often involves electrical testing. When performing burn-in inspection on a wafer, it is called wafer level burn-in (WL B I). When conducting burn-in inspection on wafers, it is necessary to commercialize wafer-contact contact boards (burn-in pads).

ファイナル検査は、 最後の電気的試験、 単なるオン 'オフテストからデバイ スの実動作周波数によるファンクションテスト等を行う。 具体的には、 ハンド ラ一を用いテス夕一ヘッドに、 インタ一ポーザ一を介して、 直接 1個ないし複 数個のベアチップ、 パッケージ品を押し付け、 測定する。 ウェハ状態で高周波 用プローブカード (6 4チップまで) を用い測定する場合もある。 発明の開示  The final inspection includes the final electrical test, a simple on-off test, and a function test at the actual operating frequency of the device. Specifically, one or more bare chips and packaged products are pressed directly against the test head using the handler via the interposer and measured. In some cases, measurement is performed using a high-frequency probe card (up to 64 chips) in the wafer state. Disclosure of the invention

上記したプローブカード検査工程においては現在のところ、 1チップから 6 4チップマルチ測定までであつたが、 これがウェハ全面一括コンタク卜が可能 であれば、 大幅な検査時間の短縮と検査コストの削減とが可能になる。  At present, the probe card inspection process described above covers from 1 chip to 64 chip multi-measurement, but if this is possible, it is possible to greatly reduce the inspection time and the cost Becomes possible.

同様に、高周波用途のウェハー括バーンインボードの実用化が可能であれば、 大幅な検査時間を短縮できると共に、 検査コストを大幅に削減できる。  Similarly, if the burn-in board for wafers for high frequency applications can be put to practical use, the inspection time can be greatly reduced, and the inspection cost can be significantly reduced.

高周波用途のウェハー括コンタクトポードを実現するには、 主としてウェハ 一括バーンイン検査用に開発されたコンタクトポードに関する技術を応用する ことが考えられる。 しかし、 かかる技術においては、 ウェハ上の全チップとの コンタクトを実現するため、 多層配線基板のコア基板としてガラス基板が用い られている。 このガラス基板を用いたコア基板は、 一方の表面だけに配線層を 形成した片側配線のため、 表面に形成される配線層が多くなつて、 微細加工を 必要とするためコストが高くなると云う欠点がある。 更に、 特性上も引出し電 極 (配線) 長が長くなり、 この結果、 抵抗値が増加すると共に、 インピーダン ス整合、 等長配線が困難になると云う欠点もある。 更に、 クロストークが増加 する等の問題があり、 高周波用途のウェハー括コンタクトボードは現状では作 製が困難である。 したがって、 ガラス基板をコア基板として用いた場合、 高周 波で検査を行うウェハー括プローブ検査用ポ一ドを実現することは困難である また、 前述したように、 配線層はガラス基板表面の片側 (ウェハ側) にだけ 形成されるため、 配線層上に抵抗、 コンデンサー、 ヒューズ等の素子を実装で きないと云う不都合な面もある。 これは、 素子には厚みがあるため、 ガラス基 板上に設けられたコンタクトバンプ等の電極が厚みのある素子の影響によって ウェハ上のパッドにコンタクト不可能となってしまうからである。 したがって、 ガラス基板を用いたプローブ用検查ポ一ドは高周波用途や D C検査用途には適 用できないと考えられている。 In order to realize a wafer contact port for high frequency applications, it is conceivable to apply the contact port technology developed mainly for batch burn-in inspection of wafers. However, in such a technique, a glass substrate is used as a core substrate of a multilayer wiring substrate in order to realize contact with all chips on a wafer. The core substrate using this glass substrate is a single-sided wiring in which a wiring layer is formed only on one surface, so the number of wiring layers formed on the surface increases, and fine processing is required, resulting in high costs. There is. In addition, the length of the extraction electrode (wiring) becomes longer in terms of characteristics, and as a result, the resistance value increases and the impedance increases. There is also a disadvantage that matching and equal length wiring become difficult. Furthermore, there are problems such as an increase in crosstalk, and it is currently difficult to manufacture a wafer-bound contact board for high-frequency applications. Therefore, when a glass substrate is used as a core substrate, it is difficult to realize a probe for wafer-bound probe inspection at a high frequency. As described above, the wiring layer is formed on one side of the glass substrate surface. Since it is formed only on the (wafer side), there is an inconvenience that elements such as resistors, capacitors, and fuses cannot be mounted on the wiring layer. This is because, since the device has a thickness, electrodes such as contact bumps provided on the glass substrate cannot contact the pad on the wafer due to the effect of the device having a large thickness. Therefore, it is considered that a probe detection probe using a glass substrate cannot be applied to high frequency applications or DC inspection applications.

ガラス基板上の素子を薄膜素子として配線層上に形成することも可能である が、 コストが非常に増加し、 現状では技術的困難度が高く、 全体的に技術的に できたにしても、 実用的なコストには遥かに及ばないものになってしまい、 現 実的なものではなくなつてしまうという問題がある。  Although it is possible to form a device on a glass substrate as a thin film device on a wiring layer, the cost is greatly increased and the technical difficulty is high at present. The problem is that the cost is far below the practical cost, and it is no longer practical.

上記のことから、 L S I検査、 M C M (マルチ ·チップ ·モジュール) 等の 配線基板等を検査する高周波用途のウェハー括コンタクトポ一ドとしては、 表 裏面を電気的に導通させたスルーホール (狭ピッチで細く高い位置精度のスル —ホールである必要あり) を基板全面に多数形成すると共に、 多層化した構造 を有するボードが必要になるものと考えられる。 しかしながら、 ガラス基板に 多数のスルーホールを形成した両面配線基板は未だ提案されていない。 これは、 ガラス基板を使用した場合、 精度、 熱膨張、 及び、 表面平坦性の点、 及び、 機 械的強度、 加工性の点で解決すべき問題が多いからである。  From the above, the wafer-bound contact port for high-frequency applications for inspecting wiring boards such as LSI inspections and MCMs (multi-chip modules) is a through-hole (narrow pitch) that electrically connects the front and back surfaces. It is considered necessary to form a large number of thin, high-precision through holes on the entire surface of the substrate and a board with a multilayered structure. However, a double-sided wiring board in which a large number of through holes are formed in a glass substrate has not yet been proposed. This is because when using a glass substrate, there are many problems to be solved in terms of accuracy, thermal expansion, and surface flatness, and mechanical strength and workability.

ここで、 ガラス基板を両面配線板を作製する方法としては、 ガラス基板にド リルで 1穴づっ加工する方法 (例えば、 実用新案登録第 3 0 8 4 4 5 2号公報) が考えられるが、 ドリルにより数千〜数万個の穴を形成した場合、 数十万〜数 百万円の費用がかかってしまい、 コスト的に到底実現不可能である。  Here, as a method for manufacturing a double-sided wiring board from a glass substrate, a method of drilling one hole in a glass substrate with a drill (for example, Japanese Utility Model Registration No. 30844542) can be considered. If thousands to tens of thousands of holes are formed by a drill, the cost of hundreds of thousands to several millions of yen is required, and it is impossible to realize the cost at all.

他方、 複数の線状の導電体を張った成形枠に溶融ガラスを流し込んだり、 或 は、 複数の線状の導電体を 2枚の板ガラスで挟み板ガラスを軟化又は流動化し たりして、 これらを固化して複数の線状の導電体を埋設したブロック体を形成 し、 このブロック体を切断して、 スルーホール形成基板を得る技術 (特開平 1 0— 1 9 0 1 9 0号公報) を利用することも考えられる しかしながら、 これ らの方法を細いワイヤーに適用した場合、 実際には、 ワイヤーが曲がったりし て、 位置が定まらず、 スルーホールの位置精度の確保が困難であるという問題 がある。 On the other hand, molten glass is poured into a molding frame with a plurality of linear conductors stretched, or a plurality of linear conductors are sandwiched between two sheet glasses to soften or fluidize the sheet glass. To form a block body in which a plurality of linear conductors are buried, and cut the block body to obtain a through-hole-formed substrate (Japanese Patent Laid-Open No. H10-19001). However, when these methods are applied to thin wires, the wires may actually bend and the position is not determined, and the position accuracy of the through-hole must be ensured. There is a problem that it is difficult.

また、 軟化したガラスにワイヤーを加圧揷入する方法も考えられるが、 細い ワイヤ一の場合、 曲がったりして、 位置が定まらないという問題があり、 さら に、 加圧挿入しても貫通せず、 相当量研磨してワイヤー下端を露出しなけれは ならず、 その研磨加工時間等がよけいにかかり、 コストが非常に増加する、 等 の欠点がある。  In addition, a method of pressurizing and inserting a wire into the softened glass is conceivable.However, in the case of a thin wire, there is a problem that the wire is bent and the position cannot be determined. However, the lower end of the wire must be exposed by polishing a considerable amount, and the polishing time is increased, and the cost is greatly increased.

さらに、 これらの方法では、 狭ピッチで細く高い位置精度のスルーホールを 基板全面に多数形成したスルーホール形成基板を作製しょうとした場合、 複数 の線状の導電体を張った成形枠の作製コスト及び張設コスト、 あるいはワイヤ 一の設置又は挿入コストが膨大となることから、 実際には、 狭ピッチで細く高 い位置精度のスルーホールを基板全面に多数形成したスルーホール形成基板を 作製することはコスト的に到底実現不可能である。  Furthermore, in these methods, when trying to manufacture a through-hole-formed substrate in which a large number of thin through holes with narrow pitch and high position accuracy are formed on the entire surface of the substrate, the cost of manufacturing a molding frame with a plurality of linear conductors stretched is reduced. In actuality, it is necessary to manufacture a through-hole-formed board in which a large number of thin and fine through-holes with high positional accuracy are formed on the entire surface of the board due to the huge cost of installing and inserting or inserting wires. Is not feasible at all in terms of cost.

このように、 狭ピッチで細く高い位置精度のスル一ホールを基板全面に多数 形成したスルーホール形成基板は、 要望されているが現状では全く実現されて おらず、 価格面及び精度面の双方を満たす製法の見通しは全く立っていないの が現状である。  As described above, a through-hole-formed substrate in which a large number of thin through holes with fine pitch and high position accuracy are formed on the entire surface of the substrate has been demanded, but has not been realized at present at all. Currently, there is no prospect of a satisfying manufacturing method.

このため、 実際にはウェハ全面コンタクトし、 ある程度以上の高周波伝送特 性を満足するためのウェハー括コン夕クトポードの作製は不可能であった。 本発明の目的は、 高周波用途のウェハー括コンタクトポ一ドを簡単に且つ安 価に実現できるホール形成基板、 及びスルーホール形成基板の製造方法を提供 することである。  For this reason, it has not been possible to actually fabricate a wafer consolidation contact port that makes contact with the entire surface of the wafer and satisfies a certain level of high-frequency transmission characteristics. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hole-formed substrate and a through-hole formed substrate, which can easily and inexpensively realize a wafer-bound contact port for high frequency use.

本発明の目的は、 多数の穴を迅速に形成できると共に、 形成された穴に正確 に導電部材を埋設できるホール形成基板、 及びスルーホール形成基板の製造方 法を提供することである。 本発明の更に他の目的は、 平坦性の優れたガラス基板によって構成され、 こ のため、配線層の断線等を防止できるスルーホール基板を提供することである。 本発明は以下の構成を有する。 An object of the present invention is to provide a hole forming substrate capable of rapidly forming a large number of holes and accurately embedding a conductive member in the formed holes, and a method of manufacturing a through hole forming substrate. Still another object of the present invention is to provide a through-hole substrate which is constituted by a glass substrate having excellent flatness and which can prevent disconnection of a wiring layer and the like. The present invention has the following configuration.

(構成 1 ) 多数の穴を形成したホール形成基板における各穴に、 導電部材を埋 設する工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導電 部材と共に熱処理して、 前記各穴に前記導電部材を固定する導電部材固定工程 とを有することを特徴とするホール形成基板の製造方法。  (Configuration 1) A step of burying a conductive member in each hole of the hole-formed substrate having a large number of holes formed therein, and after embedding the conductive member, heat-treating the hole-formed substrate together with the buried conductive member, A step of fixing the conductive member to each hole.

(構成 2 ) 構成 1において、 前記導電部材固定工程は、 前記ホール形成基板の 軟化点温度以上で、 基板形状が維持できる温度以下の前記ホール形成基板を加 熱することにより、 前記各穴に前記導電部材を融着する工程を含むことを特徴 とするホール形成基板の製造方法。  (Structure 2) In the structure 1, the conductive member fixing step may include heating the hole-forming substrate at a temperature equal to or higher than a softening point temperature of the hole-forming substrate and equal to or lower than a temperature at which a substrate shape can be maintained. A method for manufacturing a hole-formed substrate, comprising a step of fusing a conductive member.

(構成 3 ) 構成 1において、 前記導電部材固定工程は、 前記ホール形成基板の 軟化点温度以上で、 基板形状が維持できる温度以下の前記ホール形成基板を加 熱する工程と、 前記ホール形成基板の加熱後、 冷却することによって、 前記基 板を熱収縮させる工程とを含み、 これによつて、 前記導電部材を各穴に固定す ることを特徴とするホール形成基板の製造方法。  (Constitution 3) In the constitution 1, the conductive member fixing step may include a step of heating the hole formation substrate at a temperature higher than a softening point temperature of the hole formation substrate and lower than a temperature at which a substrate shape can be maintained; Cooling the substrate after heating to thereby thermally shrink the substrate, whereby the conductive member is fixed to each hole.

(構成 4 ) 構成 1において、 前記ホール形成基板はガラス材料からなり、 前記 導電部材固定工程では、 ガラスの粘度が 1 0 4〜 1 0 11ポアズとなるように、 前 記ホール形成基板を加熱することを特徴とするホール形成基板の製造方法。 In (Configuration 4) Configuration 1, the hole forming substrate is made of glass material, in the conductive member fixing step, so that the viscosity of the glass becomes 1 0 4 -1 0 11 poises, heat the pre-Symbol hole forming substrate A method for manufacturing a hole-formed substrate, comprising:

(構成 5 ) 構成 1において、 更に、 被加工基板と、 複数のドリルを植設したド リル治具を用意し、 当該被加工基板の一方の表面に、 前記複数のドリルを有す るドリル治具を接触した状態で、 前記ドリル治具を振動させることにより、 複 数の穴を一括して形成し、 前記ホール形成基板を形成する工程を有することを 特徴とするホール形成基板の製造方法。  (Structure 5) In the structure 1, a substrate to be processed and a drill jig in which a plurality of drills are implanted are prepared, and a drill jig having the plurality of drills is provided on one surface of the substrate to be processed. A method of manufacturing a hole-formed substrate, comprising: forming a plurality of holes at once by vibrating the drill jig in a state where the tools are in contact with each other, and forming the hole-formed substrate.

(構成 6 ) 構成 5において、 前記ドリル治具には超音波を与えて、 複数の穴を 一括形成することを特徴とするホール形成基板の製造方法。  (Structure 6) A method of manufacturing a hole-formed substrate according to structure 5, wherein ultrasonic waves are applied to the drill jig to form a plurality of holes at a time.

(構成 7 ) 構成 1において、 前記導電部材を埋設する工程は前記ホール形成基 板の各穴の径ょりも細い径の線状導電体を前記穴が形成された前記ホール形成 基板の表面に載せた後、 前記ホール基板に振動を与えることによって前記各穴 に前記導電体を挿入して埋設することを特徴とするホール形成基板の製造方法 C (Structure 7) In the structure 1, the step of burying the conductive member may include the step of embedding a linear conductor having a smaller diameter in each hole of the hole forming substrate on the surface of the hole forming substrate in which the hole is formed. After placing, each hole is given by applying vibration to the hole substrate. The method of manufacturing the hole forming substrate, characterized by embedding by inserting the conductor to C

(構成 8 ) 構成 1において、 前記導電部材を埋設する工程は前記導電部材とし て金属微粒子を用い、 前記金属微粒子に振動を与えることにより前記ホール形 成基板の各穴に充填し、 これによつて、 前記導電部材を埋設することを特徴と するホール形成基板の製造方法。 (Constitution 8) In the constitution 1, in the step of burying the conductive member, fine metal particles may be used as the conductive member, and the fine metal particles may be vibrated to fill each hole of the hole forming substrate. A method for manufacturing a hole-formed substrate, wherein the conductive member is embedded.

(構成 9 ) 多数の穴を形成したホール形成基板における各穴に、 導電部材を埋 設する工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導電 部材と共に熱処理して、 前記各穴に前記導電部材を固定する導電部材固定工程 と、 前記導電部材を固定されたホール形成基板を表面研磨して、 対向する両面 に前記導電部材を露出させる工程と、 を有することを特徴とするスル一ホール 形成基板の製造方法。  (Configuration 9) A step of burying a conductive member in each hole in the hole-formed substrate having a large number of holes formed therein, and after embedding the conductive member, heat-treating the hole-formed substrate together with the buried conductive member, A conductive member fixing step of fixing the conductive member in each hole; and a step of polishing the surface of the hole-formed substrate to which the conductive member is fixed to expose the conductive member on both opposing surfaces. A method for manufacturing a through hole forming substrate.

(構成 1 0 ) 多数の穴を形成したホール形成基板における各穴に、 導電部材を 埋設する工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導 電部材と共に熱処理して、 前記各穴に前記導電部材を固定する導電部材固定ェ 程と、 前記導電部材を固定されたホール形成基板を表面研磨して、 対向する両 面に前記導電部材を露出させる工程と、 及び、 前記両面のうち、 少なくとも一 方の面上に前記露出した前記導電部材に配線層を形成する工程とを有すること を特徴とする配線基板の製造方法。  (Configuration 10) A step of burying a conductive member in each hole in the hole-formed substrate having a large number of holes formed therein, and after burying the conductive member, heat-treating the hole-formed substrate together with the buried conductive member, A conductive member fixing step of fixing the conductive member to each of the holes, a step of polishing the surface of the hole-formed substrate to which the conductive member is fixed, and exposing the conductive member on both opposing surfaces; and Forming a wiring layer on the exposed conductive member on at least one of the two surfaces.

(構成 1 1 ) 構成 1 0記載に記載された配線基板を用いて構成されたことを特 徴とするウェハー括コンタクトボード。  (Structure 11) A wafer-bound contact board characterized by being configured using the wiring board described in Structure 10.

(構成 1 2 ) 複数の導電部材を複数の穴内に埋設した構成を備えた基板におい て、 前記基板はガラス材料によって形成され、 前記導電部材を埋設した表面は 最大高さ R m a Xで 2 m以下の表面粗さを有するように研磨されていること を特徴とする基板。  (Configuration 12) In a substrate having a configuration in which a plurality of conductive members are embedded in a plurality of holes, the substrate is formed of a glass material, and the surface on which the conductive members are embedded has a maximum height R max of 2 m. A substrate polished to have the following surface roughness.

構成 1記載の発明では、 多数の孔 (穴) (貫通孔でなくても可) を形成した ホール形成基板における各穴に、 導電部材を埋設後 (挿入又は充填した後) 、 ホール形成基板を埋設された導電部材と共に熱処理して、 各孔に前記導電部材 を固定する導電部材固定工程を有することを特徴とする。 さらに構成 2記載の 発明では、前記導電部材固定工程は、ホール形成基板の軟化温度以上であって、 基板形状が維持できる温度以下に前記基板を加熱することによって前記導電部 材を融着する工程を含むことを特徴としており、 融着により、 前記導電部材を 十分に固定することができる。 さらに構成 3記載の発明では、 ホール形成基板 の加熱後の冷却によって前記基板を熱収縮させ、 前記導電部材を固定する工程 を有し、 熱収縮により前記導電部材を強固に固定できる。 さらに、 融着及び熱 収縮により隙間なく密封されることになるので、 耐腐蝕性等を向上できる。 上述の通り、 本発明では、 融着及び Z又は熱収縮により前記導電部材を固定 する工程を有しているので、 スルーホールの数が多数の場合であっても、 一度 に固定可能できるため、 廉価 (安価) なスルーホール形成基板を実現できる。 また、 多数の穴 (貫通孔でなくても可) を形成したホール形成基板における 各穴に、 導電部材を揷入又は充填するので、 特開平 1 0— 1 9 0 1 9 0号公報 における、 線状の導電体 (ワイヤーなど) が細い時、 折れ曲がったり、 十分揷 入できない場合があるという問題や、 スルーホールの位置精度の問題がない。 導電部材としては、 線状の導電体 (例えばワイヤ一など) 、 金属粒子、 その 他の導電性材料等が挙げられる。 ワイヤーの場合は断線の恐れがない。 In the invention described in the configuration 1, after the conductive member is buried (after insertion or filling) in each hole in the hole forming substrate in which a large number of holes (holes) (not necessarily through holes) are formed, the hole forming substrate is A conductive member fixing step of fixing the conductive member in each hole by heat treatment together with the embedded conductive member. Further, in the invention according to Configuration 2, the conductive member fixing step is performed at a temperature equal to or higher than a softening temperature of the hole-forming substrate, The method includes a step of fusing the conductive member by heating the substrate to a temperature at which the substrate shape can be maintained, and the conductive member can be sufficiently fixed by fusing. The invention according to the third aspect further includes a step of heat-shrinking the substrate by cooling the hole-formed substrate after heating, and fixing the conductive member. The conductive member can be firmly fixed by the heat shrinkage. In addition, since sealing is performed without gaps by fusion and heat shrinkage, corrosion resistance and the like can be improved. As described above, the present invention includes the step of fixing the conductive member by fusion and Z or heat shrinkage, so that even if the number of through holes is large, it can be fixed at once, An inexpensive (low-priced) through-hole forming substrate can be realized. Further, since a conductive member is inserted or filled into each hole in the hole-formed substrate in which a large number of holes (not necessarily through-holes) are formed, Japanese Patent Application Laid-Open No. When the linear conductor (wire, etc.) is thin, there is no problem that it may bend or not be inserted sufficiently, and there is no problem with the positioning accuracy of the through hole. Examples of the conductive member include a linear conductor (for example, a wire), metal particles, and other conductive materials. In the case of wire, there is no risk of disconnection.

融着ゃ熱収縮時に、 線状の導電体の上端部等を加圧する工程を付加すること が好ましい。線状の導電体が完全にスルーホール内に挿入され、不良をなくし、 更に研磨量を少なくしてコストを低減させるためである。  It is preferable to add a step of pressing the upper end portion or the like of the linear conductor during fusion and heat shrinkage. This is because the linear conductor is completely inserted into the through hole, eliminating defects and further reducing the amount of polishing to reduce cost.

構成 4記載の発明では、 前記ホール形成基板をガラス材料とし、 前記導電部 材固定工程でのガラスの粘度が 1 0 4〜 1 0 11ポアズとなるようにガラス材料を 加熱する。 1 0 4ポアズはガラスの作業温度 (成形温度) 付近の温度を意味し、 これより粘性が低い場合、 ガラスが軟化しすぎて基板形状が保てない。 また、 1 0 11ポアズはガラスの屈伏点付近の粘度を意味し、 これより粘度が高い場合、 ガラスの成形が困難である。 好ましくは、 ガラスの粘性が 1 0 5〜1 0 8ポアズ となるように加熱することが好ましい。 In the invention of structure 4 wherein said hole forming substrate as the glass material, the viscosity of the glass at the conductive member fixing step heats the glass material so that 1 0 4 -1 0 11 poises. 1 0 4 poises means working temperature temperature (molding temperature) around the glass, when it from the low viscosity, not keep the board shaped glass is excessively softened. Further, 1 0 11 poises means the viscosity near the yield point of the glass, when it than the viscosity is high, it is difficult to mold the glass. Preferably, it is preferable to heat such that the glass viscosity becomes 1 0 5-1 0 8 poises.

構成 5記載の発明では、前記ホール形成基板は、被加工基板の一方の表面に、 複数のドリルを有するドリル治具を接触した状態で、 前記ドリル治具を振動さ せることによって、 複数の穴を一括して形成しているので、 1本刃のドリルや 1本刃の超音波ドリルを使用し順次孔を開けて行く場合に比べ、 多数の穴を一 括してあけるため、 多数の穴を有するホール形成基板の廉価を実現できる。 しかも、 構成 6によれば、 前記ドリル治具には超音波を与えて、 複数の穴を 一括して形成することで、 狭ピッチ (例えば 3 mmピッチ以下) で細い (例え ばスルーホール径が 0 . 5 πιπι φ以下) の穴を基板全面に多数形成した基板を 得ることができることが判った。 つまり、 狭ピッチで細かく多数の穴を形成し ても破損が全くないことが判った。 これは、 全ての穴にドリル刃が挿入された 状態で加工が行われており均一に力が作用するためであると考えられる。 既に 形成された穴の近くに狭ピッチで新規な穴をドリル加工する場合は破損の恐れ がある。 In the invention according to the fifth aspect, the hole-forming substrate may include a plurality of holes formed by vibrating the drill jig in a state where the drill jig having the plurality of drills is in contact with one surface of the substrate to be processed. Are formed all at once, so a larger number of holes are required than when using a single-blade drill or a single-blade ultrasonic drill to drill holes sequentially. Since the holes are formed together, the cost of a hole-formed substrate having a large number of holes can be realized. In addition, according to Configuration 6, by applying ultrasonic waves to the drill jig to form a plurality of holes at once, the drill jig has a narrow pitch (for example, 3 mm pitch or less) and is thin (for example, the through hole diameter is small). It was found that a substrate having a large number of holes (0.5 πιπιφ or less) formed on the entire surface of the substrate could be obtained. In other words, it was found that even if many holes were finely formed at a narrow pitch, there was no breakage at all. This is thought to be due to the fact that the processing is performed with the drill bit inserted in all the holes, and the force acts uniformly. Drilling a new hole at a narrow pitch near an already formed hole may cause damage.

この超音波を印加するドリルは、 被加工基板に対し安定的に自立可能な数及 び配置の多数のドリルの刃を基板の一方の面に形成したものであることが好ま しい。 このドリルが安定的に自立可能でないと、 被加工基板に対しドリルを水 平に保つことが難しく、 垂直かつ穴径精度の高い穴加工が実現できないからで ある。  It is preferable that the drill for applying the ultrasonic wave is formed by forming a large number of drill blades on one surface of the substrate, the number and the number of drills being stably self-supporting with respect to the substrate to be processed. If the drill is not stable and self-supporting, it is difficult to keep the drill horizontal with respect to the substrate to be processed, and it is not possible to realize vertical drilling with high hole diameter accuracy.

また、 この超音波を印加するドリルは、 その自重によってドリルの刃が屈曲 しない数及び配置の多数のドリルの刃を基板の一方の面に形成したものである ことが好ましい。 ドリルの自重によってドリルの刃が屈曲してしまうと、 垂直 かつ穴径精度の高い穴加工が実現できないからである。  Further, it is preferable that the drill to which the ultrasonic wave is applied has a large number of drill blades formed and arranged on one surface of the substrate so that the drill blades are not bent by their own weight. If the drill blade is bent by the weight of the drill, drilling with vertical and high hole diameter accuracy cannot be realized.

具体的には、 ドリルの刃の数は、 5 0以上が好ましく、 1 0 0以上がさらに 好ましい。 例えば、 ウェハー括コンタクトボード用としては、 ドリルの刃の数 は、 穴加工回数の低減及びドリルの作製コストの観点から、 5 0 0以上が好ま しく、 1 0 0 0以上がさらに好ましい。  Specifically, the number of drill bits is preferably 50 or more, more preferably 100 or more. For example, for a wafer contact board, the number of drill blades is preferably 500 or more, and more preferably 100 or more, from the viewpoint of reducing the number of drilling times and the cost of manufacturing a drill.

なお、 ドリルによって形成される穴は被加工基板を貫通したスル一ホールで あっても、 貫通しない穴であっても良い。 貫通させない場合は、 穴に揷入又は 充填する線状の導電体 (例えば、 ワイヤーなど) や金属粒子がボトム開口部よ り抜け落ちることがないので、 抜け落ち防止策が不要である。 貫通させない場 合は、 研磨により非貫通部を除去して線状の導電体 (例えば、 ワイヤーなど) や金属粒子を露出させる。 貫通させる場合は、 ボトム開口部の径は線状の導電 体や金属粒子径よりも小さくし、 線状の導電体や金属粒子がボトム開口部より 抜け落ちないようにするか、 粘性が高いペースト状のものに線状の導電体や金 属粒子を混在させ穴に流し込む方法を採用する等の工夫をすることができる。 勿論、 貫通孔形成後に一側を、 シート材、 高粘度液体コート剤等で塞いでおい ても良い。 The hole formed by the drill may be a through hole that penetrates the substrate to be processed or a hole that does not penetrate. If it does not penetrate, no linear conductor (eg, wire) or metal particles that enter or fill the hole will fall out of the bottom opening, so no measures to prevent falling off are necessary. If not penetrated, the non-penetrated part is removed by polishing to expose the linear conductor (for example, wire) and metal particles. When penetrating, the diameter of the bottom opening is smaller than the diameter of the linear conductor or metal particle, and the diameter of the linear conductor or metal particle is smaller than that of the bottom opening. It is possible to adopt a method of preventing falling off or adopting a method of mixing a linear conductor or metal particles into a paste having high viscosity and pouring the mixture into a hole. Of course, one side may be covered with a sheet material, a high-viscosity liquid coating agent or the like after the formation of the through holes.

尚、 ドリルに超音波を印加して多数の穴を形成する前の被加工基板の表面粗 さを、 最大高さ Rm a xで 2 m以下とすることにより、 超音波を印加して多 数の穴を一括して形成する際に、 被加工基板表面に存在するクラックやキズな どから発生するヒビゃ割れ (破損) の発生を効果的に低減することができる。 好ましい表面粗さは、算術平均粗さ R aで 0 . 2 m以下、 さらに好ましくは、 R aで 0 . 1 m以下が望ましい。 尚、 上述の算術平均粗さ R aは J I S B 6 0 1 - 1 9 9 4で定義されている測定方法に基づき測定したものである。 また、 ドリルに超音波を印加して多数の穴を形成する前の被加工基板の表面 を上述の表面粗さにするために、 研削加工や研磨加工を施すことにより、 被加 ェ基板表面に存在するクラックゃキズを極力なくすことができると共に、 超音 波を印加して多数の穴を一括して形成する際に、 効果的にヒビゃ割れ (破損) を効果的に低減することができると云う利点がある。 尚、 超音波としては、 数 k H z〜数百 k H zの周波数を有する超音波を使用できる。  By applying ultrasonic waves to the drill and setting the surface roughness of the substrate before forming a large number of holes to 2 m or less at the maximum height Rmax, a large number of ultrasonic waves can be applied. When holes are collectively formed, the occurrence of cracks (breakage) due to cracks and scratches on the surface of the substrate to be processed can be effectively reduced. The preferred surface roughness is an arithmetic average roughness Ra of 0.2 m or less, more preferably, a Ra of 0.1 m or less. The arithmetic average roughness Ra described above is measured based on the measurement method defined in JIS B601-1994. In addition, in order to make the surface of the substrate before forming a large number of holes by applying ultrasonic waves to the drill into the above-described surface roughness, the surface of the substrate to be processed is ground or polished. Existing cracks and scratches can be minimized, and cracks (breakage) can be effectively reduced when a large number of holes are formed at once by applying ultrasonic waves. There is an advantage called. In addition, as an ultrasonic wave, an ultrasonic wave having a frequency of several kHz to several hundred kHz can be used.

構成 7や構成 8記載の発明のように、 振動で線状の導電体 (例えば、 ワイヤ —など) (構成 7 ) や金属微粒子 (構成 8 ) をホール形成基板の各穴に挿入す ると、 全ての穴に線状の導電体や金属微粒子が自動的に挿入されることが判つ た。 この場合の振動は数 H zから数十 H zである。 したがって、 線状の導電体 や金属微粒子の挿入工程の極端な低コスト化が可能となることが判った。特に、 線状の導電体や金属微粒子を挿入するスルーホールの数が多数である場合、 本 構成の効果は絶大である。 スル一ホールの数が多くなるにしたがって、 1穴毎 に位置合わせを行い線状の導電体や金属微粒子を挿入する方法では、 コストが 膨大となり、 経済性の面で実現不可能である。  As in the inventions described in Configurations 7 and 8, when a linear conductor (for example, a wire) (vibration 7) or fine metal particles (configuration 8) is inserted into each hole of the hole forming substrate by vibration, It was found that linear conductors and fine metal particles were automatically inserted into all holes. The vibration in this case is several Hz to several tens Hz. Therefore, it was found that the cost of the step of inserting the linear conductor or metal fine particles can be extremely reduced. In particular, when the number of through holes into which linear conductors or metal fine particles are inserted is large, the effect of this configuration is enormous. As the number of through holes increases, the method of aligning each hole and inserting linear conductors or fine metal particles increases the cost and is not feasible in terms of economy.

全ての穴に線状の導電体が自動的にスムーズに挿入される観点から、 線状の 導電体の径は、 穴径の 9 0 %以下、 さらには 8 5 %以下、 さらには 8 0 %以下 とすることが好ましい。 同様に、 線状の導電体の長さは、 穴の深さと同程度、 さらには穴の深さより も若干長い程度、 さらには穴の深さの 1 . 1倍程度とすることが好ましい。 線状の導電体の材質は、 全ての穴に線状の導電体が自動的にスムーズに挿入 される材質であることが好ましい。 From the viewpoint that the linear conductor is automatically and smoothly inserted into all holes, the diameter of the linear conductor is 90% or less of the hole diameter, further 85% or less, and further 80%. It is preferable to set the following. Similarly, the length of the linear conductor is preferably about the same as the depth of the hole, more preferably slightly longer than the depth of the hole, and more preferably about 1.1 times the depth of the hole. The material of the linear conductor is preferably a material that allows the linear conductor to be automatically and smoothly inserted into all the holes.

なお、 振動でなく、 数 k H z以上の周波数を有する超音波によって振動させ ても線状の導電体を揷入することも可能である。 確実性の観点から超音波振動 が好ましいことが判明した。  Note that it is also possible to insert a linear conductor by vibrating with ultrasonic waves having a frequency of several kHz or more instead of vibration. It has been found that ultrasonic vibration is preferable from the viewpoint of reliability.

また、 構成 9記載の発明のように、 上記構成 1〜8において得られたホール 形成基板を用い、 前記導電部材を固定されたホール形成基板を表面研磨して、 対向する両面に前記導電部材を露出させることで、 前記基板の表裏面を導電部 材で導通したスルーホール形成基板が得られる。  Further, as in the invention according to the ninth aspect, using the hole-forming substrate obtained in any one of the first to eighth aspects, the surface of the hole-forming substrate to which the conductive member is fixed is polished, and the conductive member is provided on both opposed surfaces. By exposing, a through-hole-formed substrate in which the front and back surfaces of the substrate are electrically connected by the conductive member is obtained.

なお、 上記構成 9において、 前記導電部材を融着及び/又は固定した後、 前 記基板の片面又は両面を研磨する工程を有することによって、 導電部材の金属 面を出すことができ、 酸化被膜の問題等を回避できる。 また、 研磨によって、 線状の導電体の端部 (穴からはみ出た部分) を除去することで、 線状の導電体 の長さを調整する等の煩雑な作業が不要となる。 また、 研磨によって、 基板の 平坦性付与又は平坦性向上が可能となる。 さらに研磨により基板表面と導電部 材の端面とを面一にすると、 他の方法により面一にした場合と比べ、 面一の'レ ベルが高いので、 配線層の形成や、 配線層との接続性の点で有利である。  In addition, in the above-mentioned configuration 9, after the conductive member is fused and / or fixed, a step of polishing one or both surfaces of the substrate is provided, whereby the metal surface of the conductive member can be exposed, and the oxide film can be formed. Problems can be avoided. Also, by removing the ends (portions protruding from the holes) of the linear conductor by polishing, complicated work such as adjusting the length of the linear conductor is not required. In addition, the polishing can impart or improve the flatness of the substrate. Furthermore, if the surface of the substrate and the end surface of the conductive member are made flush with each other by polishing, the level of the flush is higher than in the case of flushing with other methods. This is advantageous in terms of connectivity.

研磨量は片面で、 製造コストの観点から l mm以下、 さらには 0 . 5 mm以 下が好ましい。 研磨後の基板表面は最大高さ R m a Xで 2 以下、 好ましく は、 0 . 2 m以下である。 このように、 平坦な表面を有する基板、 特に、 ガラ ス基板は、 その表面に厚さの薄い配線層を形成しても配線層に断線等が生じな いと言う利点がある。  The polishing amount on one side is preferably 1 mm or less, more preferably 0.5 mm or less from the viewpoint of manufacturing cost. The substrate surface after polishing has a maximum height R max of 2 or less, preferably 0.2 m or less. As described above, a substrate having a flat surface, particularly a glass substrate, has an advantage that even if a thin wiring layer is formed on the surface, disconnection or the like does not occur in the wiring layer.

構成 1 0記載の発明では、構成 9記載の廉価なスルーホール形成基板を用い、 少なくとも一方の面上に露出した導電部材に配線層を形成することで、 廉価な 配線基板を実現できる。  In the invention according to the tenth aspect, an inexpensive wiring board can be realized by using the inexpensive through-hole formation substrate according to the ninth aspect and forming a wiring layer on the conductive member exposed on at least one surface.

構成 1 0において、 配線層は単層又は多層とすることができる。 また、 配線 層は、 何れか一方の面、 または両方の面に形成することができる。 配線層を両 方の面に形成した場合は、 両面配線基板となる。 配線層には、 配線や電極が含 まれる。 配線層の形成には、 フォトリソグラフィ一法、 ビル'トアップ法 (多層 の場合) 、 プリント法その他公知の配線又は多層配線技術が用いられる。 構成 1 0記載の配線基板は、 スルーホールの数が多数 (例えば 2 0 0以上) の場合、 ウェハー括コンタクトボード用の多層配線基板として特に適する。 構成 1 1記載の発明のウェハー括コンタクトボードでは、 両面配線基板の母 材であるスルーホール形成基板が低熱膨張で、 高い表面平坦性を有する必要が ある。 ウェハと全面コンタクトし、 導通 ·検査するためである。 両面配線基板 の母材であるスルーホール形成基板の熱膨張率は 1 5 p p m以下であることが 好ましい。 両面配線基板の母材であるスルーホール形成基板全体に亘る表面平 坦性は 4 0 m以下であることが好ましい。 In the configuration 10, the wiring layer can be a single layer or a multilayer. Further, the wiring layer can be formed on any one surface or both surfaces. Both wiring layers If it is formed on one side, it will be a double-sided wiring board. The wiring layer includes wiring and electrodes. For forming the wiring layer, a photolithography method, a built-up method (in the case of a multilayer), a printing method, or other known wiring or multilayer wiring technology is used. The wiring board described in the configuration 10 is particularly suitable as a multilayer wiring board for a wafer-bound contact board when the number of through holes is large (for example, 200 or more). In the wafer-bound contact board according to the invention described in Configuration 11, the through-hole-forming substrate, which is the base material of the double-sided wiring substrate, needs to have low thermal expansion and high surface flatness. This is for contacting the whole surface with the wafer and conducting and inspecting. It is preferable that the through-hole-forming substrate, which is the base material of the double-sided wiring substrate, has a coefficient of thermal expansion of 15 ppm or less. It is preferable that the surface flatness over the entire through-hole forming substrate, which is the base material of the double-sided wiring substrate, is 40 m or less.

本発明のウェハー括コンタクトボードでは、 両面配線基板の母材として、 狭 ピッチで細いスルーホールを高精度で全面に多数形成したスルーホール形成基 板を用いる必要がある。 ある程度以上の伝送特性 (プロ一ブ検査や特定のバ一 ンイン検査に必要な高周波伝送特性) を満足させるためである。  In the wafer contact board of the present invention, it is necessary to use, as a base material of the double-sided wiring board, a through-hole forming substrate in which a large number of narrow through holes with a narrow pitch are formed with high precision over the entire surface. This is in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for probe inspection and specific burn-in inspection).

本発明では、 半導体素子等の被検査電極との対応を図る目的で狭ピッチで細 いスルーホールを基板全面に多数形成する。  In the present invention, a large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate in order to correspond to an electrode to be inspected such as a semiconductor element.

本発明では、 ゥェ八全面コンタクトし、 ある程度以上の伝送特性 (プローブ 検查ゃ特定のバーンィン検査に必要な高周波伝送特性) を満足するためのゥェ ハー括コンタクトボードの作製を可能とする目的で狭ピッチで細いスルーホー ルを基板全面に多数形成する。  An object of the present invention is to make it possible to manufacture a wafer-contacted contact board in order to satisfy a certain level of transmission characteristics (high-frequency transmission characteristics required for a burn-in inspection specific to probe inspection) by contacting the entire surface. A large number of narrow through holes with a narrow pitch are formed on the entire surface of the substrate.

本発明では、 ウェハー括コンタクトポ一ドの主要部を構成する両面配線基板 (多層両面配線基板が好ましい) における表側の各チップに対応して表側に形 成された電極とスル一ホールを介して導通している裏面のパッド電極は、 基本 的にウェハ上のチップの上部近傍に形成され外部への導通はほぼ垂直に若しく は最短経路で結ばれる構造とすることが好ましい。 つまり、 裏面パッドは各チ ップ上の電極に対し最短位置に形成することが好ましい。  According to the present invention, through a through hole and an electrode formed on the front side corresponding to each chip on the front side of a double-sided wiring board (preferably a multilayer double-sided wiring board) constituting the main part of the wafer contact pad. It is preferable that the conductive pad electrode on the back surface is basically formed near the upper part of the chip on the wafer and has a structure in which conduction to the outside is connected almost vertically or by the shortest path. That is, the back pad is preferably formed at the shortest position with respect to the electrode on each chip.

本発明では、 前記スルーホール形成基板は、 被検査物デバイスの種類が変わ つても対応できるように、 基板全面に導電性スルーホールが標準化された所定 の位置に形成されていることが好ましい。 このようにすることによりコスト的 に安価に製造できる。 例えば、 スル一ホールは基板全面に放射状に若しくは同 心円状若しくはアレー状に形成できる。 In the present invention, the through-hole-formed substrate may have a standardized conductive through-hole on the entire surface of the substrate so that the type of the device under test can be changed. Is preferably formed at the position. By doing so, it can be manufactured at a low cost. For example, through holes can be formed radially, concentrically, or in an array over the entire surface of the substrate.

ウェハー括コンタクトポ一ドとしては、 基板サイズは少なくともウェハサイ ズ以上であることが好ましい。 基板の厚さは、 機械的耐久性が得られ、 正確に スルーホールを形成するために、 2〜7 mm程度であることが好ましい。 スル 一ホールの数は基板に実装される抵抗、 コンデンサ等のチップ素子の数に関連 して定められ、 チップ素子の数 X 2 (例えば 1 0 0 0以上) であることが好ま しい。 スルーホールのピッチは、 スルーホール間の機械的耐久性が得られる範 囲で 3 mmピッチ以下、 スル一ホールの径は 0 . 1〜0 . 5 πιπι φであること が好ましい。  It is preferable that the substrate size of the wafer-contacting contact port is at least as large as the wafer size. The thickness of the substrate is preferably about 2 to 7 mm in order to obtain mechanical durability and accurately form a through-hole. The number of through holes is determined in relation to the number of chip elements such as resistors and capacitors mounted on the substrate, and is preferably the number of chip elements X 2 (for example, 100 or more). It is preferable that the pitch of the through-holes is 3 mm or less as long as the mechanical durability between the through-holes can be obtained, and the diameter of the through-hole is 0.1 to 0.5 πιπιφ.

ウェハー括コンタクトポ一ドには、 ウェハー括バーンイン検査用ボード、 ゥ ェハ一括プローブ検査用ボード、 ウェハー括ファイナル検査用ポードが含まれ る。 '  The wafer package contact port includes a wafer package burn-in inspection board, a wafer batch probe inspection board, and a wafer package final inspection port. '

なお、 このような基板全面に多数のスルーホールを形成したスルーホール形 成基板を用いて作製したウェハ一括コンタクトポードは、 従来得られていなか つた。 つまり、 基板全面に多数のスルーホールを形成したスルーホール形成基 板を用いていることが特徴である。  Heretofore, a wafer batch contact port manufactured using such a through-hole formed substrate having a large number of through-holes formed on the entire surface of the substrate has not been obtained. In other words, it is characterized in that a through-hole forming substrate having a large number of through-holes formed on the entire surface of the substrate is used.

また、 構成 1 2記載の発明のように、 複数の導電部材を複数の穴内に埋設し た構成を備えた基板において、 前記基板はガラス材料によって形成され、 前記 導電部材を埋設した表面は最大高さ R m a Xで 2 ^ m以下の表面粗さを有する ように研磨されている基板とすることで、 基板の表面上に形成する配線層の断 線等を防止できる。 特に配線層の膜厚が、 配線層としての機能を有する膜厚以 上であって 5 m以下と薄い場合に、 構成 1 2の基板は特に有効である。 図面の簡単な説明  Further, as in the invention according to Configuration 12, in a substrate having a configuration in which a plurality of conductive members are embedded in a plurality of holes, the substrate is formed of a glass material, and a surface in which the conductive member is embedded has a maximum height. By using a substrate polished so as to have a surface roughness of 2 μm or less at R max, disconnection of a wiring layer formed on the surface of the substrate can be prevented. In particular, when the thickness of the wiring layer is equal to or greater than the thickness having a function as the wiring layer and is as small as 5 m or less, the substrate of Configuration 12 is particularly effective. BRIEF DESCRIPTION OF THE FIGURES

図 1 ( 1 ) 〜 (7 ) は本発明の一実施の形態に係るスル一ホール形成基板の 製造方法を工程順に示す模式図である。  1 (1) to 1 (7) are schematic views showing a method of manufacturing a through-hole formed substrate according to an embodiment of the present invention in the order of steps.

図 2 ( 1 ) 〜 (7 ) は本発明の他の実施の形態に係るスルーホール形成基板 の製造方法を工程順に示す模式図である。 2 (1) to 2 (7) show through-hole-formed substrates according to another embodiment of the present invention. FIG. 4 is a schematic view showing a manufacturing method of the present invention in the order of steps.

図 3は本発明の実施の形態に使用される低膨張ガラスの粘性カーブを示すグ ラフである。  FIG. 3 is a graph showing a viscosity curve of the low expansion glass used in the embodiment of the present invention.

図 4は本発明に係るスル一ホ一ル形成基板を含むウェハー括コンタクトポー ドを説明する模式図である。  FIG. 4 is a schematic view illustrating a wafer contact port including a through hole forming substrate according to the present invention.

図 5は本発明に係るスル一ホール形成基板を含む他のウェハー括コンタクト ポ一ドを説明する模式図である。  FIG. 5 is a schematic view for explaining another wafer contact contact including the through hole forming substrate according to the present invention.

図 6 (a) 及び (b) はプロ一ブカードの一例を説明する平面図及び断面図 である。  6 (a) and 6 (b) are a plan view and a cross-sectional view illustrating an example of a probe card.

図 7は他のプローブカードを説明するための部分断面図である。 発明を実施するための最良の形態  FIG. 7 is a partial cross-sectional view for explaining another probe card. BEST MODE FOR CARRYING OUT THE INVENTION

スルーホール形成基板の作製方法 A  Method for manufacturing through-hole-formed substrate A

工程 (1) 低膨張ガラス基板の用意  Process (1) Preparation of low expansion glass substrate

図 1 (1) に示すように、 例えば HOYA製低膨張ガラス基板 NA45 (サ ィズ 23 OmmX 230mm、 5 mm厚) の低膨張ガラス基板 1を用意する。  As shown in FIG. 1 (1), for example, a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared.

(尚、 この低膨張ガラス基板 1の表面の表面粗さは R aで、 0. 2 ^m以下で あった。 表面粗さは、 触針式表面粗さ計 (商品名テンコール Ρ 2 :テンコール インスツルメント社製) で測定。 )  (The surface roughness of the low-expansion glass substrate 1 was Ra, which was 0.2 μm or less. The surface roughness was measured using a stylus type surface roughness meter (trade name: Tencor Ρ2: Tencor Measured by Instruments).

尚、 この低膨張ガラス基板 ΝΑ45の粘性カーブ (温度 V s粘度(log)) は 図 3の特性を有している。 この粘性力一ブから、 ガラスの粘性が 1 04〜 1 011 ポアズとなる温度範囲は 710°C〜1 17 5 °Cであることがわかる。 The viscosity curve (temperature vs viscosity (log)) of the low expansion glass substrate # 45 has the characteristics shown in FIG. This viscous force one blanking, the temperature range in which the viscosity of the glass becomes 1 0 4 -1 0 11 poises is found to be 710 ° C~1 17 5 ° C.

工程 (2) 超音波ドリル加工  Process (2) Ultrasonic drilling

平らなサイズ 1 0 5mmX 1 05mm、 3 mm厚のステンレス基板 2に、 ピ ツチ 3mm、 径 0. 5mmのねじ穴をアレー状に 3 X 30 =計 900個あけ、 そこに、 M0. 5のねじ (長さ 8 mm) をすベて挿入してドリル 3を備えたド リル治具を形成する。尚、 ドリル治具 3を形成するドリル 3はステンレス、鉄、 タングステン等によって形成されている。  Flat size 1 0 5 mm X 105 mm, 3 mm thick stainless steel substrate 2, 3 x 30 = 900 holes drilled in a 3 x 30 screw holes with a pitch of 3 mm and a diameter of 0.5 mm. (8 mm in length) is inserted to form a drill jig with drill 3. The drill 3 forming the drill jig 3 is formed of stainless steel, iron, tungsten, or the like.

剣山状のドリル 3をドリル治具を図 1 (2) に示すように、 ガラス基板 1上 3010515 に載せた状態で、 研磨剤 4を水にといて、 ガラス基板 1とドリル 3の間に供給 しながら、 38 kH zの超音波により加工を施す (図 1 (2) ) 。 Insert the drill 3 in a sword mountain shape on the glass substrate 1 as shown in Fig. 1 (2). While placed on the 3010515, the abrasive 4 is immersed in water and processed by ultrasonic waves at 38 kHz while supplying between the glass substrate 1 and the drill 3 (Fig. 1 (2)).

工程 (3) 超音波加工により、 ドリル 3とほぼ同じ径の穴 5を深さ 4. 5 m m穿つ。 実際には、 ステンレス板の位置をずらせ 4回加工し、 900 X 4=計 3600個の穴 5を正確に、 アレー状に穿つ。 その後、 研磨剤を洗い流す (図 1 (3) ) 。  Process (3) Drill a hole 5 with the same diameter as the drill 3 to a depth of 4.5 mm by ultrasonic machining. Actually, the position of the stainless steel plate is shifted and processed four times, and 900 x 4 = a total of 3600 holes 5 are accurately drilled in an array. After that, the abrasive is washed away (Fig. 1 (3)).

工程 (4) 線状の導電体 (ワイヤ一) 挿入  Process (4) Insert a linear conductor (one wire)

図 1 (4) に示すように、 ガラス基板 1上に多数のタングステン製ワイヤー 6 (直径 0. 4 ΦΧ長さ 5. 5mm) をのせ、 図 1 (2) と同様な超音波振動 を与えると、 穴の中にワイヤー 6が自動的に一括挿入される。  As shown in Fig. 1 (4), a number of tungsten wires 6 (diameter 0.4 ΦΧ length 5.5 mm) are placed on the glass substrate 1 and subjected to the same ultrasonic vibration as in Fig. 1 (2). The wire 6 is automatically inserted into the hole at once.

なお、 タングステンワイヤ一を用いると、 全ての穴にワイヤ一 6が自動的に スムーズに挿入でき、 さらに回収及び再利用可能であるので環境対応面でも優 れている。  If tungsten wire is used, the wire 6 can be automatically and smoothly inserted into all holes, and it can be recovered and reused, so that it is also environmentally friendly.

工程 (5) ガラス基板の加熱によるワイヤーの融着  Process (5) Wire fusion by heating glass substrate

ワイヤー 6が全ての穴に挿入されていることを確認した後、 余計なワイヤー 6を取り除き、 穴に立ったワイヤ一 6の上部に平らに研磨されたカーボン、 も しくは耐熱性が 1 200°C以上ある材質の板 7 (サイズ 250mmX 250m m、 30mm厚) を載せ、 そのままガラス基板を平らな台の上に載せ、 窒素雰 囲気中にて 800°C (ガラスの粘性が 1 08ポアズとなる温度) に加熱する (図 1 (5) ) 。 After confirming that the wire 6 is inserted into all the holes, remove the extra wire 6 and place a flat polished carbon on the top of the wire 6 standing at the hole, or heat resistance of 1,200 ° C or more is material of the plate 7 (size 250mmX 250m m, 30mm thickness) loaded with, as it is placed on a glass substrate of a flat surface, the viscosity of 800 ° C (glass in a nitrogen atmosphere and a 1 0 8 poises (Fig. 1 (5)).

このときガラスは軟化し、 ワイヤ一 6は力一ボン板 7の自重で、 軟化したガ ラス内部 (穴の底部) に揷入され、 さらにワイヤ一 6が挿入されたガラスの加 ェ穴と融着して、 ワイヤー 6は密着、 固定される。  At this time, the glass is softened, and the wire 16 is introduced into the softened glass (at the bottom of the hole) by the weight of the force plate 7, and further melts with the glass hole into which the wire 16 is inserted. The wire 6 is attached and fixed.

このときワイヤー 6は、 ガラス基板に穿った穴の底部に 0. 5mm厚で残つ たガラス内部に挿入される。 必ずしもワイヤー 6が穴の底部より突き出る必要 はない。 なお、 工程 (5) において、 ワイヤー 6の加圧は省略しても良い。 工程 (6) ガラス基板の冷却 ·熱収縮によるワイヤーの固定  At this time, the wire 6 is inserted into the glass left at the bottom of the hole drilled in the glass substrate with a thickness of 0.5 mm. It is not necessary that the wire 6 protrude from the bottom of the hole. In step (5), pressurization of the wire 6 may be omitted. Process (6) Cooling glass substrate

ワイヤ一 6の直径はスル一ホールの穴径よりも小さい。 ガラスを軟化し冷却 するとスルーホールは収縮し、 ワイヤー 6は強固に固定される。 その後ワイヤ 一付ガラス基板を室温まで冷却する (図 1 (6) ) 。 The diameter of the wire 16 is smaller than the diameter of the through hole. When the glass is softened and cooled, the through-hole shrinks and the wire 6 is firmly fixed. Then wire The attached glass substrate is cooled to room temperature (Fig. 1 (6)).

工程(7)両面研磨加工(ワイヤ一の両端部をガラス基板表面に露出する工程) 上記ワイヤー付ガラス基板の両面を平坦に研磨し、 ワイヤー 6をガラス基板 の表裏面に完全に露出させる。  Step (7) Double-side polishing (a step of exposing both ends of the wire to the surface of the glass substrate) Both surfaces of the glass substrate with wires are polished flat, and the wires 6 are completely exposed to the front and back surfaces of the glass substrate.

このときワイヤ一 6の露出した面と、 ガラス基板 1の表裏面はほぼ一致する 様に研磨する必要がある。この時の表面粗さは最大高さ Rm a Xで 0.2 m以 下であった。  At this time, the exposed surface of the wire 16 and the front and back surfaces of the glass substrate 1 need to be polished so that they substantially coincide with each other. The surface roughness at this time was less than 0.2 m at the maximum height Rmax.

以後、 研磨された表面をよく洗浄することにより、 ガラス基板 1の表裏面が スルーホール内に挿入されたワイヤー 6を介して電気的に接続可能となってい るスルーホール形成基板 1 0が出来上がる (図 1 (7) ) 。  Thereafter, by thoroughly cleaning the polished surface, a through-hole-formed substrate 10 in which the front and back surfaces of the glass substrate 1 can be electrically connected via the wires 6 inserted into the through-holes is completed ( Figure 1 (7)).

このときスル一ホール形成基板 10の板厚は約 4 mmであった。  At this time, the thickness of the through-hole formed substrate 10 was about 4 mm.

スルーホール形成基板の作製方法 B  Method of manufacturing through-hole-formed substrate B

工程 (1) 低膨張ガラス基板の用意  Process (1) Preparation of low expansion glass substrate

図 2 (1) に示すように、 例えば HOYA製低膨張ガラス基板 NA45 (サ ィズ 23 OmmX 230mm、 5 mm厚) の低膨張ガラス基板 1を用意する。 (尚、 この低膨張ガラス基板 1の表面の表面粗さは R aで、 0. 2 ^m以下で あった。 表面粗さは、 触針式表面粗さ計 (テンコール P 2) で測定。 )  As shown in FIG. 2 (1), for example, a low expansion glass substrate 1 made of HOYA low expansion glass substrate NA45 (size 23 OmmX 230 mm, 5 mm thick) is prepared. (The surface roughness of the surface of the low expansion glass substrate 1 was Ra, which was 0.2 μm or less. The surface roughness was measured by a stylus type surface roughness meter (Tencor P2). )

工程 (2) 超音波ドリル加工  Process (2) Ultrasonic drilling

平らなサイズ 10 5mmX 1 05mm、 3 mm厚のステンレス基板 2に、 ピ ツチ 3mm、 径 0. 5mmのねじ穴をアレー状に 3 X 30 =計 900個あけ、 ねじ穴に M0. 5のねじ (長さ 8mm) をすベて挿入してステンレス製のドリ ル 3を形成する。 このようにして、 図 1 (2) と同様なドリル治具を得る。 このドリル治具をガラス基板 1上に載せる一方、 研磨剤 4を水にといて、 ガ ラス基板 1とドリル 3の間に供給しながら 38 kHzの超音波を印加して加工 を施す (図 2 (2) ) 。  Flat size 105 mm x 105 mm, 3 mm thick stainless steel substrate 2, 3 x 30 = drill holes of 0.5 mm in diameter 3 x 30 = 900 holes drilled in total in an array, and M0.5 screw in the screw hole ( Insert the entire length 8mm) to form a stainless steel drill 3. In this way, a drill jig similar to that shown in Fig. 1 (2) is obtained. The drill jig is placed on the glass substrate 1, while the polishing agent 4 is immersed in water and applied with 38 kHz ultrasonic waves while being supplied between the glass substrate 1 and the drill 3 for processing (Fig. 2 (2)).

工程 (3) 超音波加工により、 ドリル 3とほぼ同じ径の穴 5を深さ 4. 5 m m穿つ。 実際には、 ドリル治具を構成するステンレス板 2の位置をずらして 4 回加工し、 900 X 4=計 3600個の穴 5を正確に、 アレー状に穿つ。 その 後研磨剤を洗い流す (図 2 (3) ) 。 なお、 上記 (1 ) 〜 (3 ) の工程は上記作製方法 Aと同じである。 Process (3) Drill a hole 5 with the same diameter as the drill 3 by 4.5 mm in depth by ultrasonic machining. Actually, the stainless steel plate 2 that constitutes the drill jig is shifted four times and processed four times, and 900 x 4 = a total of 3600 holes 5 are accurately drilled in an array. After that, the abrasive is washed away (Fig. 2 (3)). Note that the above steps (1) to (3) are the same as the above-mentioned production method A.

工程 (4 ) 金属微粒子挿入  Process (4) Inserting metal fine particles

本作製方法ではワイヤーの代わりに、 金属微粒子 8を用いた。 金属微粒子 8 は、 振動を与えると、 穴の中に金属微粒子 8が自動的に一括挿入される (図 2 ( 4 ) ) 。 ここで、 金属微粒子 8は、 はんだ、 タングステン、 銅、 ニッケル、 金、 銀等の金属微粒子、 又は、 その合金の微粒子、 若しくは、 表面を金メッキ したニッケル等の金属粒子を使用できる。 いずれの場合にも、 金属微粒子 8は 穴径の 1 / 1 0以下の粒径を備えていることが望ましい。 粒径の異なる金嵐微 粒子を混合して用いると、 穴内における金属微粒子の充填密度を高くすること ができる。 、 なお、 金属微粒子 8の代わりに、 金属粒子等を分散剤 (接着剤や樹脂等) に 分散させたもの等を穴の中に充填する方法を用いても良い。 この場合、 ドリル 加工穴は完全に貫通させた方が分散剤に分散させた金属粒子を完全に穴に充填 することができる。  In this manufacturing method, metal fine particles 8 were used instead of the wires. When the fine metal particles 8 are vibrated, the fine metal particles 8 are automatically and collectively inserted into the holes (FIG. 2 (4)). Here, as the metal fine particles 8, metal fine particles of solder, tungsten, copper, nickel, gold, silver, or the like, or fine particles of an alloy thereof, or metal particles of nickel or the like whose surface is plated with gold can be used. In any case, it is desirable that the metal fine particles 8 have a particle diameter of 1/10 or less of the hole diameter. When a mixture of gold storm particles having different particle sizes is used, the packing density of the metal fine particles in the hole can be increased. Instead of the metal fine particles 8, a method in which metal particles or the like are dispersed in a dispersant (adhesive, resin, or the like) may be used to fill the holes. In this case, when the drilled hole is completely penetrated, the metal particles dispersed in the dispersant can be completely filled in the hole.

工程 (5 ) ガラス基板の加熱による金属粒子の融着 ·固定  Process (5) Fusion and fixation of metal particles by heating glass substrate

金属微粒子 8が全ての穴に挿入されていることを確認した後、 余計な金属微 粒子 8を取り除き、 穴に入った金属微粒子 8の上部に平らに研磨されたカーボ ン、 もしくは耐熱性が 1 2 0 0 °C以上ある材質の板 7を載せ、 そのままガラス 基板を平らな台の上に載せ、 窒素雰囲気中にて 1 0 5 0 °C (ガラスの粘性が 1 0 5ポアズとなる温度) で加熱する (図 2 ( 5 ) ) 。 加熱中、 金属微粒子 8は溶 融しても良いし、 溶融しなくても、 スルーホール内に固定されれば良い。 After confirming that the metal microparticles 8 are inserted into all the holes, remove the extra metal microparticles 8 and place a flat polished carbon Place the 2 0 0 ° C or more is material of the plate 7, it is placed on a glass substrate of a flat table, in a nitrogen atmosphere 1 0 5 0 ° C (the temperature at which the viscosity of the glass becomes 1 0 5 poises) (Fig. 2 (5)). During heating, the metal microparticles 8 may be melted or may not be melted, as long as they are fixed in the through holes.

金属微粒子 8の粒径はスルーホールの穴径ょりも小さいため、 ガラスを軟化 すると融着により金属微粒子 8は十分に固定され、 さらに加熱後の冷却による 熱収縮により金属微粒子 8は強固に固定される。  When the glass is softened, the metal microparticles 8 are sufficiently fixed by fusion, and the metal microparticles 8 are firmly fixed by heat shrinkage due to cooling after heating because the diameter of the metal microparticles 8 is small even in the through hole. Is done.

なお、 工程 (5 ) において、 金属微粒子の加圧は省略しても良い。  In step (5), pressurizing the metal fine particles may be omitted.

工程 (6 ) その後、 余計な金属微粒子を取り除き、 金属微粒子をスルーホー ルに充填したガラス基板を室温まで冷却する (図 2 ( 6 ) ) 。  Step (6) After that, unnecessary metal fine particles are removed, and the glass substrate filled with the metal fine particles in the through-hole is cooled to room temperature (FIG. 2 (6)).

工程 〔7〕 両面研磨加工  Process [7] Double-side polishing

上記金属微粒子 8をスルーホールに充填したガラス基板の両面を平坦に研磨 し、 金属微粒子 8の両端部をガラス基板 1の表裏面に完全に露出させる。 Both sides of the glass substrate filled with metal fine particles 8 in through holes are polished flat Then, both ends of the metal fine particles 8 are completely exposed on the front and back surfaces of the glass substrate 1.

このとき金属微粒子 8の露出した面と、 ガラス基板 1の表裏面はほぼ一致す る様に研磨する必要がある。 研磨後のガラス基板 1の表裏面は最大高さ R m a xで 0 . 2 m以下であった。  At this time, it is necessary to polish the exposed surface of the metal fine particles 8 and the front and back surfaces of the glass substrate 1 so as to substantially coincide. The front and back surfaces of the polished glass substrate 1 had a maximum height R max of 0.2 m or less.

研磨後、 表裏面を洗浄することにより、 ガラス基板 1の表裏面がスルーホー ル内に挿入された金属微粒子 8を介して電気的に接続されたスルーホール形成 基板 1 0が得られる (図 2 ( 7 ) ) 。  After polishing, the front and back surfaces are washed to obtain a through-hole-formed substrate 10 in which the front and back surfaces of the glass substrate 1 are electrically connected via the fine metal particles 8 inserted into the through-hole (FIG. 7))).

このときスルーホール形成基板 1 0の板厚は約 4 mmであった。  At this time, the thickness of the through-hole-formed substrate 10 was about 4 mm.

工程 (7 ) では、 金属微粒子 8の代わりに、 金属粒子等を分散剤に分散させ たものを使用した場合に、 はみ出した分散剤及び金属粒子等の導電性部材を研 磨によって除去するとともに、 基板の平坦化加工を施すことができる。  In the step (7), when a metal particle or the like dispersed in a dispersant is used instead of the metal fine particle 8, the protruding dispersant and the conductive member such as the metal particle are removed by polishing, The substrate can be flattened.

両面配線基板の作製  Fabrication of double-sided wiring board

上記方法により形成したスルーホール形成基板(コア基板) A又は Bを用い、 その両面に配線層を形成して、 両面配線板を作製する。  Using the through-hole-formed substrate (core substrate) A or B formed by the above method, a wiring layer is formed on both surfaces thereof to produce a double-sided wiring board.

なお、 スルーホール形成基板全面に形成されたスルーホール (例えば 3 6 0 0個) は、 すべて利用する必要はなく、 用途に応じて、 一部を利用することが できる。 具体的には、 利用するスルーホール上を配線が通る設計とし、 利用し ないスルーホール上を配線が通らない設計とする。  Note that it is not necessary to use all of the through holes (for example, 360) formed on the entire surface of the through hole forming substrate, and some of them can be used depending on the application. Specifically, the design is such that the wiring passes over the used through-holes, and the design does not allow the wiring to pass over the unused through-holes.

表裏を導通させる必要のある配線は、 最寄りのスルーホールを介して接続さ れるように、 配線を設計することが好ましい。 また、 表裏の配線長がなるべく 短くなるように、 スルーホール形成位置 (及び数) や配線を設計することが好 ましい。  It is preferable to design the wiring so that the wiring that needs to be conductive between the front and back is connected through the nearest through hole. Also, it is preferable to design the through-hole formation position (and number) and wiring so that the wiring length on the front and back sides is as short as possible.

スルーホール形成基板 (コア基板) A又は Bの両面に、 スパッ夕法或いはメ ツキ法により、 配線層を形成する。 具体的には、 スパッタ法にて、 C r膜を約 3 0 0オングストローム、 C u膜を約 2 . 5 u rn, N i膜を約 0 . 3 z mの月莫 厚で順次成膜して C r / C u /N i配線層を形成する。  Through-hole forming substrate (core substrate) Wiring layers are formed on both sides of A or B by the spattering method or the plating method. Specifically, a Cr film is formed by sputtering at a thickness of about 300 angstroms, a Cu film is formed at a thickness of about 2.5 urn, and a Ni film is formed at a thickness of about 0.3 zm. A Cr / Cu / Ni wiring layer is formed.

次ぎに、 配線の設計に基づき、 所定のフォトリソグラフィ一工程 (レジスト コート、 露光、 現像、 エッチング) を行い、 C r Z C u ZN i配線層をパター  Next, based on the wiring design, a predetermined photolithography process (resist coating, exposure, development, etching) is performed, and the CrZCuZNi wiring layer is patterned.

'一ホール形成基板の両面に配線パターンが形成された両面配線 5 基板を作製した。 '' Double-sided wiring with wiring patterns formed on both sides of a single-hole-formed substrate Five substrates were fabricated.

多層両面配線基板の作製  Fabrication of multilayer double-sided wiring board

次ぎに 1層目の配線パターン上に感光性ポリイミド前駆体をスピンナ一等を 用いて 10 mの厚みで塗布して、 ポリイミド絶縁膜を形成し、 このポリイミ ド絶緣膜にコンタクトホールを形成する。 詳しくは、 コンタクトホールは、 塗 布した感光性ポリイミド前駆体を 80°Cで 30分間べ一クし、 所定のマスクを 用いて露光、 現像して形成した。  Next, a photosensitive polyimide precursor is applied on the first wiring pattern with a thickness of 10 m using a spinner or the like to form a polyimide insulating film, and a contact hole is formed in the polyimide insulating film. Specifically, the contact holes were formed by baking the coated photosensitive polyimide precursor at 80 ° C. for 30 minutes, exposing and developing using a predetermined mask.

次ぎに、 上述と同様にしてコンタクトホールが形成されたポリイミド絶縁膜 上に、 C rZC uZN i配線層を形成し、 上述と同様に C rZCuZN i配線 層をパターニングして、 2層目の配線パターンを形成し、 スルーホール形成基 板の両面に 2層の配線パターンを形成した多層両面配線基板を得た。  Next, a CrZCuZNi wiring layer is formed on the polyimide insulating film in which the contact hole is formed in the same manner as described above, and the CrZCuZNi wiring layer is patterned in the same manner as described above to form a second-layer wiring pattern. Was formed to obtain a multilayer double-sided wiring board in which two-layer wiring patterns were formed on both sides of the through-hole forming substrate.

尚、 多層両面配線基板の配線層の膜材料、 絶縁層の材料、 配線層及び絶縁層 の層数、 膜厚及び多層両面配線基板の製造方法は上述に限定されない。  The film material of the wiring layer of the multilayer double-sided wiring board, the material of the insulating layer, the number of wiring layers and insulating layers, the film thickness, and the method of manufacturing the multilayer double-sided wiring board are not limited to those described above.

配線層の膜材料としては、 上述の C rZCuZN i以外に、 C r/CuZN i/Au多層構造や、 CuZN i /Au多層構造などでも良い。  As the film material of the wiring layer, a Cr / CuZN i / Au multilayer structure, a CuZN i / Au multilayer structure, or the like may be used in addition to the above-mentioned CrZCuZNi.

また、 絶縁層の材料としては、 上述のポリイミド以外に、 アクリル系樹脂や エポキシ樹脂などが挙げられる。 中でも低膨張率を有し、 耐熱性ゃ耐薬品性に 優れるポリイミドが好ましい。  Examples of the material of the insulating layer include an acrylic resin and an epoxy resin in addition to the polyimide described above. Among them, polyimide having a low expansion coefficient and excellent in heat resistance and chemical resistance is preferable.

多層両面配線基板の製造方法も、 上述では両面同時に配線層、 配線パターン を形成したが、 裏面を保護しながら片面ずつ配線層、 配線パターンを形成して も良い。  In the manufacturing method of the multilayer double-sided wiring board, the wiring layer and the wiring pattern are formed simultaneously on both sides in the above description, but the wiring layer and the wiring pattern may be formed one by one while protecting the back surface.

ウェハー括コンタクトボードの作製例 1  Fabrication example 1 of wafer contact board

作製例 1のウェハー括コンタクトボードは、 多層両面配線基板と、 異方性導 電ゴムシートと、 バンプ付きメンブレンから構成されている (図 4) 。  The wafer contact board of Production Example 1 was composed of a multilayer double-sided wiring board, an anisotropic conductive rubber sheet, and a membrane with bumps (Fig. 4).

図 4に示すように、 ウェハー括コンタクトボード 20において、 多層両面配 線基板 (サイズは 20 Omm^以上) は、 上記方法により基板全面に 3600 個のスルーホールをアレイ状に形成したコア基板 A又は Bを用い、 その両面に 多層配線層を形成して作製されており、 両面の配線はスルーホール内に挿入さ れた導電部材 (ワイヤ一、 金属微粒子など) によって電気的にコンタクトされ ている。 As shown in FIG. 4, in the wafer contact board 20, the multilayer double-sided wiring board (having a size of 20 Omm ^ or more) is a core substrate A or 3600 through-holes formed in an array on the entire surface of the substrate by the above method. It is manufactured by forming a multilayer wiring layer on both sides using B, and the wiring on both sides is electrically contacted by conductive members (wires, metal fine particles, etc.) inserted in through holes. ing.

多層両面配線基板の裏側の配線には、 外部から電気を導く配線及び外部とコ ン夕クトするためのパッドが形成されている。 そのパッド部分に例えばポゴピ ン (パネが入った伸縮自在のピン) 等でテスタ一に電気的に接続される。 ここ で、 多層両面配線基板の周辺部のみならず、 中心部を含む基板全面でテスター に電気的に接続される構造が特徴的である。  On the wiring on the back side of the multilayer double-sided wiring board, wiring for conducting electricity from the outside and pads for connecting to the outside are formed. The pad portion is electrically connected to the tester using, for example, a pogo pin (an extensible pin containing a panel). Here, not only the peripheral portion of the multilayer double-sided wiring board but also the entire surface including the central portion is electrically connected to the tester.

多層両面配線基板の表側の配線は、 電気信号を流すための配線と、 素子 (チ ップ抵抗やチップコンデンサ等) と、 被検査対象であるウェハ上に形成された パッド電極に対応したパッド電極と、 が形成されている。 そして、 クッション 性がある異方性導電シートを中間層に介し、 ポリイミドフィルム等の表裏面に 孤立パッド及び孤立バンプを形成してなるバンプ付きメンプレン (表裏面の孤 立パッド Z孤立バンプ間はビアを介して電気的につながつている) のバンプを 介して、 ウェハ上のパッド電極と接続する構成となっている。  The wiring on the front side of the multilayer double-sided wiring board consists of wiring for passing electric signals, elements (chip resistors, chip capacitors, etc.) and pad electrodes corresponding to the pad electrodes formed on the wafer to be inspected. And are formed. Then, a bumped membrane formed by forming an isolated pad and an isolated bump on the front and back surfaces of a polyimide film or the like via an anisotropic conductive sheet with cushioning properties in the middle layer (isolated pad on the front and back surfaces Z via hole between isolated bumps) It is electrically connected to the pad electrode on the wafer via the bump.

図 4に示す多層両面配線基板は、 基本的には、 ウェハ上に形成されたチップ に対応して 1チップ当たり均等にスル一ホールが穿たれるように必要な穴の数、 ピッチのスルーホールが複数形成されており、 裏面には表側の、 ウェハ上に形 成されたパッドに対応するパッドよりもピッチが広くかつ、 少なぃパッドが形 成されているが、裏面全面にスルーホールが形成されていることが特徴である。 表側の各チップに対応するスルーホールを通してつながつている裏面のパッド 電極は、 基本的にウェハチップの上部近傍に形成され外部への導通はほぼ垂直 にもしくは最短経路で結ばれる。  Basically, the multilayer double-sided wiring board shown in Fig. 4 has the number of holes and the required through-holes so that the through holes are evenly drilled per chip corresponding to the chips formed on the wafer. A plurality of pads are formed on the back side with a wider pitch and fewer pads than the pads on the front side corresponding to the pads formed on the wafer, but through holes are formed on the entire back side It is characteristic that it is done. The pad electrode on the back surface connected through the through hole corresponding to each chip on the front side is basically formed near the upper part of the wafer chip, and conduction to the outside is connected almost vertically or by the shortest path.

このコァ基板は被検査物デバイスの種類が変わつても対応できるように、 基 板全面に導電性スルーホール (スルーホール内に導電部材が揷入され基板表裏 面が電気的に接続可能となっているスルーホール) が所定の位置に形成されて おり、 標準化されている。 このようにすることによりコスト的に安価に製造で さる。  This core substrate has conductive through holes throughout the substrate (a conductive member is inserted into the through hole so that the front and back surfaces of the substrate can be electrically connected so that the type of device under test can be changed). Are formed at predetermined positions and standardized. By doing so, it is possible to manufacture at low cost.

そのスルーホールはコア基板全面に放射状にもしくは同心円状もしくはァレ —状に形成されており、 その全てにワイヤー、 金属微粒子、 もしくは導電性べ 一スト、 はんだ金属等もしくはメツキ金属により埋め込まれている。 基板の穴 2003/010515 とその導電性物質との間に隙間がある塲合(例えば金属微粒子を充填した場合) は、 樹脂等の非導電性物質で隙間を密閉しても良い。 The through holes are formed radially, concentrically or in an array on the entire surface of the core substrate, all of which are filled with wires, fine metal particles, or conductive paste, solder metal, or metal plating. . Board hole If there is a gap between 2003/010515 and its conductive material (for example, when filled with fine metal particles), the gap may be sealed with a non-conductive material such as resin.

コア基板材料は高温で使用するため、 耐熱性があり、 かつ位置精度が低温、 高温で優れている必要があるため、 熱膨張率が 1 5 p p m以下であること (さ らにはシリコンとの熱膨張率差が 1 3 . 8 2 p p m以下であること) 、 望まし くは l O p p m以下、 さらに望ましくは 5 p p m以下である必要がある。 この ような材料としては、 例えば、 材質として、 S i、 アルミナ、 S i C、 S i N 等のセラミックス、 パイレックス、 石英ガラス、 アルミノボロシリケ一トガラ ス、 コ一ニング 7 0 5 9、 11〇 八製 八4 0 , 4 5等の低膨張ガラスが挙げ られる。 コア基板材料は、 必ずしも絶縁性材料である必要はない。 ただし、 低 膨張金属 (N i合金等) や上記 S i、 S i Cのような半導体をコア基板材料と して用いる場合にあっては、 スルーホール内部を酸化物、 樹脂等で絶縁してか ら、 スル一ホール内部の導電性材料を埋め込む必要がある。 このように、 絶縁 性基板を用いない場合、表面の絶縁化を施した後配線を形成する必要があるが、 逆にコア基板の導電性を利用してコア基板自体にアース接続することにより、 高周波特性、 低ノイズ特性に優れた多層配線基板を得ることができる。 この場 合、 コア基板の内部導電部分 (スルーホール内部を絶縁せずに、 導電性材料を 埋め込んだ部分) に配線の G R Dを導通させることは言うまでもない。  The core substrate material must be heat-resistant because it is used at high temperatures, and it must have excellent positional accuracy at low and high temperatures. Therefore, the coefficient of thermal expansion must be 15 ppm or less. The difference in the coefficient of thermal expansion must be 13.82 ppm or less), preferably 10 ppm or less, more preferably 5 ppm or less. Such materials include, for example, ceramics such as Si, alumina, SiC, and SiN, Pyrex, quartz glass, aluminoborosilicate glass, and Corning 705, 11八 Low-expansion glass such as Eighty-four, forty-five and forty-five. The core substrate material does not necessarily need to be an insulating material. However, when a low expansion metal (Ni alloy or the like) or a semiconductor such as Si or SiC is used as the core substrate material, the inside of the through hole should be insulated with oxide, resin, etc. Therefore, it is necessary to embed the conductive material inside the through hole. As described above, when an insulating substrate is not used, it is necessary to form wiring after insulating the surface, but conversely, by grounding the core substrate itself using the conductivity of the core substrate, A multilayer wiring board having excellent high-frequency characteristics and low-noise characteristics can be obtained. In this case, it goes without saying that the GRD of the wiring is conducted to the conductive portion inside the core substrate (the portion in which the conductive material is embedded without insulating the inside of the through hole).

また、 コア基板材料が感光性ガラスの場合、 感光性ガラス基板にマスクを通 して多数の穴を形成する部分に潜像が形成されるように露光し、 この露光した 部分を結晶化させ、 結晶化させた領域を溶解除去して多数の穴を形成してコア 基板としても良い。 この場合、 さらに狭ピッチで細い (スルーホ一ル径が小さ い) 穴を高精度に一括して形成することができる。  When the core substrate material is a photosensitive glass, the photosensitive glass substrate is exposed through a mask so that a latent image is formed in a portion where a large number of holes are formed, and the exposed portion is crystallized. The crystallized region may be dissolved and removed to form a large number of holes to form a core substrate. In this case, narrower holes (small through-hole diameters) can be formed at a high precision with a narrower pitch.

異方性導電シートは、 垂直方向に導電性を持つように形成されており、 ゴム 等の弾性体にワイヤーが垂直方向に埋め込まれている構造をとつてもよく、 金 属等の導電粒子が一面にもしくは局所的に埋め込まれた構造をとつてもよい。 バンプ付きメンプレン構造は、 例えば、 ポリイミドフィルムの裏面に銅の孤 立パッドが形成されており、 その表側の面にはフォトリソグラフィ一法により 形成された金属パッドでもよく、 メツキ等で形成されたバンプでもよいが、 裏 PC漏 003/010515 面の孤立パッドと表側のパッド又はバンプとはフィルム内部を通して導通して いる。 このフレキシブルフィルムの構造は表裏が反対でもよい。 バンプ付きメ ンプレンはフレキシブル性を持つているが、 必すしもクッション性持つていな くとも良い。 The anisotropic conductive sheet is formed so as to have conductivity in the vertical direction, and may have a structure in which wires are buried in an elastic body such as rubber in the vertical direction, and conductive particles such as metal may be used. A structure embedded on one side or locally may be adopted. In the membrane structure with bumps, for example, an isolated copper pad is formed on the back surface of a polyimide film, and a metal pad formed by a photolithography method may be formed on the front surface thereof. But it may be The isolated pad on the PC leakage 003/010515 surface and the pad or bump on the front side are electrically connected through the inside of the film. The structure of the flexible film may be reversed. The bumped membrane has flexibility, but does not have to have cushioning.

ウェハー括コンタクトボードの作製例 2  Example of making a wafer contact board 2

作製例 2のウェハー括コンタクトボードは、 多層両面配線基板と、 バネ性を 持った微小なコンタクトプローブから構成されている (図 5 ) 。  The wafer contact board of Fabrication Example 2 consists of a multilayer double-sided wiring board and a small contact probe with spring properties (Fig. 5).

図 5に示すように、 ウェハー括コンタクトポ一ド 2 0における多層両面配線 基板の表側のパッド電極は、 バネ性を (材質的に、 もしくは構造的に) 持った 微小なコンタクトプロ一ブ (釙) 等を介して、 ウェハ上のパッド電極と接続す る構成とすることができる。 ここで、 パネ性を持った針等の線材は、 多層両面 配線基板の表側のパッド電極と、 はんだ、 熱融着、 その他の方法で機械的、 電 気的に接合される。 例えば、 ワイヤ一ボンディング技術を応用して金属ワイヤ 一を接合しても良いし、 マイクロマシン技術を応用して形成した微細な釙をは んだ等の技術を用いて接合しても良い。  As shown in Fig. 5, the pad electrode on the front side of the multilayer double-sided wiring board in the wafer contact node 20 is a small contact probe (釙 material or structural) that has spring properties (material or structural). ) Can be connected to the pad electrode on the wafer via the above. Here, the wire material such as a needle having a paneling property is mechanically and electrically bonded to the pad electrode on the front side of the multilayer double-sided wiring board by soldering, heat fusion, or other methods. For example, the metal wires may be joined by applying a wire-to-bonding technique, or the joining may be carried out by using a technique such as a fine solder formed by applying a micromachine technique.

多層両面配線基板の表側のパッド電極は、 直接ウェハ上のパッド電極と接続 する構成とすることもできる。  The pad electrode on the front side of the multilayer double-sided wiring board may be configured to be directly connected to the pad electrode on the wafer.

多層両面配線基板の表側のパッド電極は、 異方性弾性シート等の可塑性等の 繰り返しコンタクト可能な異方性部材を介して、 ウェハ上のパッド電極と接続 する構成とすることもできる。  The pad electrode on the front side of the multilayer double-sided wiring board may be configured to be connected to the pad electrode on the wafer via an anisotropic member such as an anisotropic elastic sheet that can be repeatedly contacted.

多層両面配線基板の表側のパッド電極上に又はパッド電極自体を、 導電性圧 縮材料 (例えば、 はんだポール、 A u等の) 柔らかい材料を用いたバンプ (凸 状の電極) を形成し、 永久コンタクト (1回限りのコンタクト) もしくは、 繰 り返し耐久性のあまりないような部材を形成、 あるいは別形成させて (挟み込 んで) 、 被測定デバイス、 素子等の電極と接続する構成とすることもできる。 その他の事項に関しては、 上記ウェハー括コンタクトポードの作製例 1と同 様である。  A bump (convex electrode) made of a soft material such as a conductive compressive material (eg, solder pole, Au, etc.) is formed on the pad electrode on the front side of the multilayer double-sided wiring board or on the pad electrode itself. A contact (one-time contact) or a member that is not durable repeatedly is formed, or formed separately (sandwiched) and connected to the electrodes of the device under test, elements, etc. You can also. Other items are the same as those in the first example of the wafer-bound contact port.

なお、 上記ウェハー括コンタクトボードの作製例 1、 2では、 多層両面配線 基板としたが、 多層でなくても、 コア基板の表裏面に 1層形成された両面配線 基板であっても良いことは言うまでもない。 産業上の利用可能性 Note that, in the above examples 1 and 2 of manufacturing the wafer contact board, a multi-layer double-sided wiring board was used. Needless to say, the substrate may be used. Industrial applicability

本発明のスルーホール形成基板の製造方法によれば、 基板に形成した孔 (穴) に導電部材を掙入又は充填した後、 基板の軟化温度以上であって基板形状が維 持できる温度以下に前記基板を加熱することによって、 融着により導電部材を 十分に固定できる。 さらに加熱後の冷却による熱収縮により導電部材を強固に 固定できる。 さらに、 融着及び熱収縮により隙間なく密封されることになるの で、 耐腐蝕性等を向上できる。 さらに、 融着及び/又は熱収縮により前記導電 部材を固定しているので、 スルーホールの数が多数の場合であっても、 一度に 固定可能である。 また、 振動でワイヤ一を挿入することによって、 ワイヤ一揷 入工程の極端な低コスト化が可能となる。  According to the method for manufacturing a through-hole-formed substrate of the present invention, after a conductive member is inserted or filled in a hole (hole) formed in the substrate, the temperature is reduced to a temperature not lower than the softening temperature of the substrate and not higher than the temperature at which the shape of the substrate can be maintained. By heating the substrate, the conductive member can be sufficiently fixed by fusion. Further, the conductive member can be firmly fixed by heat shrinkage due to cooling after heating. Furthermore, since sealing is performed without gaps by fusion and heat shrinkage, corrosion resistance and the like can be improved. Further, since the conductive member is fixed by fusion and / or heat shrinkage, it can be fixed at a time even if the number of through holes is large. Further, by inserting the wire by vibration, extremely low cost of the wire inserting process can be achieved.

また、 本発明のスルーホール形成基板の製造方法によれば、 被加工基板の一 方の面に多数のドリルを等間隔に配置し、 このドリルに超音波を印加して前記 被加工基板に多数の穴を一括して形成しているので、 多数の穴を有するスルー ホール形成基板の廉価を実現できる。 したがって、 この廉価なスルーホール形 成基板を用い、 廉価両面配線基板を実現できる。  Further, according to the method of manufacturing a through-hole formed substrate of the present invention, a large number of drills are arranged at regular intervals on one surface of a substrate to be processed, and ultrasonic waves are applied to the drills to form a large number of holes on the substrate to be processed. Since the holes are collectively formed, the cost of a through-hole forming substrate having a large number of holes can be realized. Therefore, an inexpensive double-sided wiring board can be realized using this inexpensive through-hole formed substrate.

本発明によれば、 上記各発明を組み合わせることによって、 狭ピッチで細く 高い位置精度のスルーホールを基板全面に多数形成した高精度、 低熱膨張、 表 面平坦性の良いスル一ホール形成基板を安価に実現できる。  According to the present invention, by combining the above-described inventions, a through-hole formed substrate with high precision, low thermal expansion, and excellent surface flatness, in which a large number of narrow and fine through holes with high positional accuracy are formed on the entire surface of the substrate, is inexpensive Can be realized.

本発明のウェハー括コンタクトボードの製造方法によれば、 高周波用途のゥ ェハー括コンタクトポードを実現できる。  According to the method for manufacturing a wafer-bound contact board of the present invention, a wafer-bound contact board for high-frequency applications can be realized.

Claims

請 求 の 範 囲 The scope of the claims 1 . 多数の穴を形成したホール形成基板における各穴に、 導電部材を埋設す る工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導電部材 と共に熱処理して、 前記各穴に前記導電部材を固定する導電部材固定工程とを 有することを特徴とするホール形成基板の製造方法。 1. a step of burying a conductive member in each hole of the hole-formed substrate having a large number of holes formed therein; and, after embedding the conductive member, heat-treating the hole-formed substrate together with the buried conductive member to form each of the holes. And a conductive member fixing step of fixing the conductive member. 2 . 請求項 1において、 前記導電部材固定工程は、 前記ホール形成基板の軟 化点温度以上で、 基板形状が維持できる温度以下の前記ホール形成基板を加熱 することにより、 前記各穴に前記導電部材を融着する工程を含むことを特徴と するホール形成基板の製造方法。  2. The conductive member fixing step according to claim 1, wherein the hole-forming substrate is heated to a temperature equal to or higher than a softening point temperature of the hole-forming substrate and equal to or lower than a temperature at which a substrate shape can be maintained. A method for manufacturing a hole-formed substrate, comprising a step of fusing members. 3 . 請求項 1において、 前記導電部材固定工程は、 前記ホール形成基板の軟 化点温度以上で、 基板形状が維持できる温度以下の前記ホール形成基板を加熱 する工程と、 前記ホール形成基板の加熱後、 冷却することによって、 前記基板 を熱収縮させる工程とを含み、 これによつて、 前記導電部材を各穴に固定する ことを特徴とするホール形成基板の製造方法。  3. The method according to claim 1, wherein the conductive member fixing step comprises: heating the hole forming substrate at a temperature equal to or higher than a softening point temperature of the hole forming substrate and equal to or lower than a temperature at which a substrate shape can be maintained; And a step of heat-shrinking the substrate by cooling, whereby the conductive member is fixed in each hole. 4 . 請求項 1において、 前記ホール形成基板はガラス材料からなり、 前記導 電部材固定工程では、 ガラスの粘度が 1 0 4〜1 0 11ポアズとなるように、 前記 ホール形成基板を加熱することを特徴とするホ一ル形成基板の製造方法。 4. In claim 1, wherein the hole forming substrate is made of glass material, in the conductive member fixing process, so that the viscosity of the glass becomes 1 0 4 to 1 0 11 poise, heating the hole forming substrate A method for producing a hole-formed substrate. 5 . 請求項 1において、 更に、 被加工基板と、 複数のドリルを植設したドリ ル治具を用意し、 当該被加工基板の一方の表面に、 前記複数のドリルを有する ドリル治具を接触した状態で、 前記ドリル治具を振動させることにより、 複数 の穴を一括して形成し、 前記ホール形成基板を形成する工程を有することを特 徴とするホール形成基板の製造方法。  5. The method according to claim 1, further comprising preparing a substrate to be processed and a drill jig in which a plurality of drills are implanted, and contacting a drill jig having the plurality of drills with one surface of the substrate to be processed. A method for manufacturing a hole-formed substrate, comprising: forming a plurality of holes in a lump by vibrating the drill jig in this state to form the hole-formed substrate. 6 . 請求項 5において、 前記ドリル治具には超音波を与えて、 複数の穴を一 括形成することを特徴とするホール形成基板の製造方法。  6. The method for manufacturing a hole-formed substrate according to claim 5, wherein ultrasonic waves are applied to the drill jig to collectively form a plurality of holes. 7 . 請求項 1において、 前記導電部材を埋設する工程は前記ホール形成基板 の各穴の径ょりも細い径の線状導電体を前記穴が形成された前記ホール形成基 板の表面に載せた後、 前記ホール基板に振動を与えることによって前記各穴に 前記導電体を挿入して埋設することを特徴とするホール形成基板の製造方法。 7. The method according to claim 1, wherein the step of burying the conductive member comprises placing a linear conductor having a diameter smaller than that of each hole of the hole forming substrate on the surface of the hole forming substrate in which the hole is formed. Then, the conductor is inserted and buried in each of the holes by applying vibration to the hole substrate. 8 . 請求項 1において、 前記導電部材を埋設する工程は前記導電部材として 金属微粒子を用い、 前記金属微粒子に振動を与えることにより前記ホール形成 基板の各穴に充填し、 これによつて、 前記導電部材を埋設することを特徴とす るホール形成基板の製造方法。 8. The method according to claim 1, wherein the step of burying the conductive member uses metal fine particles as the conductive member, and fills each hole of the hole-forming substrate by applying vibration to the metal fine particles. A method for manufacturing a hole-formed substrate, comprising burying a conductive member. 9 . 多数の穴を形成したホール形成基板における各穴に、 導電部材を埋設す る工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導電部材 と共に熱処理して、 前記各穴に前記導電部材を固定する導電部材固定工程と、 前記導電部材を固定されたホール形成基板を表面研磨して、 対向する両面に前 記導電部材を露出させる工程と、 を有することを特徴とするスル一ホ一ル形成 基板の製造方法。  9. A step of burying a conductive member in each hole of the hole-formed substrate having a large number of holes formed therein, and after burying the conductive member, heat-treating the hole-formed substrate together with the buried conductive member to form each of the holes. A conductive member fixing step of fixing the conductive member, and a step of polishing the surface of the hole-formed substrate to which the conductive member is fixed to expose the conductive member on both opposing surfaces. A method for manufacturing a through-hole forming substrate. 1 0 . 多数の穴を形成したホール形成基板における各穴に、 導電部材を埋設 する工程と、 前記導電部材の埋設後、 前記ホール形成基板を埋設された導電部 材と共に熱処理して、前記各穴に前記導電部材を固定する導電部材固定工程と、 前記導電部材を固定されたホール形成基板を表面研磨して、 対向する両面に前 記導電部材を露出させる工程と、 及び、 前記両面のうち、 少なくとも一方の面 上に前記露出した前記導電部材に配線層を形成する工程とを有することを特徴 とする配線基板の製造方法。  10. A step of burying a conductive member in each hole of the hole-formed substrate in which a large number of holes are formed; and, after embedding the conductive member, heat-treating the hole-formed substrate together with the buried conductive member. A conductive member fixing step of fixing the conductive member in the hole, a step of polishing the surface of the hole-formed substrate to which the conductive member is fixed, and exposing the conductive member on opposing surfaces; and Forming a wiring layer on the exposed conductive member on at least one surface. 1 1 . 請求項 1 0に記載された配線基板を用いて構成されたことを特徴とす るウェハー括コンタクトポード。  11. A wafer contact hole, which is constituted by using the wiring substrate according to claim 10. 1 2 . 複数の導電部材を複数の穴内に埋設した構成を備えた基板において、 前記基板はガラス材料によって形成され、 前記導電部材を埋設した表面は最大 高さ R m a Xで 2 m以下の表面粗さを有するように研磨されていることを特 徴とする基板。  1 2. In a substrate having a configuration in which a plurality of conductive members are embedded in a plurality of holes, the substrate is formed of a glass material, and the surface on which the conductive members are embedded is a surface having a maximum height R max of 2 m or less. A substrate characterized by being polished to have roughness.
PCT/JP2003/010515 2002-08-21 2003-08-20 Perforated substrate, method for manufacturing same and full wafer contact board Ceased WO2004019668A1 (en)

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