[go: up one dir, main page]

WO2003012178A1 - Substrat a empilement cristallin, couche cristalline, dispositif et procede de fabrication associe - Google Patents

Substrat a empilement cristallin, couche cristalline, dispositif et procede de fabrication associe Download PDF

Info

Publication number
WO2003012178A1
WO2003012178A1 PCT/JP2002/007484 JP0207484W WO03012178A1 WO 2003012178 A1 WO2003012178 A1 WO 2003012178A1 JP 0207484 W JP0207484 W JP 0207484W WO 03012178 A1 WO03012178 A1 WO 03012178A1
Authority
WO
WIPO (PCT)
Prior art keywords
crystal
crystal layer
substrate
base substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2002/007484
Other languages
English (en)
Japanese (ja)
Inventor
Eiichi Yamaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powdec KK
Original Assignee
Powdec KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powdec KK filed Critical Powdec KK
Priority to JP2003517347A priority Critical patent/JP4191599B2/ja
Publication of WO2003012178A1 publication Critical patent/WO2003012178A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape

Definitions

  • the present invention relates to a crystal laminated substrate, a crystal layer, an element, and a method for producing the same, and is suitably applied to the production of various semiconductor elements.
  • a semiconductor layer is formed on a basic substrate
  • research and development have been conducted in which the basic substrate is removed from the semiconductor layer, and the semiconductor layer is used as a subsequent semiconductor substrate.
  • the technology for separating the Si substrate as a basic substrate For example, a technology has been proposed in which a silicon solar cell thin film semiconductor layer is formed on a Si substrate by CVD, the thin film semiconductor layer is peeled off from a basic substrate, and the Si substrate is reused.
  • a porous Si layer is formed on a Si substrate, a semiconductor layer such as a solar cell is formed thereon, and adhesives are provided above and below the semiconductor layer.
  • a method is shown in which the porous Si layer is mechanically broken by pulling the jig in the opposite direction, and the semiconductor layer is separated from the Si substrate.
  • Japanese Patent Application Laid-Open No. H10-15021 discloses a method of breaking and separating the porous Si layer by ultrasonic irradiation with the same structure.
  • a plastic substrate is adhered on a solar cell layer with the same structure, and by cooling the plastic substrate, the heat between the plastic substrate and the Si substrate is reduced.
  • a method is described in which the porous Si layer is broken and separated by shear stress based on the difference in shrinkage.
  • Japanese Patent Application Laid-Open No. 2000-185757 a reticulated Si exposed surface is formed on an Si substrate on which an oxide layer is formed. From this, a technique of forming a reticulated solar cell by selective growth and separating it by a mechanical peeling method is disclosed.
  • a technique for separating a sapphire substrate from a gallium nitride semiconductor layer formed on the sapphire substrate has been developed.
  • a conventional technique for manufacturing a gallium nitride semiconductor substrate is to form a thick gallium nitride on a sapphire substrate by a chloride method and then scrape the sapphire substrate by a mechanical lapping method or a cutting method. There is a way.
  • a substrate separation method using a chemical etching method has been proposed.
  • a gallium nitride semiconductor is grown on a base substrate through a buffer layer made of an oxide such as zinc oxide (ZnO) or magnesium oxide (MgO) and the buffer layer is removed by etching.
  • ZnO zinc oxide
  • MgO magnesium oxide
  • the above chemical etching method requires a very long time to separate the base substrate and the semiconductor layer.
  • etching between the base substrate and the semiconductor layer is considered.
  • There has been proposed a method of providing a flow hole for the flow of the agent and significantly shortening the etching time see Japanese Patent Application Laid-Open No. 2001-36939).
  • FIG. 1 shows the structure of the semiconductor laminated substrate by the etching separation method. The steps of manufacturing and separating the conventional semiconductor laminated substrate shown in FIG. 1 will be briefly described.
  • an aluminum nitride (A1N) thin film layer 32 is formed as a separation layer on a base substrate 1 made of a sapphire substrate, and a gallium nitride (GaN) buffer layer 33 is grown thereon to about 2 m.
  • the nitride layer is formed in a stripe or island shape by a standard lithography process and gas etching.
  • an oxide is uniformly deposited by a CVD method, and vertical etching is performed by vapor phase plasma etching to form an oxide growth prevention film 34 on the side wall of the stripe-shaped or island-shaped nitride.
  • the gallium nitride layer is not deposited on the side wall due to the presence of the oxide growth preventing film 34, but is deposited only on the upper portion of the stripe while spreading laterally.
  • the stripes unite to form the gallium nitride semiconductor layer 2 the initial stripe covered with the oxide is preserved as it is, and the recess 4 on the stripe is formed as a flow hole.
  • the steps for separating the base substrate 1 and the gallium nitride semiconductor layer 2 are as follows. First, an aqueous solution of hydrofluoric acid or the like is passed through the concave portions 4 on the stripes, and the growth preventing film 34 on the side walls is removed by etching. Next, after removing the hydrofluoric acid, an Al-based etching solution is passed through the concave portion 4 to etch the aluminum nitride thin film layer 32, whereby the basic substrate 1 is finally separated.
  • the present invention has been made in view of such a problem, and its purpose is to provide a simple Crystal substrate that can easily separate the base substrate from the crystal layer such as a semiconductor layer using the pressure of volume expansion based on thermal expansion or phase transition of a liquid, and a crystal such as a semiconductor layer obtained by using the substrate. It is an object of the present invention to provide devices such as layers and semiconductor devices and methods for their manufacture. Disclosure of the invention
  • a crystal laminated substrate according to the present invention is a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid undergoes thermal expansion or phase transition.
  • a crystal layer is formed on a base substrate, and the liquid is caused to penetrate into the space of the crystal laminated substrate having a space for liquid to enter between the crystal layer and the base substrate, and the heat of the liquid is caused. It is separated from the base substrate by expansion pressure based on expansion or phase transition.
  • a crystal element layer is formed on a base substrate, and the liquid is caused to enter the gap of the crystal laminated substrate having a gap for the liquid to enter between the crystal element layer and the base substrate. It is separated from the base substrate by expansion pressure based on thermal expansion or phase transition of the substrate.
  • a method for manufacturing a crystal laminated substrate according to the present invention is a method for manufacturing a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid
  • the method includes a step of forming a gap for separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition.
  • a crystal layer is formed on a base substrate, and a crystal laminated substrate having a gap between the crystal layer and the base substrate is formed. And a step of injecting a liquid into the void and separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.
  • a crystal element layer is formed on a basic substrate, a crystal laminated substrate having a gap between the crystal element layer and the basic substrate is formed, and a liquid is caused to enter the gap.
  • the method includes a step of separating the crystal element layer from the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.
  • the voids formed in the crystal-laminated substrate may be basically any shape as long as the shape allows a liquid to flow therethrough.
  • the voids may be linear, stripe-shaped, or lattice-shaped. These may be dispersed and formed.
  • the gap is preferably selected to have a depth of 3 to 20 and a width of 3 to 20 ⁇ m.
  • the gaps are typically formed periodically at a pitch of 6 or more and 40 im or less. In this case, the width of the gap and the width of the convex portion between them are selected, for example, to be substantially the same.
  • This gap can be formed as follows. That is, for example, a void can be formed by forming an uneven groove on the base substrate and using the fact that the crystal layer or the crystal element layer avoids lamination when forming a crystal layer or a crystal element layer thereon. Alternatively, after forming a crystal layer for forming voids on a flat base substrate, grooves of irregularities are cut in the crystal layer for forming voids, and when the target crystal layer is further laminated thereon, A gap can be formed even by utilizing the fact that a portion is prevented from being laminated.
  • the gap can also be formed by utilizing the fact that the groove portion avoids the lamination when the crystal layers are laminated.
  • the crystal layer or the crystal element layer is typically a semiconductor layer or a semiconductor element layer, but may be made of a material other than a semiconductor depending on the application.
  • the element is typically a semiconductor element, but may be other various elements.
  • the base substrate may be made of any material necessary for forming a crystal layer or a crystal element layer thereon.
  • a nitride-based semiconductor layer is formed as a crystal layer, sapphire, silicon, spinel, neodymium gallate, lithium gallate, lithium aluminate, ⁇ -V nitride, ⁇ -Group V compounds or silicon oxides can be used.
  • the nitride-based semiconductor layer is typically made of at least one group III material selected from the group consisting of gallium (Ga), aluminum (A1), boron (B), and indium (in).
  • nitride semiconductor containing an element and at least a group V element containing nitrogen selected from the group consisting of nitrogen (N), phosphorus (P) and arsenic (As).
  • the semiconductor layer other than the nitride-based semiconductor include a semiconductor layer made of silicon, germanium, or a mixed crystal thereof.
  • the semiconductor layer When a semiconductor layer is used as the crystal layer, the semiconductor layer does not have to be doped with impurities.However, by doping a p-type impurity, an n-type impurity, or a transition metal in order to obtain a semi-insulating type, active The type of conduction can be controlled effectively.
  • a device structure such as a field effect transistor, a bipolar transistor, a light receiving device, a light emitting diode or a semiconductor laser structure can be formed therein. It is an element layer.
  • Water is the simplest liquid to penetrate or flow into the voids, but various mixed solutions can be used to adjust the phase transition temperature.
  • the liquid for example, at least one selected from the group consisting of water, alcohols, ketones, ethers, amines, petroleums and salts can be used.
  • the solidification temperature can be lowered by adding ethanol or methanol to the water.
  • the most suitable one can be selected for controlling the expansion coefficient and viscosity.
  • phase transition is not a liquid-to-solid transition, but a liquid-to-gas transition due to temperature rise can be used.
  • cooling medium causing the phase transition for example, a cooling medium containing ethanol, methanol or a mixed liquid thereof, liquid nitrogen or liquid air may be used, or a cooling medium containing cooled nitrogen, oxygen or dry air may be used. May be used. If the latter cooled gas is blown, the cooling rate can be controlled for each location, and the separation process can be strictly controlled.
  • a part of the crystal laminated substrate may be covered with a heat shield to locally control the thermal expansion rate or the phase transition rate. In this way, the cooling rate can be controlled for each location, and the separation step can be strictly controlled.
  • a liquid penetrates between a crystal layer or a crystal element layer and a base substrate, and is subjected to expansion pressure based on thermal expansion or phase transition of the liquid. Since there is a gap for separating the crystal layer or the crystal element layer from the base substrate, After the body penetrates or circulates, by changing the temperature of the crystal laminated substrate, the crystal layer or crystal element layer is separated from the base substrate by the expansion pressure based on the thermal expansion or phase transition of the liquid. Become. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a cross-sectional view showing a configuration of a conventional semiconductor multilayer substrate
  • FIG. 2 is a cross-sectional view showing a configuration of a semiconductor multilayer substrate according to a first embodiment of the present invention
  • FIG. FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a second embodiment
  • FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a third embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a configuration of a semiconductor laminated substrate according to the embodiment.
  • FIG. 2 is a sectional view of the semiconductor multilayer substrate according to the first embodiment of the present invention.
  • 1 is a base substrate made of a sapphire substrate
  • 2 is a gallium nitride semiconductor layer
  • 3 is a stripe-shaped projection formed on the base substrate 1, and has a depth of, for example, about 20 m and a stripe width. Is about 5 um, for example.
  • Reference numeral 4 denotes a stripe-shaped concave portion formed on the basic substrate 1 and has a width of, for example, about 5 win.
  • the semiconductor laminated substrate having such a configuration can be manufactured, for example, as follows.
  • the C-plane sapphire substrate 1 is patterned by a known lithography technique and an ion milling method to form a stripe-shaped convex portion 3 .
  • a known nitrided buffer layer is formed at 550 ° C. by a known MOCVD method.
  • a gallium nitride of 0.5 u m Laminate For example, trimethylgallium (TMG) is used as a gallium raw material, ammonia (NH 3 ) is used as a nitrogen raw material, and nitrogen and hydrogen are used as carrier gases.
  • TMG trimethylgallium
  • NH 3 ammonia
  • 300 gm of gallium nitride is grown at 1000 ° C. by a known hydride method.
  • gallium chloride which is a raw material for gallium, causes metal gallium to react with hydrochloric acid gas upstream of the furnace.
  • the nitrogen source for example, ammonia gas is used. No impurity doping is performed here.
  • the gallium nitride semiconductor layer 2 is separated from the base substrate 1 by the following steps.
  • the semiconductor laminated substrate is placed in a container connected to a simple decompression device, and water is added. At this point, the semiconductor laminated substrate is separated from water.
  • the pressure is reduced to about 1 kPa or less, the semiconductor laminated substrate is immersed in water and then returned to the atmospheric pressure. By the above operation, water is filled into the stripe-shaped concave portions 4.
  • the semiconductor laminated substrate is immersed in ethanol cooled to about 110 ° C. to about 150 ° C. to solidify and expand water in the recess 4.
  • the gallium nitride semiconductor layer 2 is dissociated from the bonding surface of the stripe due to the volume expansion of about 9% due to the solidification of water.
  • the gallium nitride semiconductor layer separated from the base substrate 1 in this manner can be used for various applications as a gallium nitride substrate.
  • a semiconductor stripe 3 made of, for example, gallium nitride having a width of, for example, several 1 is formed by a known method, and then a thick gallium nitride semiconductor layer 2 is formed.
  • the distance between the semiconductor stripes 31 is controlled. In the recess, the lamination is avoided when the gallium nitride semiconductor layer 2 is formed, and a void, that is, a stripe-shaped recess 4 is generated.
  • the semiconductor stripe 31 when forming a semiconductor stripe 31 having a width of several meters, the semiconductor stripe 31 is dug down to the underlying base substrate 1 to form a deep stripe-shaped projection 3. I do.
  • a gallium nitride semiconductor layer 1 b is formed on a base substrate 1 a such as a sapphire substrate as a base substrate 1. Digging down to a depth in the middle of b to form a semiconductor stripe 31 of a number;
  • a crystal layer or a crystal element layer is formed on a base substrate, and a gap is formed between the crystal layer or the crystal element layer and the base substrate.
  • an expensive chemical such as a conventional etching liquid and having a concern about environmental load is used. Since it is not necessary, the manufacturing cost can be reduced and the environmental load can be significantly reduced.
  • a group III-V nitride semiconductor such as gallium nitride
  • a group V nitride semiconductor substrate such as a gallium nitride semiconductor substrate can be easily obtained, and a crystal layer can be formed thereon.
  • the resulting semiconductor element has excellent heat dissipation properties, and has an effect that an excellent semiconductor element can be easily manufactured because the cleavage of the substrate can be utilized.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un substrat à empilement cristallin, une couche cristalline, un dispositif et un procédé de fabrication associé présentant un caractère avantageux pour la fabrication de divers types de dispositifs semi-conducteurs. Le substrat à empilement cristallin est fabriqué par formation d'espaces libres (4) dans une forme de bande ou de trame sur la surface d'un substrat de base (1), tel qu'un substrat de saphir, et par superposition sur celle-ci d'une couche semi-conductrice (2), telle qu'une couche semi-conductrice de nitrure de gallium, dans des conditions telles que ces espaces libres (4) n'engendrent pas d'empilement. Un liquide, tel que de l'éthanol, est infiltré dans ces espaces libres (4) et la couche semi-conductrice (2) est séparée du substrat de base (1) sous une pression d'expansion, en fonction de l'expansion thermique ou du transfert de phase du liquide. Cette couche semi-conductrice (2) est utilisée comme substrat semi-conducteur. La fabrication d'une couche cristalline ou d'une couche à élément cristallin par mise en oeuvre d'un substrat à empilement cristallin facilite la fabrication d'un substrat cristallin, tel qu'un substrat semi-conducteur, ou d'un dispositif, tel qu'un dispositif semi-conducteur.
PCT/JP2002/007484 2001-08-01 2002-07-24 Substrat a empilement cristallin, couche cristalline, dispositif et procede de fabrication associe Ceased WO2003012178A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003517347A JP4191599B2 (ja) 2001-08-01 2002-07-24 結晶層の製造方法および素子の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001233454 2001-08-01
JP2001-233454 2001-08-01

Publications (1)

Publication Number Publication Date
WO2003012178A1 true WO2003012178A1 (fr) 2003-02-13

Family

ID=19065232

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/007484 Ceased WO2003012178A1 (fr) 2001-08-01 2002-07-24 Substrat a empilement cristallin, couche cristalline, dispositif et procede de fabrication associe

Country Status (2)

Country Link
JP (1) JP4191599B2 (fr)
WO (1) WO2003012178A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009270200A (ja) * 2008-05-09 2009-11-19 Advanced Optoelectronic Technology Inc 半導体をその基板から分離する方法
JP2014150211A (ja) * 2013-02-04 2014-08-21 Pawdec:Kk 半導体素子の製造方法、絶縁ゲート型電界効果トランジスタ、絶縁ゲート型電界効果トランジスタの製造方法、半導体発光素子の製造方法および太陽電池の製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101337351B1 (ko) * 2011-11-23 2013-12-06 주식회사 아이브이웍스 질화물계 반도체소자의 제조방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101139A (ja) * 1998-09-25 2000-04-07 Toshiba Corp 半導体発光素子及びその製造方法並びに半導体発光装置
JP2001036139A (ja) * 1999-07-23 2001-02-09 Sony Corp 半導体積層基板，半導体結晶基板および半導体素子ならびにそれらの製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101139A (ja) * 1998-09-25 2000-04-07 Toshiba Corp 半導体発光素子及びその製造方法並びに半導体発光装置
JP2001036139A (ja) * 1999-07-23 2001-02-09 Sony Corp 半導体積層基板，半導体結晶基板および半導体素子ならびにそれらの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009270200A (ja) * 2008-05-09 2009-11-19 Advanced Optoelectronic Technology Inc 半導体をその基板から分離する方法
JP2014150211A (ja) * 2013-02-04 2014-08-21 Pawdec:Kk 半導体素子の製造方法、絶縁ゲート型電界効果トランジスタ、絶縁ゲート型電界効果トランジスタの製造方法、半導体発光素子の製造方法および太陽電池の製造方法

Also Published As

Publication number Publication date
JPWO2003012178A1 (ja) 2004-11-18
JP4191599B2 (ja) 2008-12-03

Similar Documents

Publication Publication Date Title
TWI464913B (zh) 用於固態照明裝置之氮化鎵晶圓基板及相關系統及方法
TWI233217B (en) Method for producing semiconductor crystal
KR100623558B1 (ko) Ｉｉｉ족 질화물계 화합물 반도체 및 그 제조방법
CN100573822C (zh) 衬底及其制备方法以及半导体器件及其制备方法
CN101853808B (zh) 形成电路结构的方法
TWI395341B (zh) Group III nitride semiconductor crystal and its manufacturing method, Group III nitride semiconductor device and manufacturing method thereof, and light emitting machine
KR101200182B1 (ko) 질화물 반도체 디바이스의 제조 방법 및 질화물 반도체디바이스
US8133803B2 (en) Method for fabricating semiconductor substrates and semiconductor devices
CN101645481B (zh) 制作氮化物半导体发光器件的方法
JP5916625B2 (ja) 光抽出構造を含む半導体発光装置及び方法
JP2000323417A (ja) Ｉｉｉ族窒化物半導体の製造方法及びｉｉｉ族窒化物半導体発光素子
KR20120114357A (ko) 복합 기판의 형성 및 복합 기판 상 ⅲ-ⅴ족 발광 장치 성장 방법
EP1376664A1 (fr) Procede de fabrication d'un semi-conducteur a base d'un compose nitrure du groupe iii et dispositif semi-conducteur a base d'un compose nitrure du groupe iii
JP7645319B2 (ja) 半導体素子
US20080296626A1 (en) Nitride substrates, thin films, heterostructures and devices for enhanced performance, and methods of making the same
JP5371430B2 (ja) 半導体基板並びにハイドライド気相成長法により自立半導体基板を製造するための方法及びそれに使用されるマスク層
CN116941016A (zh) 半导体基板和其制造方法以及制造装置、模板基板
JP3568112B2 (ja) 半導体基板の製造方法
JPH11274082A (ja) Ｉｉｉ 族窒化物半導体およびその製造方法、およびｉｉｉ 族窒化物半導体装置
KR20090092091A (ko) 발광 소자 및 그 제조 방법
JP4698053B2 (ja) Ｉｉｉ族窒化物系化合物半導体の製造方法
JP4191599B2 (ja) 結晶層の製造方法および素子の製造方法
KR20150015760A (ko) 발광 소자 제조용 템플릿 및 자외선 발광소자 제조 방법
JP4082409B2 (ja) 半導体素子の製造方法
JP2007123435A (ja) 半導体発光素子およびその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR

Kind code of ref document: A1

Designated state(s): CN JP KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR IE IT LU MC NL PT SE SK TR

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FR GB GR IE IT LU MC NL PT SE SK TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003517347

Country of ref document: JP

122 Ep: pct application non-entry in european phase