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WO2003012178A1 - Crystal stacking substrate, crystal layer, device, and their manufacturing method - Google Patents

Crystal stacking substrate, crystal layer, device, and their manufacturing method Download PDF

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Publication number
WO2003012178A1
WO2003012178A1 PCT/JP2002/007484 JP0207484W WO03012178A1 WO 2003012178 A1 WO2003012178 A1 WO 2003012178A1 JP 0207484 W JP0207484 W JP 0207484W WO 03012178 A1 WO03012178 A1 WO 03012178A1
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Prior art keywords
crystal
crystal layer
substrate
base substrate
layer
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French (fr)
Japanese (ja)
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Eiichi Yamaguchi
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Powdec KK
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Powdec KK
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Priority to JP2003517347A priority Critical patent/JP4191599B2/en
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    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/60Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape characterised by shape

Definitions

  • the present invention relates to a crystal laminated substrate, a crystal layer, an element, and a method for producing the same, and is suitably applied to the production of various semiconductor elements.
  • a semiconductor layer is formed on a basic substrate
  • research and development have been conducted in which the basic substrate is removed from the semiconductor layer, and the semiconductor layer is used as a subsequent semiconductor substrate.
  • the technology for separating the Si substrate as a basic substrate For example, a technology has been proposed in which a silicon solar cell thin film semiconductor layer is formed on a Si substrate by CVD, the thin film semiconductor layer is peeled off from a basic substrate, and the Si substrate is reused.
  • a porous Si layer is formed on a Si substrate, a semiconductor layer such as a solar cell is formed thereon, and adhesives are provided above and below the semiconductor layer.
  • a method is shown in which the porous Si layer is mechanically broken by pulling the jig in the opposite direction, and the semiconductor layer is separated from the Si substrate.
  • Japanese Patent Application Laid-Open No. H10-15021 discloses a method of breaking and separating the porous Si layer by ultrasonic irradiation with the same structure.
  • a plastic substrate is adhered on a solar cell layer with the same structure, and by cooling the plastic substrate, the heat between the plastic substrate and the Si substrate is reduced.
  • a method is described in which the porous Si layer is broken and separated by shear stress based on the difference in shrinkage.
  • Japanese Patent Application Laid-Open No. 2000-185757 a reticulated Si exposed surface is formed on an Si substrate on which an oxide layer is formed. From this, a technique of forming a reticulated solar cell by selective growth and separating it by a mechanical peeling method is disclosed.
  • a technique for separating a sapphire substrate from a gallium nitride semiconductor layer formed on the sapphire substrate has been developed.
  • a conventional technique for manufacturing a gallium nitride semiconductor substrate is to form a thick gallium nitride on a sapphire substrate by a chloride method and then scrape the sapphire substrate by a mechanical lapping method or a cutting method. There is a way.
  • a substrate separation method using a chemical etching method has been proposed.
  • a gallium nitride semiconductor is grown on a base substrate through a buffer layer made of an oxide such as zinc oxide (ZnO) or magnesium oxide (MgO) and the buffer layer is removed by etching.
  • ZnO zinc oxide
  • MgO magnesium oxide
  • the above chemical etching method requires a very long time to separate the base substrate and the semiconductor layer.
  • etching between the base substrate and the semiconductor layer is considered.
  • There has been proposed a method of providing a flow hole for the flow of the agent and significantly shortening the etching time see Japanese Patent Application Laid-Open No. 2001-36939).
  • FIG. 1 shows the structure of the semiconductor laminated substrate by the etching separation method. The steps of manufacturing and separating the conventional semiconductor laminated substrate shown in FIG. 1 will be briefly described.
  • an aluminum nitride (A1N) thin film layer 32 is formed as a separation layer on a base substrate 1 made of a sapphire substrate, and a gallium nitride (GaN) buffer layer 33 is grown thereon to about 2 m.
  • the nitride layer is formed in a stripe or island shape by a standard lithography process and gas etching.
  • an oxide is uniformly deposited by a CVD method, and vertical etching is performed by vapor phase plasma etching to form an oxide growth prevention film 34 on the side wall of the stripe-shaped or island-shaped nitride.
  • the gallium nitride layer is not deposited on the side wall due to the presence of the oxide growth preventing film 34, but is deposited only on the upper portion of the stripe while spreading laterally.
  • the stripes unite to form the gallium nitride semiconductor layer 2 the initial stripe covered with the oxide is preserved as it is, and the recess 4 on the stripe is formed as a flow hole.
  • the steps for separating the base substrate 1 and the gallium nitride semiconductor layer 2 are as follows. First, an aqueous solution of hydrofluoric acid or the like is passed through the concave portions 4 on the stripes, and the growth preventing film 34 on the side walls is removed by etching. Next, after removing the hydrofluoric acid, an Al-based etching solution is passed through the concave portion 4 to etch the aluminum nitride thin film layer 32, whereby the basic substrate 1 is finally separated.
  • the present invention has been made in view of such a problem, and its purpose is to provide a simple Crystal substrate that can easily separate the base substrate from the crystal layer such as a semiconductor layer using the pressure of volume expansion based on thermal expansion or phase transition of a liquid, and a crystal such as a semiconductor layer obtained by using the substrate. It is an object of the present invention to provide devices such as layers and semiconductor devices and methods for their manufacture. Disclosure of the invention
  • a crystal laminated substrate according to the present invention is a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid undergoes thermal expansion or phase transition.
  • a crystal layer is formed on a base substrate, and the liquid is caused to penetrate into the space of the crystal laminated substrate having a space for liquid to enter between the crystal layer and the base substrate, and the heat of the liquid is caused. It is separated from the base substrate by expansion pressure based on expansion or phase transition.
  • a crystal element layer is formed on a base substrate, and the liquid is caused to enter the gap of the crystal laminated substrate having a gap for the liquid to enter between the crystal element layer and the base substrate. It is separated from the base substrate by expansion pressure based on thermal expansion or phase transition of the substrate.
  • a method for manufacturing a crystal laminated substrate according to the present invention is a method for manufacturing a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid
  • the method includes a step of forming a gap for separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition.
  • a crystal layer is formed on a base substrate, and a crystal laminated substrate having a gap between the crystal layer and the base substrate is formed. And a step of injecting a liquid into the void and separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.
  • a crystal element layer is formed on a basic substrate, a crystal laminated substrate having a gap between the crystal element layer and the basic substrate is formed, and a liquid is caused to enter the gap.
  • the method includes a step of separating the crystal element layer from the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.
  • the voids formed in the crystal-laminated substrate may be basically any shape as long as the shape allows a liquid to flow therethrough.
  • the voids may be linear, stripe-shaped, or lattice-shaped. These may be dispersed and formed.
  • the gap is preferably selected to have a depth of 3 to 20 and a width of 3 to 20 ⁇ m.
  • the gaps are typically formed periodically at a pitch of 6 or more and 40 im or less. In this case, the width of the gap and the width of the convex portion between them are selected, for example, to be substantially the same.
  • This gap can be formed as follows. That is, for example, a void can be formed by forming an uneven groove on the base substrate and using the fact that the crystal layer or the crystal element layer avoids lamination when forming a crystal layer or a crystal element layer thereon. Alternatively, after forming a crystal layer for forming voids on a flat base substrate, grooves of irregularities are cut in the crystal layer for forming voids, and when the target crystal layer is further laminated thereon, A gap can be formed even by utilizing the fact that a portion is prevented from being laminated.
  • the gap can also be formed by utilizing the fact that the groove portion avoids the lamination when the crystal layers are laminated.
  • the crystal layer or the crystal element layer is typically a semiconductor layer or a semiconductor element layer, but may be made of a material other than a semiconductor depending on the application.
  • the element is typically a semiconductor element, but may be other various elements.
  • the base substrate may be made of any material necessary for forming a crystal layer or a crystal element layer thereon.
  • a nitride-based semiconductor layer is formed as a crystal layer, sapphire, silicon, spinel, neodymium gallate, lithium gallate, lithium aluminate, ⁇ -V nitride, ⁇ -Group V compounds or silicon oxides can be used.
  • the nitride-based semiconductor layer is typically made of at least one group III material selected from the group consisting of gallium (Ga), aluminum (A1), boron (B), and indium (in).
  • nitride semiconductor containing an element and at least a group V element containing nitrogen selected from the group consisting of nitrogen (N), phosphorus (P) and arsenic (As).
  • the semiconductor layer other than the nitride-based semiconductor include a semiconductor layer made of silicon, germanium, or a mixed crystal thereof.
  • the semiconductor layer When a semiconductor layer is used as the crystal layer, the semiconductor layer does not have to be doped with impurities.However, by doping a p-type impurity, an n-type impurity, or a transition metal in order to obtain a semi-insulating type, active The type of conduction can be controlled effectively.
  • a device structure such as a field effect transistor, a bipolar transistor, a light receiving device, a light emitting diode or a semiconductor laser structure can be formed therein. It is an element layer.
  • Water is the simplest liquid to penetrate or flow into the voids, but various mixed solutions can be used to adjust the phase transition temperature.
  • the liquid for example, at least one selected from the group consisting of water, alcohols, ketones, ethers, amines, petroleums and salts can be used.
  • the solidification temperature can be lowered by adding ethanol or methanol to the water.
  • the most suitable one can be selected for controlling the expansion coefficient and viscosity.
  • phase transition is not a liquid-to-solid transition, but a liquid-to-gas transition due to temperature rise can be used.
  • cooling medium causing the phase transition for example, a cooling medium containing ethanol, methanol or a mixed liquid thereof, liquid nitrogen or liquid air may be used, or a cooling medium containing cooled nitrogen, oxygen or dry air may be used. May be used. If the latter cooled gas is blown, the cooling rate can be controlled for each location, and the separation process can be strictly controlled.
  • a part of the crystal laminated substrate may be covered with a heat shield to locally control the thermal expansion rate or the phase transition rate. In this way, the cooling rate can be controlled for each location, and the separation step can be strictly controlled.
  • a liquid penetrates between a crystal layer or a crystal element layer and a base substrate, and is subjected to expansion pressure based on thermal expansion or phase transition of the liquid. Since there is a gap for separating the crystal layer or the crystal element layer from the base substrate, After the body penetrates or circulates, by changing the temperature of the crystal laminated substrate, the crystal layer or crystal element layer is separated from the base substrate by the expansion pressure based on the thermal expansion or phase transition of the liquid. Become. BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 is a cross-sectional view showing a configuration of a conventional semiconductor multilayer substrate
  • FIG. 2 is a cross-sectional view showing a configuration of a semiconductor multilayer substrate according to a first embodiment of the present invention
  • FIG. FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a second embodiment
  • FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a third embodiment of the present invention
  • FIG. 4 is a cross-sectional view showing a configuration of a semiconductor laminated substrate according to the embodiment.
  • FIG. 2 is a sectional view of the semiconductor multilayer substrate according to the first embodiment of the present invention.
  • 1 is a base substrate made of a sapphire substrate
  • 2 is a gallium nitride semiconductor layer
  • 3 is a stripe-shaped projection formed on the base substrate 1, and has a depth of, for example, about 20 m and a stripe width. Is about 5 um, for example.
  • Reference numeral 4 denotes a stripe-shaped concave portion formed on the basic substrate 1 and has a width of, for example, about 5 win.
  • the semiconductor laminated substrate having such a configuration can be manufactured, for example, as follows.
  • the C-plane sapphire substrate 1 is patterned by a known lithography technique and an ion milling method to form a stripe-shaped convex portion 3 .
  • a known nitrided buffer layer is formed at 550 ° C. by a known MOCVD method.
  • a gallium nitride of 0.5 u m Laminate For example, trimethylgallium (TMG) is used as a gallium raw material, ammonia (NH 3 ) is used as a nitrogen raw material, and nitrogen and hydrogen are used as carrier gases.
  • TMG trimethylgallium
  • NH 3 ammonia
  • 300 gm of gallium nitride is grown at 1000 ° C. by a known hydride method.
  • gallium chloride which is a raw material for gallium, causes metal gallium to react with hydrochloric acid gas upstream of the furnace.
  • the nitrogen source for example, ammonia gas is used. No impurity doping is performed here.
  • the gallium nitride semiconductor layer 2 is separated from the base substrate 1 by the following steps.
  • the semiconductor laminated substrate is placed in a container connected to a simple decompression device, and water is added. At this point, the semiconductor laminated substrate is separated from water.
  • the pressure is reduced to about 1 kPa or less, the semiconductor laminated substrate is immersed in water and then returned to the atmospheric pressure. By the above operation, water is filled into the stripe-shaped concave portions 4.
  • the semiconductor laminated substrate is immersed in ethanol cooled to about 110 ° C. to about 150 ° C. to solidify and expand water in the recess 4.
  • the gallium nitride semiconductor layer 2 is dissociated from the bonding surface of the stripe due to the volume expansion of about 9% due to the solidification of water.
  • the gallium nitride semiconductor layer separated from the base substrate 1 in this manner can be used for various applications as a gallium nitride substrate.
  • a semiconductor stripe 3 made of, for example, gallium nitride having a width of, for example, several 1 is formed by a known method, and then a thick gallium nitride semiconductor layer 2 is formed.
  • the distance between the semiconductor stripes 31 is controlled. In the recess, the lamination is avoided when the gallium nitride semiconductor layer 2 is formed, and a void, that is, a stripe-shaped recess 4 is generated.
  • the semiconductor stripe 31 when forming a semiconductor stripe 31 having a width of several meters, the semiconductor stripe 31 is dug down to the underlying base substrate 1 to form a deep stripe-shaped projection 3. I do.
  • a gallium nitride semiconductor layer 1 b is formed on a base substrate 1 a such as a sapphire substrate as a base substrate 1. Digging down to a depth in the middle of b to form a semiconductor stripe 31 of a number;
  • a crystal layer or a crystal element layer is formed on a base substrate, and a gap is formed between the crystal layer or the crystal element layer and the base substrate.
  • an expensive chemical such as a conventional etching liquid and having a concern about environmental load is used. Since it is not necessary, the manufacturing cost can be reduced and the environmental load can be significantly reduced.
  • a group III-V nitride semiconductor such as gallium nitride
  • a group V nitride semiconductor substrate such as a gallium nitride semiconductor substrate can be easily obtained, and a crystal layer can be formed thereon.
  • the resulting semiconductor element has excellent heat dissipation properties, and has an effect that an excellent semiconductor element can be easily manufactured because the cleavage of the substrate can be utilized.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

A crystal stacking substrate, crystal layer, and device, and their manufacturing method which are preferable for the application to the manufacture of various kind of semiconductor devices. This crystal stacking substrate is manufactured by forming air voids (4) in a stripe or lattice form on the surface of a base substrate (1) such as a sapphire substrate, and by overlaying it with a semiconductor layer (2) such as a gallium nitride semiconductor layer under a condition that these air voids (4) cause no stacking. A liquid such as ethanol is infiltrated into these air voids (4), and the semiconductor layer (2) is separated from the base substrate (1) under an expansion pressure based on the thermal expansion or phase transfer of the liquid. This semiconductor layer (2) is used as a semiconductor substrate. The manufacture of a crystal layer or a crystal element layer by using a crystal stacking substrate makes it much easier to manufacture a crystal substrate such as a semiconductor substrate or a device such as a semiconductor device.

Description

結晶積層基板、 結晶層、 素子およびそれらの製造方法  Crystal laminated substrate, crystal layer, element, and method of manufacturing them

技術分野 Technical field

本発明は、 結晶積層基板、 結晶層、 素子およびそれらの製造方法に 関し、 各種の半導体素子の製造に適用して好適なものである。 明  INDUSTRIAL APPLICABILITY The present invention relates to a crystal laminated substrate, a crystal layer, an element, and a method for producing the same, and is suitably applied to the production of various semiconductor elements. Light

背景技術 Background art

 Rice field

半導体層を基礎基板上に形成した後、 上記半導体層から上記基礎基 板を取除き、 上記半導体層を後の半導体基板として利用する研究開発 がなされている。 その中で、 基礎基板として、 S i基板を分離する技術 は多数の報告がある。 例えば、 S i基板上に CVD によりシリコン太陽電 池薄膜半導体層を形成し、 基礎基板から上記薄膜半導体層を剥がし、 S i基板を再利用する技術が提案されている。 例えば、 特開平 8— 2 1 3 6 4 5号公報では、 S i基板上に多孔質 S i層を形成し、 その上に太陽 電池等の半導体層を形成した後、 その上下を接着剤付きの治具で挟み 込み、 治具を反対方向に引っ張って多孔質 S i層を機械的に破断し、 半 導体層を S i基板から分離する方法が示されている。 また、 特開平 1 0 - 1 5 0 2 1 1号公報では、 同構造で超音波照射により上記多孔質 S i 層を破断し、 分離する方法が示されている。 また、 特開平 1 0— 1 9 0 0 3 2号公報では、 同構造で太陽電池層の上にブラスティック基板 を接着し、 それを冷却することにより、 ブラスティック基板と S i基板 との熱収縮率の差に基づいたせん断応力により多孔質 S i層を破断し、 分離する方法が示されている。 また、 特開 2 0 0 1 — 8 5 7 2 5号公 報では、 酸化物層を形成した S i基板上に、 網状の S i露出面を形成し、 そこから選択成長により網状膜の太陽電池を形成し、 機械的な剥離法 にて分離を行う技術が示されている。 After a semiconductor layer is formed on a basic substrate, research and development have been conducted in which the basic substrate is removed from the semiconductor layer, and the semiconductor layer is used as a subsequent semiconductor substrate. Among them, there are many reports on the technology for separating the Si substrate as a basic substrate. For example, a technology has been proposed in which a silicon solar cell thin film semiconductor layer is formed on a Si substrate by CVD, the thin film semiconductor layer is peeled off from a basic substrate, and the Si substrate is reused. For example, in Japanese Patent Application Laid-Open No. Hei 8-2-136545, a porous Si layer is formed on a Si substrate, a semiconductor layer such as a solar cell is formed thereon, and adhesives are provided above and below the semiconductor layer. A method is shown in which the porous Si layer is mechanically broken by pulling the jig in the opposite direction, and the semiconductor layer is separated from the Si substrate. Also, Japanese Patent Application Laid-Open No. H10-15021 discloses a method of breaking and separating the porous Si layer by ultrasonic irradiation with the same structure. Also, in Japanese Patent Application Laid-Open No. Hei 10-1990, a plastic substrate is adhered on a solar cell layer with the same structure, and by cooling the plastic substrate, the heat between the plastic substrate and the Si substrate is reduced. A method is described in which the porous Si layer is broken and separated by shear stress based on the difference in shrinkage. Also, in Japanese Patent Application Laid-Open No. 2000-185757, a reticulated Si exposed surface is formed on an Si substrate on which an oxide layer is formed. From this, a technique of forming a reticulated solar cell by selective growth and separating it by a mechanical peeling method is disclosed.

次に、 サファイア基板上に形成した窒化ガリゥム半導体層からサフ アイァ基板を分離する技術開発がなされている。 例えば、 窒化ガリウ ム半導体基板を製造するための従来技術としては、 サファイア基板上 に塩化物法により厚く窒化ガリゥムを形成した後、 機械的なラッピン グ法または切削法により、 サファイア基板を削り取ってしまう方法が ある。 別の方法として、 化学的なエッチング法による基板分離法も提 案されている。 例えば、 基礎基板の上に酸化亜鉛 (ZnO)あるいは酸化 マグネシウム (MgO)などの酸化物よりなるバッファ層を介して、 窒化 ガリゥム半導体を成長させ、 このバッファ層をエッチングにより除去 するものが提案されている (特開平 7— 1 6 5 4 9 8号公報、 特開平 1 0 - 1 7 8 2 0 2号公報、 特開平 1 1 一 3 5 3 9 7号公報参照) 。 また、 上記化学的エッチング法では、 基礎基板と半導体層との分離に は時間が非常にかかることが指摘されており、 上記ェッチング法の改 良技術として、 基礎基板と半導体層との間にエッチング剤が流通する ための流通孔を備え、 エツチング時間を格段に短縮する方法が提案さ れている (特開 2 0 0 1 - 3 6 1 3 9号公報参照) 。  Next, a technique for separating a sapphire substrate from a gallium nitride semiconductor layer formed on the sapphire substrate has been developed. For example, a conventional technique for manufacturing a gallium nitride semiconductor substrate is to form a thick gallium nitride on a sapphire substrate by a chloride method and then scrape the sapphire substrate by a mechanical lapping method or a cutting method. There is a way. As another method, a substrate separation method using a chemical etching method has been proposed. For example, it has been proposed that a gallium nitride semiconductor is grown on a base substrate through a buffer layer made of an oxide such as zinc oxide (ZnO) or magnesium oxide (MgO) and the buffer layer is removed by etching. (See Japanese Patent Application Laid-Open Nos. Hei 7-165498, Hei 10-178202, and Hei 11-35797). In addition, it has been pointed out that the above chemical etching method requires a very long time to separate the base substrate and the semiconductor layer. As an improved technique of the etching method, etching between the base substrate and the semiconductor layer is considered. There has been proposed a method of providing a flow hole for the flow of the agent and significantly shortening the etching time (see Japanese Patent Application Laid-Open No. 2001-36939).

しかしながら、 前記従来技術では、 歩留まりよく半導体層を基礎基 板から取除く ことは困難であった。 例えば、 機械的ラッピング法では 基板に反りが生じてくるので、 大面積を維持した状態でのラッビング が難しく、 現実的でなかった。  However, it is difficult to remove the semiconductor layer from the base substrate with a high yield in the conventional technology. For example, the mechanical lapping method warps the substrate, making rubbing with a large area difficult is difficult and impractical.

前記の改良された化学的エッチング法 (特開 2 0 0 1 - 3 6 1 3 9 号公報) は従来の事実上不可能な程のエッチング時間の長さを劇的に 短縮する技術であるが、 基礎基板と半導体層との間に精緻な構造を作 り込まなければならない欠点を有していた。 例えば、 典型的な改良型 エッチング分離法による半導体積層基板の構造を第 1図に示す。 第 1 図の従来の半導体積層基板の作製工程と分離工程とを簡単に述べる。 まず、 サファイア基板からなる基礎基板 1上に窒化アルミニウム (A1 N)薄膜層 3 2を分離層として形成し、 その上に窒化ガリウム (GaN)バ ッファ層 3 3を 2 m 程度成長させる。 次に、 標準的なリソグラフィ 工程とガスエッチングにより上記窒化物層をストライプ状または島状 に形成する。 次に、 酸化物を CVD 法により一様に堆積し、 気相プラズ マエッチングにより垂直エッチングを施し、 上記ストライプ状または 島状の窒化物の側壁に酸化物の成長防止膜 3 4を形成する。 次に、 M0 CVD または塩化物法により窒化ガリウム層を堆積してゆく と、 側壁に は酸化物の成長防止膜 3 4の存在により堆積せず、 ストライプの上部 のみに横広がりを伴いながら堆積し、 やがてストライプ同士が合体し て窒化ガリゥム半導体層 2が形成され、 酸化物で覆われた初期のスト ライプはそのまま保存され、 流通孔としてストライプ上の凹部 4が形 成される。 The above-mentioned improved chemical etching method (Japanese Patent Application Laid-Open No. 2001-36939) is a technique for dramatically shortening the length of etching time, which is virtually impossible in the past. However, it has a disadvantage that a precise structure must be formed between the base substrate and the semiconductor layer. For example, a typical improved FIG. 1 shows the structure of the semiconductor laminated substrate by the etching separation method. The steps of manufacturing and separating the conventional semiconductor laminated substrate shown in FIG. 1 will be briefly described. First, an aluminum nitride (A1N) thin film layer 32 is formed as a separation layer on a base substrate 1 made of a sapphire substrate, and a gallium nitride (GaN) buffer layer 33 is grown thereon to about 2 m. Next, the nitride layer is formed in a stripe or island shape by a standard lithography process and gas etching. Next, an oxide is uniformly deposited by a CVD method, and vertical etching is performed by vapor phase plasma etching to form an oxide growth prevention film 34 on the side wall of the stripe-shaped or island-shaped nitride. Next, when a gallium nitride layer is deposited by M0 CVD or the chloride method, the gallium nitride layer is not deposited on the side wall due to the presence of the oxide growth preventing film 34, but is deposited only on the upper portion of the stripe while spreading laterally. Eventually, the stripes unite to form the gallium nitride semiconductor layer 2, the initial stripe covered with the oxide is preserved as it is, and the recess 4 on the stripe is formed as a flow hole.

基礎基板 1 と窒化ガリゥム半導体層 2とを分離する工程は、 次のと おりである。 まず、 フッ酸などの水溶液をストライプ上の凹部 4に通 し、 側壁の成長防止膜 3 4をエッチングにより取除く。 次に、 このフ ッ酸を排除した後アル力リ系エッチング液をこの凹部 4に通し、 窒化 アルミニウム薄膜層 3 2をエッチングすると、 ついに基礎基板 1が分 離される。  The steps for separating the base substrate 1 and the gallium nitride semiconductor layer 2 are as follows. First, an aqueous solution of hydrofluoric acid or the like is passed through the concave portions 4 on the stripes, and the growth preventing film 34 on the side walls is removed by etching. Next, after removing the hydrofluoric acid, an Al-based etching solution is passed through the concave portion 4 to etch the aluminum nitride thin film layer 32, whereby the basic substrate 1 is finally separated.

以上に示されるように、 従来技術では、 窒化ガリウム半導体層を得 るために多数の CVD プロセス、 リソグラフィ、 エッチング工程が繰り 返し用いられる。 これにより、 歩留まりの低下と製造コストの上昇要 因となっていた。  As shown above, in the prior art, a number of CVD processes, lithography, and etching steps are repeatedly used to obtain a gallium nitride semiconductor layer. This has led to lower yields and higher manufacturing costs.

本発明はかかる問題点に鑑みてなされたもので、 その目的は、 簡単 な液体の熱膨張または相転移に基づく体積膨張の圧力を用いて容易に 基礎基板と半導体層などの結晶層とを分離することができる結晶積層 基板、 それを用いて得られる半導体層などの結晶層および半導体素子 などの素子ならびにそれらの製造方法を提供することである。 発明の開示 The present invention has been made in view of such a problem, and its purpose is to provide a simple Crystal substrate that can easily separate the base substrate from the crystal layer such as a semiconductor layer using the pressure of volume expansion based on thermal expansion or phase transition of a liquid, and a crystal such as a semiconductor layer obtained by using the substrate. It is an object of the present invention to provide devices such as layers and semiconductor devices and methods for their manufacture. Disclosure of the invention

本発明による結晶積層基板は、 基礎基板上に結晶層が形成された結 晶積層基板であって、 結晶層と基礎基板との間に、 液体が侵入し、 そ の液体の熱膨張または相転移に基づく膨張圧力により、 結晶層と基礎 基板とを分離するための空隙を有し、 この空隙は深さが 3 以上で 巾が 3 m以上であるものである。  A crystal laminated substrate according to the present invention is a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid undergoes thermal expansion or phase transition. Has a gap for separating the crystal layer and the base substrate by the expansion pressure based on the above, and the gap has a depth of 3 or more and a width of 3 m or more.

本発明による結晶層は、 基礎基板上に結晶層が形成され、 結晶層と 基礎基板との間に液体が侵入するための空隙を有する結晶積層基板の 空隙に液体を侵入させ、 その液体の熱膨張または相転移に基づく膨張 圧力により、 基礎基板から分離したものである。  In the crystal layer according to the present invention, a crystal layer is formed on a base substrate, and the liquid is caused to penetrate into the space of the crystal laminated substrate having a space for liquid to enter between the crystal layer and the base substrate, and the heat of the liquid is caused. It is separated from the base substrate by expansion pressure based on expansion or phase transition.

本発明による素子は、 基礎基板上に結晶素子層が形成され、 結晶素 子層と基礎基板との間に液体が侵入するための空隙を有する結晶積層 基板の空隙に液体を侵入させ、 その液体の熱膨張または相転移に基づ く膨張圧力により、 基礎基板から分離したものである。  In the device according to the present invention, a crystal element layer is formed on a base substrate, and the liquid is caused to enter the gap of the crystal laminated substrate having a gap for the liquid to enter between the crystal element layer and the base substrate. It is separated from the base substrate by expansion pressure based on thermal expansion or phase transition of the substrate.

本発明による結晶積層基板の製造方法は、 基礎基板上に結晶層が形 成された結晶積層基板の製造方法であって、 結晶層と基礎基板との間 に、 液体が侵入し、 その液体の熱膨張または相転移に基づく膨張圧力 により、 結晶層と基礎基板とを分離するための空隙を形成する工程を 含むものである。  A method for manufacturing a crystal laminated substrate according to the present invention is a method for manufacturing a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate, and the liquid The method includes a step of forming a gap for separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition.

本発明による結晶層の製造方法は、 基礎基板上に結晶層が形成され 、 結晶層と基礎基板との間に空隙を有する結晶積層基板を形成するェ 程と、 その空隙に液体を侵入させ、 その液体の熱膨張または相転移に 基づく膨張圧力により、 結晶層と基礎基板とを分離する工程を含むも のである。 In the method for producing a crystal layer according to the present invention, a crystal layer is formed on a base substrate, and a crystal laminated substrate having a gap between the crystal layer and the base substrate is formed. And a step of injecting a liquid into the void and separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.

本発明による素子の製造方法は、 基礎基板上に結晶素子層が形成さ れ、 結晶素子層と基礎基板との間に空隙を有する結晶積層基板を形成 する工程と、 その空隙に液体を侵入させ、 その液体の熱膨張または相 転移に基づく膨張圧力により、 結晶素子層と基礎基板とを分離するェ 程を含むものである。  In the method for manufacturing an element according to the present invention, a crystal element layer is formed on a basic substrate, a crystal laminated substrate having a gap between the crystal element layer and the basic substrate is formed, and a liquid is caused to enter the gap. The method includes a step of separating the crystal element layer from the base substrate by an expansion pressure based on thermal expansion or phase transition of the liquid.

本発明において、 結晶積層基板に形成する空隙は、 液体が流通する 形状であれば、 基本的にはどのような形状のものであってもよいが、 例えば、 線状あるいはストライプ状や格子状であってよく、 これらが 分散して形成される。 この空隙は、 結晶層あるいは結晶素子層を基礎 基板から容易に分離する観点からは、 好適には、 深さは 3 以上 2 0 以下で巾は 3 〃m以上 2 0〃m以下に選ばれる。 また、 この空 隙は、 典型的には、 6 以上 4 0 i m以下のピッチで周期的に形成 され、 その場合空隙の巾とその間の凸部の巾とは例えばほぼ同一に選 ばれる。  In the present invention, the voids formed in the crystal-laminated substrate may be basically any shape as long as the shape allows a liquid to flow therethrough.For example, the voids may be linear, stripe-shaped, or lattice-shaped. These may be dispersed and formed. From the viewpoint of easily separating the crystal layer or the crystal element layer from the basic substrate, the gap is preferably selected to have a depth of 3 to 20 and a width of 3 to 20 μm. The gaps are typically formed periodically at a pitch of 6 or more and 40 im or less. In this case, the width of the gap and the width of the convex portion between them are selected, for example, to be substantially the same.

この空隙は次のようにして形成することができる。 すなわち、 例え ば、 基礎基板上に凹凸の溝を刻み、 その上に結晶層あるいは結晶素子 層を形成するときにその溝の部分が積層を免れることを利用して空隙 を形成することができる。 あるいは、 平坦な基礎基板上に空隙形成用 の結晶層を形成した後、 この空隙形成用の結晶層に凹凸の溝を刻み、 その上に更に目的とする結晶層を積層するときに前記溝の部分が積層 を免れることを利用しても、 空隙を形成することができる。 更に、 平 坦な基礎基板上に空隙形成用の結晶層を形成した後、 この空隙形成用 の結晶層を貫いて基礎基板に至る凹凸の溝を刻み、 その上に更に目的 とする結晶層を積層するときにその溝の部分が積層を免れることを利 用することによつても、 空隙を形成することができる。 This gap can be formed as follows. That is, for example, a void can be formed by forming an uneven groove on the base substrate and using the fact that the crystal layer or the crystal element layer avoids lamination when forming a crystal layer or a crystal element layer thereon. Alternatively, after forming a crystal layer for forming voids on a flat base substrate, grooves of irregularities are cut in the crystal layer for forming voids, and when the target crystal layer is further laminated thereon, A gap can be formed even by utilizing the fact that a portion is prevented from being laminated. Further, after forming a crystal layer for forming voids on a flat base substrate, grooves of irregularities reaching the base substrate through the crystal layer for forming voids are cut, and furthermore, an objective is formed thereon. The gap can also be formed by utilizing the fact that the groove portion avoids the lamination when the crystal layers are laminated.

結晶層あるいは結晶素子層は、 典型的には、 半導体層あるいは半導 体素子層であるが、 用途などに応じて、 半導体以外の材料からなるも のを用いてもよい。 同様に、 素子は、 典型的には、 半導体素子である が、 その他の各種の素子であってもよい。  The crystal layer or the crystal element layer is typically a semiconductor layer or a semiconductor element layer, but may be made of a material other than a semiconductor depending on the application. Similarly, the element is typically a semiconductor element, but may be other various elements.

基礎基板は、 その上の結晶層あるいは結晶素子層の形成に必要な材 料ならば、 どのような材料のものであってもよい。 具体的には、 例え ば、 結晶層として窒化物系半導体層を形成する場合であれば、 サファ ィァ、 シリコン、 スピネル、 ネオジムガレート、 リチウムガレート、 リチウムアルミネート、 ΙΠ - V族窒化物、 ΠΙ - V族化合物あるいは酸化ケ ィ素等を用いることができる。 ここで、 窒化物系半導体層は、 典型的 には、 ガリ ウム (Ga) 、 アルミニウム (A1 ) 、 ホウ素 (B)およびイ ン ジゥム (in) からなる群より選ばれた少なくとも 1種の III族元素と、 窒素 (N)、 リ ン (P)およびヒ素(As)からなる群より選ばれた少なく と も窒素を含む V族元素とを含む πι -ν族窒化物半導体よりなる。 窒化物 系半導体以外の半導体層としては、 シリコン、 ゲルマニウムまたはそ の混晶からなる半導体層が挙げられる。  The base substrate may be made of any material necessary for forming a crystal layer or a crystal element layer thereon. Specifically, for example, when a nitride-based semiconductor layer is formed as a crystal layer, sapphire, silicon, spinel, neodymium gallate, lithium gallate, lithium aluminate, ΙΠ-V nitride, 、 -Group V compounds or silicon oxides can be used. Here, the nitride-based semiconductor layer is typically made of at least one group III material selected from the group consisting of gallium (Ga), aluminum (A1), boron (B), and indium (in). It is composed of a πι-ν group nitride semiconductor containing an element and at least a group V element containing nitrogen selected from the group consisting of nitrogen (N), phosphorus (P) and arsenic (As). Examples of the semiconductor layer other than the nitride-based semiconductor include a semiconductor layer made of silicon, germanium, or a mixed crystal thereof.

結晶層として半導体層を用いる場合、 その半導体層は不純物ドーピ ングを行わなくてもよいが、 p型不純物や n型不純物あるいは半絶縁 型とするために遷移金属などのドーピングを行うことによって、 積極 的に伝導の型を制御することができる。  When a semiconductor layer is used as the crystal layer, the semiconductor layer does not have to be doped with impurities.However, by doping a p-type impurity, an n-type impurity, or a transition metal in order to obtain a semi-insulating type, active The type of conduction can be controlled effectively.

半導体層を形成するとき、 その中に素子構造、 例えば、 電界効果ト ランジス夕、 バイポーラ トランジスタ、 受光素子、 発光ダイォードぁ るいは半導体レーザ構造などの素子構造を形成しておく こともでき、 これが半導体素子層である。 空隙に侵入あるいは流通させる液体は水が最も簡便であるが、 相転 移温度の調節のため種々の混合溶液を用いることができる。 具体的に は、 この液体としては、 例えば、 水、 アルコール、 ケトン類、 エーテ ル類、 アミン類、 石油類および塩からなる群より選ばれた少なく とも 1種を用いることができ、 典型的にはエタノールおよびメタノールの うちの少なく とも 1種を含む水溶液または水を用いることができる。 ここで、 水にエタノールまたはメタノールを添加することにより、 固 化温度を低下させることができる。 また、 ケトン類、 エーテル類、 ァ ミン類、 石油類、 塩などのうちから、 膨張率や粘性などの制御のため に最適なものを選択することができる。 When a semiconductor layer is formed, a device structure such as a field effect transistor, a bipolar transistor, a light receiving device, a light emitting diode or a semiconductor laser structure can be formed therein. It is an element layer. Water is the simplest liquid to penetrate or flow into the voids, but various mixed solutions can be used to adjust the phase transition temperature. Specifically, as the liquid, for example, at least one selected from the group consisting of water, alcohols, ketones, ethers, amines, petroleums and salts can be used. Can be an aqueous solution or water containing at least one of ethanol and methanol. Here, the solidification temperature can be lowered by adding ethanol or methanol to the water. In addition, from ketones, ethers, amines, petroleums, salts, and the like, the most suitable one can be selected for controlling the expansion coefficient and viscosity.

相転移の形態は、 液体から固体への転移ではなく、 温度上昇による 液体から気体による転移を用いることも可能である。  The form of the phase transition is not a liquid-to-solid transition, but a liquid-to-gas transition due to temperature rise can be used.

相転移を起こさせる冷却媒体としては、 例えば、 エタノール、 メタ ノールまたはその混合液体または液体窒素または液体空気を含む冷却 媒体を用いてもよいし、 冷却した窒素、 酸素または乾燥空気を含む冷 却媒体を用いてもよい。 後者の冷却したガスを吹き付けるようにすれ ば、 冷却速度を場所ごとに制御することができ、 分離工程を厳密に制 御することができる。  As the cooling medium causing the phase transition, for example, a cooling medium containing ethanol, methanol or a mixed liquid thereof, liquid nitrogen or liquid air may be used, or a cooling medium containing cooled nitrogen, oxygen or dry air may be used. May be used. If the latter cooled gas is blown, the cooling rate can be controlled for each location, and the separation process can be strictly controlled.

必要に応じて、 結晶積層基板の一部を遮熱材で覆い、 熱膨張速度ま たは相転移速度を場所的に制御するようにしてもよい。 このようにす れば、 冷却速度を場所ごとに制御することができ、 分離工程を厳密に 制御することができる。  If necessary, a part of the crystal laminated substrate may be covered with a heat shield to locally control the thermal expansion rate or the phase transition rate. In this way, the cooling rate can be controlled for each location, and the separation step can be strictly controlled.

上述のように構成された本発明による結晶積層基板は、 結晶層ある いは結晶素子層と基礎基板との間に、 液体が侵入し、 その液体の熱膨 張または相転移に基づく膨張圧力により、 結晶層あるいは結晶素子層 と基礎基板とを分離するための空隙を有しているので、 その空隙に液 体を侵入あるいは流通させた後、 結晶積層基板の温度を変化させるこ とにより、 その液体の熱膨張または相転移に基づく膨張圧力により、 基礎基板から結晶層あるいは結晶素子層が分離されることになる。 図面の簡単な説明 In the crystal laminated substrate according to the present invention configured as described above, a liquid penetrates between a crystal layer or a crystal element layer and a base substrate, and is subjected to expansion pressure based on thermal expansion or phase transition of the liquid. Since there is a gap for separating the crystal layer or the crystal element layer from the base substrate, After the body penetrates or circulates, by changing the temperature of the crystal laminated substrate, the crystal layer or crystal element layer is separated from the base substrate by the expansion pressure based on the thermal expansion or phase transition of the liquid. Become. BRIEF DESCRIPTION OF THE FIGURES

第 1図は、 従来の半導体積層基板の構成を示す断面図、 第 2図は、 本発明の第 1の実施形態による半導体積層基板の構成を示す断面図、 第 3図は、 本発明の第 2の実施形態による半導体積層基板の構成を示 す断面図、 第 4図は、 本発明の第 3の実施形態による半導体積層基板 の構成を示す断面図、 第 5図は、 本発明の第 4の実施形態による半導 体積層基板の構成を示す断面図である。 発明を実施するための最良の形態  FIG. 1 is a cross-sectional view showing a configuration of a conventional semiconductor multilayer substrate, FIG. 2 is a cross-sectional view showing a configuration of a semiconductor multilayer substrate according to a first embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a second embodiment; FIG. 4 is a cross-sectional view illustrating a configuration of a semiconductor multilayer substrate according to a third embodiment of the present invention; FIG. 4 is a cross-sectional view showing a configuration of a semiconductor laminated substrate according to the embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

以下、 本発明の実施の形態について、 図面を参照して詳細に説明す る。  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第 2図は、 本発明の第 1の実施形態による半導体積層基板の断面図 である。 図において、 1はサファイア基板からなる基礎基板、 2は窒 化ガリゥム半導体層、 3は基礎基板 1に形成されているストライプ状 の凸部であり、 深さは例えば約 20 m 、 ス トライプの巾は例えば約 5 u m である。 4は基礎基板 1上に形成されたストライプ状の凹部であ り、 巾は例えば約 5 w in である。 このような構成を有する半導体積層 基板は、 例えば、 次のようにして製造することができる。  FIG. 2 is a sectional view of the semiconductor multilayer substrate according to the first embodiment of the present invention. In the figure, 1 is a base substrate made of a sapphire substrate, 2 is a gallium nitride semiconductor layer, 3 is a stripe-shaped projection formed on the base substrate 1, and has a depth of, for example, about 20 m and a stripe width. Is about 5 um, for example. Reference numeral 4 denotes a stripe-shaped concave portion formed on the basic substrate 1 and has a width of, for example, about 5 win. The semiconductor laminated substrate having such a configuration can be manufactured, for example, as follows.

まず、 例えば C面のサファイア基板 1 を公知のリソグラフィ技術と イオンミ リング法とによりパターユングしてストライプ状の凸部 3を 形成し、 次に、 公知の M O C V D法により、 窒化ガリゥムバッファ層 を 550 °Cで 30nm積層し、 温度を 1080°Cとして、 窒化ガリゥムを 0. 5 u m 積層する。 例えば、 ガリゥム原料としてトリメチルガリウム(TMG) を、 窒素原料としてアンモニア(NH3) を、 そしてキヤリァガスとして 窒素と水素を用いる。 次に、 公知のハイ ドライ ド法により、 1000°Cに て、 窒化ガリゥムを 300 z m 成長させる。 例えば、 ガリゥム原料であ る塩化ガリウムは、 炉の上流で金属ガリウムと塩酸ガスとを反応させ る。 窒素原料は例えばアンモニアガスを用いる。 ここでは不純物ドー ビングは行わない。 成長条件を適切にとることにより、 ストライプ上 から成長した窒化ガリウムは、 横方向に広がりながら成長し、 合体し 平坦な窒化ガリウム半導体層 2となり、 その下に空隙、 すなわちスト ライプ状の凹部 4を残す。 First, for example, the C-plane sapphire substrate 1 is patterned by a known lithography technique and an ion milling method to form a stripe-shaped convex portion 3 .Next, a known nitrided buffer layer is formed at 550 ° C. by a known MOCVD method. At a temperature of 1080 ° C and a gallium nitride of 0.5 u m Laminate. For example, trimethylgallium (TMG) is used as a gallium raw material, ammonia (NH 3 ) is used as a nitrogen raw material, and nitrogen and hydrogen are used as carrier gases. Next, 300 gm of gallium nitride is grown at 1000 ° C. by a known hydride method. For example, gallium chloride, which is a raw material for gallium, causes metal gallium to react with hydrochloric acid gas upstream of the furnace. As the nitrogen source, for example, ammonia gas is used. No impurity doping is performed here. By properly setting the growth conditions, gallium nitride grown from above the stripes grows while spreading in the horizontal direction, and coalesce to form a flat gallium nitride semiconductor layer 2, and voids, that is, stripe-shaped recesses 4 are formed thereunder. leave.

次に、 窒化ガリゥム半導体層 2は次の工程により基礎基板 1から分 離される。 まず、 簡単な減圧装置に接続された容器に上記半導体積層 基板を置き、 水を入れる。 この時点では、 上記半導体積層基板と水と は分離しておく。 1 kPa 程度以下まで減圧したところで、 上記半導体 積層基板を水の中に浸漬してから大気圧に戻す。 以上の操作により、 ストライプ状の凹部 4の中に水が充填される。 次に、 この半導体積層 基板を一 10°Cから一 50°C程度に冷却したエタノールに浸漬し、 凹部 4 の中の水を固化膨張させる。 この水の固化に伴う約 9 %の体積膨張に より窒化ガリゥム半導体層 2はストライプの接合面より解離する。 このようにして基礎基板 1から分離された窒化ガリゥム半導体層 は、 窒化ガリゥム基板として、 種々の応用に用いることができる。 次に、 本発明の第 2の実施形態においては、 第 3図に示すごとく、 平坦な基礎基板 1 の上にまず、 例えば数/ / m の巾の、 例えば窒化ガリ ゥムからなる半導体ストライプ 3 1 を既知の方法により形成し、 次に 厚膜の窒化ガリウム半導体層 2を形成する。 半導体ストライプ 3 1の 深さと巾とを適当に制御することにより半導体ストライプ 3 1の間の 凹部では、 窒化ガリウム半導体層 2の形成時に積層を免れ、 空隙、 す なわちストライプ状の凹部 4が生じる。 Next, the gallium nitride semiconductor layer 2 is separated from the base substrate 1 by the following steps. First, the semiconductor laminated substrate is placed in a container connected to a simple decompression device, and water is added. At this point, the semiconductor laminated substrate is separated from water. When the pressure is reduced to about 1 kPa or less, the semiconductor laminated substrate is immersed in water and then returned to the atmospheric pressure. By the above operation, water is filled into the stripe-shaped concave portions 4. Next, the semiconductor laminated substrate is immersed in ethanol cooled to about 110 ° C. to about 150 ° C. to solidify and expand water in the recess 4. The gallium nitride semiconductor layer 2 is dissociated from the bonding surface of the stripe due to the volume expansion of about 9% due to the solidification of water. The gallium nitride semiconductor layer separated from the base substrate 1 in this manner can be used for various applications as a gallium nitride substrate. Next, in a second embodiment of the present invention, as shown in FIG. 3, a semiconductor stripe 3 made of, for example, gallium nitride having a width of, for example, several 1 is formed by a known method, and then a thick gallium nitride semiconductor layer 2 is formed. By appropriately controlling the depth and width of the semiconductor stripe 31, the distance between the semiconductor stripes 31 is controlled. In the recess, the lamination is avoided when the gallium nitride semiconductor layer 2 is formed, and a void, that is, a stripe-shaped recess 4 is generated.

上記以外のことは、 その性質に反しない限り、 第 1の実施形態で述 ベたことが成立する。  Except for the above, unless otherwise contradicted, the description of the first embodiment holds.

また、 本発明の第 3の実施形態においては、 第 4図のごとく、 数 m 巾の半導体ストライプ 3 1 を形成するとき、 下地の基礎基板 1 まで 掘り下げて、 深くストライプ状の凸部 3を形成する。  Further, in the third embodiment of the present invention, as shown in FIG. 4, when forming a semiconductor stripe 31 having a width of several meters, the semiconductor stripe 31 is dug down to the underlying base substrate 1 to form a deep stripe-shaped projection 3. I do.

上記以外のことは、 その性質に反しない限り、 第 1の実施形態で述 ベたことが成立する。  Except for the above, unless otherwise contradicted, the description of the first embodiment holds.

更に、 本発明の第 4の実施形態においては、 第 5図のごとく、 基礎 基板 1 としてサファイア基板などの下地基板 1 a上に窒化ガリゥム半 導体層 1 bを形成し、 この窒化ガリゥム半導体層 1 bの途中の深さま で掘り下げて、 数; 巾の半導体ストライプ 3 1 を形成する。  Further, in the fourth embodiment of the present invention, as shown in FIG. 5, a gallium nitride semiconductor layer 1 b is formed on a base substrate 1 a such as a sapphire substrate as a base substrate 1. Digging down to a depth in the middle of b to form a semiconductor stripe 31 of a number;

上記以外のことは、 その性質に反しない限り、 第 1の実施形態で述 ベたことが成立する。  Except for the above, unless otherwise contradicted, the description of the first embodiment holds.

以上、 本発明の実施形態につき具体的に説明したが、 本発明は上述 の実施形態に限定されるものではなく、 本発明の技術的思想に基づく 各種の変形が可能である。  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible.

以上説明したように、 本発明によれば、 基礎基板上に結晶層あるい は結晶素子層が形成され、 その結晶層あるいは結晶素子層と基礎基板 との間に空隙を有するようにしたので、 その空隙に液体を侵入させる ことで、 その液体の熱膨張または相転移などによる自発的な膨張圧力 により、 容易に結晶層あるいは結晶素子層を分離することができる。 よって、 この結晶積層基板を用いて、 結晶層あるいは結晶素子層を製 造することにより、 極めて容易に半導体基板などの結晶基板あるいは 半導体素子などの素子を製造することができる。 また、 空隙に侵入させる液体として、 エタノールおよびメ タノール のうちの少なく とも 1種を含む水溶液または水を用いることにより、 従来のエツチング液のような高価で環境負荷の懸念のあるような薬剤 を用いる必要がなくなるので、 製造コス 卜の低減を図ることができる とともに、 環境負荷を大幅に軽減することができる。 As described above, according to the present invention, a crystal layer or a crystal element layer is formed on a base substrate, and a gap is formed between the crystal layer or the crystal element layer and the base substrate. By injecting the liquid into the void, the crystal layer or the crystal element layer can be easily separated by spontaneous expansion pressure due to thermal expansion or phase transition of the liquid. Therefore, by manufacturing a crystal layer or a crystal element layer using this crystal laminated substrate, it is possible to extremely easily manufacture a crystal substrate such as a semiconductor substrate or an element such as a semiconductor element. In addition, by using an aqueous solution or water containing at least one of ethanol and methanol as a liquid to be penetrated into the void, an expensive chemical such as a conventional etching liquid and having a concern about environmental load is used. Since it is not necessary, the manufacturing cost can be reduced and the environmental load can be significantly reduced.

また、 結晶層として窒化ガリゥムなどの III— V族窒化物半導体より なるものを用いることにより、 窒化ガリゥム半導体基板などの ΙΠ— V 族窒化物半導体基板を容易に得ることができ、 その上に作製する半導 体素子は放熱性に優れたものとなるとともに、 基板の劈開を利用する ことができるので優れた半導体素子を容易に製造することができると いう効果がある。  Also, by using a crystal layer made of a group III-V nitride semiconductor such as gallium nitride, a group V nitride semiconductor substrate such as a gallium nitride semiconductor substrate can be easily obtained, and a crystal layer can be formed thereon. The resulting semiconductor element has excellent heat dissipation properties, and has an effect that an excellent semiconductor element can be easily manufactured because the cleavage of the substrate can be utilized.

Claims

請 求 の 範 囲 The scope of the claims 1 . 基礎基板上に結晶層が形成された結晶積層基板であって、 前記結 晶層と前記基礎基板との間に、 液体が侵入し、 その液体の熱膨張また は相転移に基づく膨張圧力により、 前記結晶層と前記基礎基板とを分 離するための空隙を有し、 この空隙は深さが 3 m以上で巾が 3 以上であることを特徴とする結晶積層基板。 1. A crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid enters between the crystal layer and the base substrate, and an expansion pressure based on thermal expansion or phase transition of the liquid. A gap for separating the crystal layer and the base substrate, wherein the gap has a depth of 3 m or more and a width of 3 or more. 2 . 前記空隙の深さは 3 m以上 2 0 ( m以下で巾が 3 m以上 2 0 11 m以下であることを特徴とする請求の範囲第 1項記載の結晶積層基 板。  2. The crystal laminated substrate according to claim 1, wherein the depth of the void is 3 m or more and 20 m or less and the width is 3 m or more and 201 m or less. 3 . 前記空隙は 6 以上 4 0 ; u m以下のピッチで周期的に形成され ていることを特徴とする請求の範囲第 2項記載の結晶積層基板。  3. The crystal laminated substrate according to claim 2, wherein said voids are formed periodically at a pitch of 6 or more; 40; um or less. 4 . 前記基礎基板は、 サファイア、 シリコン、 スピネル、 ネオジムガ レート、 リチウムガレート、 リチウムアルミネート、 III - V族窒化物、 III - V族半導体、 あるいは酸化ケィ素よりなることを特徴とする請求の 範囲第 1項記載の結晶積層基板。  4. The base substrate is made of sapphire, silicon, spinel, neodymium gallate, lithium gallate, lithium aluminate, III-V nitride, III-V semiconductor, or silicon oxide. 2. The crystal laminated substrate according to item 1. 5 . 前記結晶層は、 ガリウム、 アルミニウム、 ホウ素およびィンジゥ ムからなる群より選ばれた少なく とも 1種の III族元素と、 窒素、 リン およびヒ素からなる群より選ばれた少なく とも窒素を含む V族元素と を含む III - V族窒化物よりなることを特徴とする請求の範囲第 1項記載  5. The crystalline layer contains at least one group III element selected from the group consisting of gallium, aluminum, boron and indium, and at least nitrogen selected from the group consisting of nitrogen, phosphorus and arsenic. 2. The compound according to claim 1, wherein the nitride is made of a group III-V nitride containing a group III element. 6 . 前記結晶層はシリコンおよびゲルマ二ゥムのうちの少なく とも 1 種からなる半導体よりなることを特徴とする請求の範囲第 1項記載の 6. The method according to claim 1, wherein the crystal layer is made of a semiconductor comprising at least one of silicon and germanium. 7 . 前記空隙は、 前記基礎基板上に凹凸の溝が刻まれ、 その上に前記 結晶層を積層するときに前記溝の部分が積層を免れることにより形成 されてなることを特徴とする請求の範囲第 1項記載の結晶積層基板。7. The voids are formed by forming concave and convex grooves on the base substrate, and when laminating the crystal layer thereon, the groove portions avoid lamination. 2. The crystal laminated substrate according to claim 1, wherein the substrate is formed. 8 . 前記空隙は、 平坦な前記基礎基板上に結晶層を形成した後、 この 結晶層に凹凸の溝が刻まれ、 その上に更に前記結晶層を積層するとき に前記溝の部分が積層を免れることにより形成されてなることを特徴 とする請求の範囲第 1項記載の結晶積層基板。 8. The voids are formed by forming a crystal layer on the flat base substrate, and then forming an uneven groove in the crystal layer. When the crystal layer is further stacked on the crystal layer, the groove portion is stacked. 2. The crystal-stacked substrate according to claim 1, wherein the substrate is formed by excluding. 9 . 前記空隙は、 平坦な前記基礎基板上に結晶層を形成した後、 この 結晶層を貫いて前記基礎基板に至る凹凸の溝が刻まれ、 その上に更に 前記結晶層を積層するときに前記溝の部分が積層を免れることにより 形成されてなることを特徴とする請求の範囲第 1項記載の結晶積層基 板。  9. After forming a crystal layer on the flat base substrate, the voids are formed with concave and convex grooves extending through the crystal layer to the base substrate, and when the crystal layer is further laminated thereon, 2. The crystal laminated substrate according to claim 1, wherein said groove portion is formed by avoiding lamination. 1 0 . 前記空隙は、 線状または格子状に分散して形成されていること を特徴とする請求の範囲第 7項、 第 8項又は第 9項記載の結晶積層基 板。  10. The crystal laminated substrate according to claim 7, 8 or 9, wherein the voids are formed in a linear or lattice form. 1 1 . 前記液体は、 水、 アルコール、 ケトン類、 エーテル類、 ァミン 類、 石油類および塩から群より選ばれた少なく とも 1種を含むことを 特徴とする請求の範囲第 1項記載の結晶積層基板。  11. The crystal according to claim 1, wherein the liquid contains at least one selected from the group consisting of water, alcohols, ketones, ethers, amines, petroleums and salts. Laminated substrate. 1 2 . 前記液体は、 エタノールおよびメ夕ノールのうちの少なく とも 1種を含む水溶液または水であることを特徴とする請求の範囲第 1項 記載の結晶積層基板。  12. The crystal laminated substrate according to claim 1, wherein the liquid is an aqueous solution or water containing at least one of ethanol and methanol. 1 3 . 基礎基板上に結晶層が形成され、 前記結晶層と前記基礎基板と の間に液体が侵入するための空隙を有する結晶積層基板の前記空隙に 液体を浸入させ、 その液体の熱膨張または相転移に基づく膨張圧力に より前記基礎基板から分離したことを特徴とする結晶層。  13 3. A crystal layer is formed on the base substrate, and the liquid penetrates into the space of the crystal laminated substrate having a space for liquid to enter between the crystal layer and the base substrate, and the liquid expands thermally. Alternatively, the crystal layer is separated from the base substrate by an expansion pressure based on a phase transition. 1 4 . 前記結晶層は、 ガリウム、 アルミニウム、 ホウ素およびインジ ゥムからなる群より選ばれた少なく とも 1種の ΠΙ族元素と、 窒素、 リ ンおよぴヒ素からなる群より選ばれた少なく とも窒素を含む V族元素 とを含む ΠΙ— V族窒化物よりなることを特徴とする請求の範囲第 1 3 項記載の結晶層。 14. The crystalline layer comprises at least one element selected from the group consisting of gallium, aluminum, boron, and indium, and at least one element selected from the group consisting of nitrogen, phosphorus, and arsenic. Group V element containing nitrogen 14. The crystal layer according to claim 13, wherein the crystal layer is made of a Group V nitride containing: 1 5 . 前記結晶層はシリコンおよびゲルマニウムのうちの少なく とも 1種からなる半導体よりなることを特徴とする請求の範囲第 1 3項記 載の結晶層。  15. The crystal layer according to claim 13, wherein the crystal layer is made of a semiconductor made of at least one of silicon and germanium. 1 6 . 基礎基板上に結晶素子層が形成され、 前記結晶素子層と前記基 礎基板との間に液体が侵入するための空隙を有する結晶積層基板の前 記空隙に液体を浸入させ、 その液体の熱膨張または相転移に基づく膨 張圧力により上記基礎基板から分離したことを特徴とする素子。  16. A crystal element layer is formed on the base substrate, and the liquid penetrates into the gaps of the crystal laminated substrate having a gap for liquid to enter between the crystal element layer and the base substrate. An element which is separated from the base substrate by an expansion pressure based on thermal expansion or phase transition of a liquid. 1 7 . 基礎基板上に結晶層が形成された結晶積層基板の製造方法であ つて、 前記結晶層と前記基礎基板との間に、 液体が侵入し、 その液体 の熱膨張または相転移に基づく膨張圧力により、 前記結晶層と前記基 礎基板とを分離するための空隙を形成する工程を含むことを特徴とす る結晶積層基板の製造方法。  17. A method for manufacturing a crystal laminated substrate in which a crystal layer is formed on a base substrate, wherein a liquid penetrates between the crystal layer and the base substrate and is based on thermal expansion or phase transition of the liquid. A method for manufacturing a crystal laminated substrate, comprising a step of forming a gap for separating the crystal layer and the base substrate by an expansion pressure. 1 8 . 前記基礎基板を、 サファイア、 シリコン、 スピネル、 ネオジム ガレート、 リチウムガレート、 リチウムアルミネート、 III - V族窒化物 、 πι -ν族半導体、 あるいは酸化ゲイ素より形成することを特徴とする 請求の範囲第 1 7項記載の結晶積層基板の製造方法。  18. The basic substrate is formed of sapphire, silicon, spinel, neodymium gallate, lithium gallate, lithium aluminate, III-V nitride, πι-ν semiconductor, or GaN. 18. The method for manufacturing a crystal laminated substrate according to item 17 above. 1 9 . 前記結晶層は、 ガリウム、 アルミニウム、 ホウ素およびインジ ゥムからなる群より選ばれた少なく とも 1種の III族元素と、 窒素、 リ ンおよびヒ素からなる群より選ばれた少なく とも窒素を含む V 族元素 とを含む III— V族窒化物よりなることを特徴とする請求の範囲第 1 7 項記載の結晶積層基板の製造方法。  19. The crystalline layer comprises at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium, and at least nitrogen selected from the group consisting of nitrogen, phosphorus and arsenic. 18. The method for producing a crystal multilayer substrate according to claim 17, comprising a group III-V nitride containing a group V element containing: 2 0 . 前記結晶層はシリコンおよびゲルマ二ゥムのうちの少なく とも 1種類からなる半導体よりなることを特徴とする請求の範囲第 1 7項 記載の結晶積層基板の製造方法。 20. The method for manufacturing a crystal laminated substrate according to claim 17, wherein said crystal layer is made of a semiconductor made of at least one of silicon and germanium. 2 1 . 前記空隙は、 前記基礎基板上に凹凸の溝が刻まれ、 その上に前 記結晶層を積層するときに前記溝の部分が積層を免れる工程を含むこ とにより形成されてなることを特徴とする請求の範囲第 1 7項記載の 結晶積層基板の製造方法。 21. The void is formed by including a step of forming an uneven groove on the base substrate and, when laminating the crystal layer thereon, excluding the groove portion from laminating. The method for producing a crystal laminated substrate according to claim 17, wherein: 2 2 . 前記空隙は、 平坦な前記基礎基板上に結晶層を形成した後、 こ の結晶層に凹凸の溝が刻まれ、 その上に更に前記結晶層を積層するこ とにより前記溝の部分が積層を免れる工程を含むことにより形成され てなることを特徴とする請求の範囲第 1 7項記載の結晶積層基板の製 造方法。  22. The gap is formed by forming a crystal layer on the flat base substrate, forming a concave and convex groove in the crystal layer, and further laminating the crystal layer thereon, thereby forming a portion of the groove. 18. The method for producing a crystal laminated substrate according to claim 17, wherein said method is formed by including a step of avoiding lamination. 2 3 . 前記空隙は、 平坦な前記基礎基板上に結晶層を形成した後、 こ の結晶層を貫いて前記基礎基板に至る凹凸の溝が刻まれ、 その上に更 に前記結晶層を積層するときに前記溝の部分が積層を免れる工程を含 むことにより形成されてなることを特徴とする請求の範囲第 1 7項記 載の結晶積層基板の製造方法。  23. The voids are formed by forming a crystal layer on the flat base substrate, and then forming an uneven groove extending through the crystal layer to the base substrate, and further laminating the crystal layer thereon. 18. The method for manufacturing a crystal laminated substrate according to claim 17, wherein the groove portion is formed by including a step of avoiding lamination when forming. 2 4 . 基礎基板上に結晶層が形成され、 前記結晶層と基礎基板との間 に空隙を有する結晶積層基板を形成する工程と、 前記空隙に液体を侵 入させ、 その液体の熱膨張または相転移に基づく膨張圧力により、 前 記結晶層と前記基礎基板とを分離する工程とを含むことを特徴とする 結晶層の製造方法。  24. A step of forming a crystal layered substrate having a crystal layer formed on the base substrate and having a gap between the crystal layer and the base substrate; Separating the crystal layer and the base substrate by an expansion pressure based on a phase transition. 2 5 . 基礎基板上に結晶素子層が形成され、 前記結晶素子層と前記基 礎基板との間に空隙を有する結晶積層基板を形成する工程と、 前記空 隙に液体を侵入させ、 その液体の熱膨張または相転移に基づく膨張圧 力により、 前記結晶層と前記基礎基板とを分離する工程とを含むこと を特徴とする素子の製造方法。  25. A step in which a crystal element layer is formed on a base substrate, a step of forming a crystal laminated substrate having a gap between the crystal element layer and the base substrate, and injecting a liquid into the gap, Separating the crystal layer and the base substrate by an expansion pressure based on thermal expansion or phase transition of the element. 2 6 . 前記相転移を起こさせる冷却媒体として、 エタノール、 メタノ ールまたはその混合液体または液体窒素または液体空気を含む冷却媒 体を用いることを特徴とする請求の範囲第 2 4項記載の結晶層の製造 方法。 26. Cooling medium containing ethanol, methanol or a mixed liquid thereof, or liquid nitrogen or liquid air as the cooling medium causing the phase transition 25. The method for producing a crystal layer according to claim 24, wherein a crystal is used. 2 7 . 前記相転移を起こさせる冷却媒体として、 エタノール、 メ 夕ノ —ルまたはその混合液体または液体窒素または液体空気を含む冷却媒 体を用いることを特徴とする請求の範囲第 2 5項記載の素子の製造方 法。  27. The cooling medium according to claim 25, wherein a cooling medium containing ethanol, methanol, a mixed liquid thereof, liquid nitrogen, or liquid air is used as the cooling medium causing the phase transition. Manufacturing method of element. 2 8 . 前記相転移を起こさせる冷却媒体として、 冷却した窒素、 酸素 または乾燥空気を含む冷却媒体を用いることを特徴とする請求の範囲 第 2 4項記載の結晶層の製造方法。  28. The method for producing a crystal layer according to claim 24, wherein a cooling medium containing cooled nitrogen, oxygen or dry air is used as the cooling medium causing the phase transition. 2 9 . 前記相転移を起こさせる冷却媒体として、 冷却した窒素、 酸素 または乾燥空気を含む冷却媒体を用いることを特徴とする請求の範囲 第 2 5項記載の素子の製造方法。  29. The method according to claim 25, wherein a cooling medium containing cooled nitrogen, oxygen, or dry air is used as the cooling medium causing the phase transition. 3 0 . 前記結晶積層基板の一部を遮熱材で覆い、 熱膨張速度または相 転移速度を場所的に制御したことを特徴とする請求の範囲第 2 6項ま たは第 2 8項記載の結晶層の製造方法。  30. The method according to claim 26 or 28, wherein a part of the crystal laminated substrate is covered with a heat shielding material, and a thermal expansion rate or a phase transition rate is locally controlled. A method for producing a crystal layer. 3 1 . 前記結晶積層基板の一部を遮熱材で覆い、 熱膨張速度または相 転移速度を場所的に制御したことを特徴とする請求の範囲第 2 7項ま たは第 2 9項記載の素子の製造方法。  31. The method according to claim 27 or 29, wherein a part of the crystal laminated substrate is covered with a heat shielding material, and a thermal expansion rate or a phase transition rate is locally controlled. A method for manufacturing an element.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009270200A (en) * 2008-05-09 2009-11-19 Advanced Optoelectronic Technology Inc Method for separating semiconductor from substrate
JP2014150211A (en) * 2013-02-04 2014-08-21 Pawdec:Kk Semiconductor element manufacturing method, insulated gate field effect transistor, insulated gate field effect transistor manufacturing method, semiconductor light-emitting element manufacturing method and solar cell manufacturing method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101337351B1 (en) * 2011-11-23 2013-12-06 주식회사 아이브이웍스 Method for manufacturing nitride based semiconductor devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101139A (en) * 1998-09-25 2000-04-07 Toshiba Corp Semiconductor light emitting element, method of manufacturing the same, and semiconductor light emitting device
JP2001036139A (en) * 1999-07-23 2001-02-09 Sony Corp Semiconductor laminated substrate, semiconductor crystal substrate, semiconductor element, and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000101139A (en) * 1998-09-25 2000-04-07 Toshiba Corp Semiconductor light emitting element, method of manufacturing the same, and semiconductor light emitting device
JP2001036139A (en) * 1999-07-23 2001-02-09 Sony Corp Semiconductor laminated substrate, semiconductor crystal substrate, semiconductor element, and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009270200A (en) * 2008-05-09 2009-11-19 Advanced Optoelectronic Technology Inc Method for separating semiconductor from substrate
JP2014150211A (en) * 2013-02-04 2014-08-21 Pawdec:Kk Semiconductor element manufacturing method, insulated gate field effect transistor, insulated gate field effect transistor manufacturing method, semiconductor light-emitting element manufacturing method and solar cell manufacturing method

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