WO2003007371A2 - Transistor cell - Google Patents

Abstract

The invention relates to a transistor cell, characterized in that for the individual transistors of said transistor cell a heat dissipation adapted to the temperature conditions of the cell in operation is provided. Heat dissipation can for example be specifically reduced for the transistors at the edge of a cell which are colder so that they reach the same temperature as the transistors in the center of the cell which are hotter. This can be achieved without substantially increasing the temperature of the hottest transistors.

Description

description

transistor cell

The present invention relates to a transistor cell. The present invention relates in particular to a power transistor cell (e.g. heterobipolar transistor power cells or MMIC power cells) which is thermally optimized by air bridges.

Cells made from transistors, especially from heterobipolar transistors (HBT), are required for many applications in the micelle range. One area of application is mobile communication technology, for example. The special advantages of HBT and HBT-MMIC (monolithic microwave integrated circuit) are their ability to carry high currents with high current densities. HBTs achieve high power amplification and high efficiency. However, these advantages often cannot be used due to the poor thermal conductivity of the semiconductor substrate material (e.g. gallium arsenide (GaAs)).

It is therefore necessary to ensure that the heat generated in the cells is sufficiently dissipated. So far, various means have been used to ensure adequate heat dissipation. The substrates used can, for example, be thinned to a thickness that corresponds to the distance between the heat sources. Metal-filled wells etched into the back of the substrate can be used as heat sinks below the transistors. From the back of the substrate to the connection contact surfaces on the top, openings (via holes) which are coated with gold can be used for heat dissipation. The transistors can be mounted using a so-called "flip-chip" assembly technique. It is also possible to mount the transistors on the heat sinks from the emitter connection surfaces via support bumps and to connect the collector and base regions on the back of the substrate. Corresponding openings are provided for the electrical connection. It is also possible to epitaxially grow the semiconductor layers of the transistor onto a heat-conducting substrate.

A possibility of direct heat dissipation via the electrical connections of the transistor areas is provided by using air bridges. Such air bridges are made of electrically and thermally conductive material, preferably a suitable metal, and electrically and thermally connect the contacts of the individual transistors of a cell to one another in a bridge-like manner. Such air bridges are described for example in the following publications.

Liou et al .: "The Effect of Thermal Shunt on the Current Instability of Multiple-Emitter-Finger Heterojunction Bipolar Transistors", IEEE 1993 Bipolar Circuits and Technology Meeting, pp. 253,256, 1993; B. Bayraktaroglu et al. : "Very High-Power-Density CW Operation of GaAs / AlGaAs Microwave Heterojunction Bipolar Transistors", IFEE Electron Device Letters 14, 493-495 (1993), T. Miura et al. : "High Efficiency AlGaAs / GaAs Power HBTs at a Low Supply Voltage for Digital Cellular Phones", GaAs TC Symposium 1996 Dig., Pp. 91-94, 1996; R. Anholt et al. : "Decoupled Electrical / Thermal Modeling of AlGaAs / GaAs Heterojunction Bipolar Transistors", IEEE GaAs IC Symposium Dig. 1996, pp. 167-170, 1996. In these HBTs, the emitter fingers are connected to one another with an airlift. A connection of the collector metal connections of the individual HBT sub-cells via air bridges is described, for example, in the publication by H.-F. Chau et al. : "High-Power, High-Efficiency K-Band _A l _G aAs / GaAs heterojunction bipolar transistors ", IEEE GaAs IC Symposium 1996 Dig., Pp. 95-98, 1996. Several of the means described can be combined. Such an airlift is also described in German Offenlegungsschrift DE 197 34 509 ,

It should be noted here that in the power transistor cells usually used, the individual transistors, in particular transistor fingers, are arranged so close to one another that they heat up each other. As a consequence, the transistors at the edge of the cell are significantly colder than those in the middle. However, warmer transistors, in particular warmer transistor fingers, have a low threshold voltage and therefore carry disproportionately more current. This is problematic because this inhomogeneity results in unfavorable electrical properties and premature aging. Therefore, stabilization measures, e.g. Base ballast resistors used. However, these sometimes considerably impair the electrical properties of the transistor cell.

It is therefore the object of the present invention to provide a transistor cell which reduces the difficulties mentioned or avoids them entirely. It is in particular the object of the present invention to provide a transistor cell in which the temperature differences between the individual transistors are significantly reduced without the electrical properties of the transistors being impaired.

This object is achieved by the transistor cell according to independent claim 1. Further advantageous embodiments, configurations and aspects of the present invention result from the dependent patent claims, the description and the accompanying drawings. According to the invention, a transistor cell, in particular a power transistor cell, is provided from individual transistors, each with at least one separate electrical connection contact, the connection contacts

Individual transistors are each thermally conductively connected to at least one heat sink and these thermally conductive connections each have a predetermined thermal resistance. The transistor cell according to the invention is characterized in that the thermal resistances of the thermally conductive connections are selected such that the temperature differences between all individual transistors of the transistor cell are less than 5% during operation.

The transistor cell according to the invention is based on the consideration that heat dissipation adapted to the temperature conditions during operation is provided for the individual transistors in the transistor cell. For example, the heat dissipation of the colder transistors (these are usually those at the edge of the cell) can be deliberately deteriorated so that they reach the same temperature as the warmer transistors (usually those in the middle of the cell). This can be achieved without significantly increasing the temperature of the hottest transistors.

The transistor cell according to the invention has the advantage that the temperature differences between the individual transistors are significantly reduced without their electrical properties being impaired. In particular, those previously used

Stabilization measures, such as base ballast resistances in the case of bipolar transistors, are designed to be less aggressive or are omitted entirely. In this way, good thermal properties and good electrical behavior are achieved at the same time. According to a preferred embodiment, the temperature differences between all individual transistors of the transistor cell during operation are less than 2%, preferably less than 1%.

It is further preferred if the connection contacts of the individual transistors are thermally conductively connected to the heat sink and to one another via an air bridge, preferably an electrically conductive air bridge. In this embodiment, all the transistors of the transistor cell are thus connected to the heat sink essentially via a single interconnected structure. This has the advantage that a temperature compensation between the transistors can already take place via this interrelated structure. Nevertheless, from the point of view of an individual transistor, a single interrelated structure ultimately only acts like a thermally conductive connection between the transistor and the heat sink, this thermal connection having a certain thermal resistance. By targeted modifications of the airlift can be used for different

Transistors different thermal resistances are generated.

It is particularly preferred if the air bridge has a substantially two-dimensional extent in a plane parallel to a semiconductor substrate in which the individual transistors are arranged. In this preferred embodiment of the present invention, an air bridge is thus used which not only extends substantially in the direction of a sequence of individual transistors aligned in a row, but which is also substantially expanded perpendicular to this direction in the plane of the substrate top. On the one hand, such an air bridge can be made relatively thick and therefore good heat conductor and, on the other hand, it can be connected to the heat sink via additional thermal contacts on larger contact surfaces. Overall, this results in a significantly reduced thermal resistance for all individual transistors.

According to a further preferred embodiment, the air bridge has constrictions and / or cutouts, so that the thermal resistances of the thermal connections from predetermined individual transistors to the heat sink are greater than the thermal resistances of the thermal connections from the remaining individual transistors to the heat sink. Constrictions and / or cutouts in the

Airlift can be taken into account in a simple manner during the manufacture of the airlift, so that there is thus an inexpensive possibility of specifically influencing the thermal resistances for the individual transistors.

It is further preferred if the air bridge comprises at least two thermally conductive layers. It is particularly preferred if the constrictions and / or recesses are formed in only one of the two layers.

According to a further preferred embodiment, the air bridge is connected to the heat sink via contact pillars. It is further preferred if predetermined contact pillars have a greater thermal resistance, so that the thermal resistances of the thermal connections from predetermined individual transistors to the heat sink are greater than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink. An essentially identical effect can also be achieved in that the contact posts are omitted or interrupted at predetermined points at which contact posts would be provided, if one wanted to generate the same thermal resistances as possible. According to a further preferred embodiment, the heat sink is arranged in the semiconductor substrate in which the individual transistors are arranged. According to another preferred embodiment, the heat sink is arranged in a carrier which is connected to the semiconductor substrate in which the individual transistors are arranged. It is particularly preferred if the contact pillars, which are connected to the heat sink via the air bridge, are designed as bumps.

According to a further preferred embodiment, the individual transistors are bipolar transistors, in particular heterobipolar transistors, each having an emitter, a base, and a collector, with for each transistor at least one emitter finger as a connection contact of the emitter, a base finger as a connection contact of the base, or a collector contact as a connection contact of the Collector is formed and the emitter fingers, the base fingers or the collector contacts are thermally conductively connected to one another via an air bridge with the heat sink. It is particularly preferred if the air bridge is thermally conductively connected to the emitter fingers of the individual transistors.

The invention is illustrated below with reference to figures of the drawing. Show it:

1 shows a cross section of the central area of a first embodiment of the transistor cell according to the invention,

Fig. 2 shows a plan view of FIG. 1

Structure,

3 shows the edge area of a first embodiment of the transistor cell according to the invention, 4 is a plan view of the structure shown in FIG. 3,

5 shows a further embodiment of the transistor cell according to the invention in a top view,

Fig. 6 shows a further embodiment of the transistor cell according to the invention in a plan.

Fig. 7 shows a further embodiment of the transistor cell according to the invention in a plan

Fig. 8 is a section through the structure shown in Fig. 7, and

9a, 9b the temperature distribution within a transistor cell according to the invention in comparison to a conventional transistor cell.

1 shows in cross section and somewhat schematically the central region of a power transistor cell consisting of a plurality of heterobipolar transistors. A thermally conductive and preferably also electrically conductive air bridge 1 connects the emitter fingers 5 applied as contacts on the emitters 2 to one another. In the case of an electrically conductive air bridge, a separate electrical connection of the emitter fingers 5 is omitted. The air bridge 1 comprises an upper electroplating layer 1 a and a lower electroplating layer 1 b. On the base area 3 there are likewise finger-shaped connection contacts as base fingers 6. Collector contacts 7 are correspondingly applied to the collector area 4. According to the invention, there are no restrictions on the shape of the contacts compared to the configurations customary in conventional power transistor cells, apart from the fact that suitable mounting surfaces must be present for the air bridge.

Arranged behind the drawing plane in the viewing direction

Contact pillars 8 are also shown in Fig. 1. The thermal and preferably also electrical connection between the air bridge 1 and the upper side of the semiconductor substrate 9 or emitter connection surfaces present on the upper side of the semiconductor substrate 9 is produced with these contact pillars. The area in which the contact pillars are seated should preferably be as large as possible. It can take up the entire free chip area, except the areas for the base and collector connection areas.

Fig. 2 shows the arrangement of Fig. 1 in supervision. The large-area airlift 1 is drawn in here with straight edges in the upward and downward direction in the plane of the drawing and with break lines to the left and right, which indicate a further expansion of the airlift 1. In this example, the airlift continues to the left and right according to the number of individual transistors present. The emitter fingers 5, the base fingers 6 and the collector contacts 7 and the contact pillars 8 are drawn in with dashed lines as hidden contours. The base fingers 6 are electrically conductively connected to a base pad 12; the collector contacts 7 are electrically conductively connected to a collector connection surface 13. The components shown are not all on the same level. The transistor cell thus has an air bridge 1 which is parallel to a semiconductor substrate in one plane which the individual transistors are arranged has an essentially two-dimensional dimension.

In the exemplary embodiment shown, the air bridge 1 uses both the emitter fingers 5 of the individual transistors provided as contacts of the emitters and the common emitter connection surface 11 as contact surfaces for the contact pillars of the air bridge. The airlift is therefore seated on the emitter fingers 5, as can be seen in FIG. 1. The contact pillars 8, 8a can be placed partly on the top 14 of the chip made of semiconductor material (contact pillars 8a in FIG. 2), partly on the emitter connection surface 11 (contact pillars 8 in FIG. 2). The air bridge 1 and the contact pillars 8 are preferably electrically conductive, and the electrical connection of the emitter fingers 5 is effected via the contact pillars 8 seated on the emitter connection surface 11.

The common collector connection surface 13 is completely or partially spanned by the air bridge 1. In the

Collector pad 13, the entire collector current is collected from the individual transistors. The air bridge 1 preferably also spans in whole or in part over the base pad 12, via which the base regions of the individual transistors are controlled. Also the

In principle, pads can be arranged and dimensioned as desired.

The top 14 of the chip and the emitter pad 11 thus each form one

Heat sink, which are connected to the transistors of the transistor cell via the air bridge 1. From the point of view of the individual transistors, the air bridge 1 represents a thermally conductive connection to the heat sinks, which has a predetermined thermal resistance. The

Airlift is designed in the central area of the transistor cell so that the transistors in the central area of the Transistor cell essentially all have to overcome the same thermal resistance.

The individual transistors of the transistor cell, in particular the transistor fingers, are arranged so close together that they heat each other up. As a consequence, the transistors at the edge of the cell are significantly colder than those in the middle.

While FIGS. 1 and 2 have hitherto illustrated the central region of an embodiment of the transistor cell according to the invention, FIGS. 3 and 4 show the edge region of this embodiment of the transistor cell according to the invention.

As can be seen from FIGS. 3 and 4, the upper electroplating layer 1 a of the air bridge 1 has a cutout 20 above the outermost transistor of the transistor cell. Accordingly, the thermal connection between the outermost transistor and the heat sinks 11, 14 has a significantly increased thermal resistance, since the heat in the region of the recess 20 can only be transported by the lower electroplating layer 1b. In this way, the heat dissipation of the transistor at the edge of the cell, which is colder in a conventional construction, can be deliberately deteriorated, so that it reaches the same temperature as that in a conventional construction, hotter transistors in the center of the cell. Thermal resistances of the thermally conductive connections are chosen so that the temperature differences between all individual transistors of the transistor cell are less than 5% during operation.

FIGS. 5 and 6 each show a further embodiment of the transistor cell according to the invention in a top view, wherein in the embodiment shown in FIG. 5 the recess 20 in the upper electroplating layer 1 a is designed in a different way than in the embodiment shown in FIG. 4. In the embodiment shown in FIG. ₆ , the recess 20 is provided in the two electroplating layers _{1 a and 1} b. Again, the recess 20 is arranged so that the thermal resistance of the thermal connection from the outermost

Individual transistor to the heat sink 11, 14 is greater than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink 11, 14. Accordingly, a significantly higher homogeneity in the temperature distribution over the transistor cell according to the invention is achieved.

7 shows a further embodiment of the transistor cell according to the invention in a top view. In this embodiment, a first, extended contact pillar 8a and two further contact pillars 8b are provided, the two contact pillars 8b having a greater thermal resistance than the contact pillar 8a, so that the thermal resistances of the thermal connections from the outermost individual transistor to the

Heat sink 14 is greater than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink 14. In this embodiment of the transistor cell according to the invention, the different contact pillars are achieved by cutouts 21 in the lower electroplating layer 1b (FIG. 8).

FIGS. 9a and 9b show the temperature distribution within a transistor cell according to the invention (FIG. 9b) in comparison to a temperature distribution within a conventional transistor cell (FIG. 9a). The temperature increase is shown along a section line through eight transistor fingers. The transistor cell according to the invention has the advantage that the temperature differences between the individual transistors are significantly reduced without their electrical properties being impaired.

Claims

claims 1. transistor cell, in particular power transistor cell, made of individual transistors each with at least one separate electrical connection contact (5, 6, 7), the connection contacts (5, 6, 7) of the individual transistors each being thermally conductively connected to at least one heat sink (11, 14) and these thermally conductive connections (1) each have a predetermined thermal resistance, characterized in that the thermal resistances of the thermally conductive connections (1) are selected so that the temperature differences between all individual transistors of the transistor cell are less than 5% during operation. 2. transistor cell according to claim 1, d a d u r c h g e k e n n z e i c h n e t that the temperature differences between all Individual transistors of the transistor cell in operation are less than 2%, preferably less than 1%. 3. Transistor cell according to claim 1 or 2, characterized in that the connection contacts (5, 6, 7) of the individual transistors with the heat sink (11, 14) and with each other via an air bridge (1), preferably an electrically conductive air bridge (1), thermally are conductively connected. 4. Transistor cell according to claim 3, characterized in that the air bridge (1) in a plane parallel to a semiconductor substrate (9), in which the individual transistors are arranged, has a substantially two-dimensional extent. 5. transistor cell according to claim 3 or 4, d a d u r c h g e k e n n z e i c h n e t that the air bridge (1) constrictions and / or recesses (20, 21), so that the thermal resistances of the thermal connections of predetermined Individual transistors to the heat sink (11, 14) are larger than the thermal resistances of the thermal connections of the remaining individual transistors to the heat sink (11, 14). 6. transistor cell according to one of claims 3 to 5, d a d u r c h g e k e n n z e i c h n e t that the air bridge (1) comprises at least two thermally conductive layers (la, lb). 7. transistor cell according to claim 6, d a d u r c h g e k e n n z e i c h n e t that the constrictions and / or recesses (20, 21) are formed in only one of the two layers (la, lb). 8. transistor cell according to one of claims 3 to 7, d a d u r c h g e k e n n z e i c h n e t that the air bridge (1) via contact pillars (8, 8a, 8b) with the heat sink (11, 14) is connected. 9. Transistor cell according to claim 8, characterized in that predetermined contact pillars (8, 8a, 8b) have a greater thermal resistance, so that the thermal resistances of the thermal connections of predetermined individual transistors to the heat sink (11, 14) are greater than the thermal resistances the thermal connections of the remaining individual transistors to the heat sink (11, 14). 10. Transistor cell according to one of claims 1 to 9, characterized in that the heat sink (11, 14) is arranged in the semiconductor substrate (9) in which the individual transistors are arranged. 11. A transistor cell according to one of claims 1 to 9, that the heat sink (11, 14) is arranged in a carrier which is connected to the semiconductor substrate (9) in which the individual transistors are arranged. 12. transistor cell according to claim 11, d a d u r c h g e k e n n z e i c h n e t that the contact pillars (8, 8a, 8b), via which the air bridge (1) is connected to the heat sink (11, 14), are formed as bumps. 13. transistor cell according to one of claims 1 to 12, characterized in that the individual transistors are bipolar transistors, in particular heterobipolar transistors, each having an emitter (2), a base (3), and a collector (4), at least for each transistor an emitter finger (5) as a connection contact of the emitter (2), a base finger (6) is designed as a connection contact of the base (3) or a collector contact (79 as a connection contact of the collector (4) and the emitter fingers (5), the base fingers (6) or the collector contacts (7) via an air bridge (1) with the Heat sink (11, 14) and thermally conductively connected to each other. 14. transistor cell according to claim 13, d a d u r c h g e k e n n z e i c h n e t that the air bridge (1) with the emitter fingers (5) of the individual transistors is thermally conductively connected.