WO2003003461A1 - Semiconductor integrated circuit device and method for reducing noise - Google Patents

Abstract

A semiconductor integrated circuit device comprising a semiconductor region or a substrate for DC isolating a first well region on which a circuit element handling a micro signal relative to the working voltage or an analog signal is formed. The semiconductor region or the substrate is AC coupled with the potential of a semiconductor region or the substrate on the periphery of the first well region using a first capacitive element. It is amplified through an inverted amplifier circuit and the output signal is AC coupled with the semiconductor region or the substrate on the periphery of the first well region using a second capacitive element, thus canceling potential variation of the semiconductor region or the substrate and stabilizing the potential.

Description

Semiconductor integrated circuit device and noise reduction method

Technical field

 The present invention relates to a semiconductor integrated circuit device and a noise reduction method, and more particularly to a technology that is effective when applied to the above-described analog circuit side noise reduction technology in a CMOS integrated circuit in which digital circuits and analog circuits are mixed.

 Light

Background art

 Rice field

 In an integrated circuit in which an analog circuit that handles weak signals and a digital circuit that generates switching noise are built on the same chip, the noise generated by the digital circuit (substrate-coupled noise) passes through the substrate to reduce the effects of noise. There are problems that are propagated to susceptible analog circuits and affect their operation. Conventionally, to solve this problem, a noise reduction method using a triple-well structure as shown in Fig. 23 has been proposed. In the integrated circuit 1, the analog circuit 2 and the digital circuit 3 are composed of p-type transistors 71, 72 and n-type components surrounded by n-type capacitors 61 and 51, respectively, having polarities opposite to those of the substrate formed on the p-type substrate 4. It is composed of 62 and 52 areas.

In order to stabilize the cell potential, the n-poles of the analog circuit 2 and the digital circuit 3 are connected to bias power supplies Vna and Vnd, respectively. The n-pole and the P substrate are connected by junction capacitances C 0a and C 0d, respectively. The noise vn generated by the digital circuit is coupled to the substrate via the resistor in the well, C0d, and further propagated to the analog circuit via the substrate resistance, C0a. In this case, the analog circuit and the digital circuit are separated by n levels, and noise is transmitted through this junction capacitance, so that the digital circuit or analog circuit is directly constructed on the board. Noise propagation Can be suppressed. Such a method is described in "Digital / analog mixed LSI (Semiconductor World, pp. 174-178, 19993)", etc. As described above, a circuit is directly provided on the P board. In the triple-well structure shown in Fig. 23, the analog circuit area and the digital circuit area are separated by the junction capacitance to suppress the propagation of noise. In addition, there is a problem that the noise of only a very low frequency can be suppressed, and the connection of the parallel or the substrate to the bias power supply Vna or Vnd is easily affected by the parasitic impedance of the wiring. In order to solve the problem that only the DC or relatively low frequency noise in the triple-hole structure described above can be suppressed, those who detect the substrate noise and generate a cancellation signal, Return Japanese Patent Application Laid-Open No. 11-237374 proposes to suppress or reduce the substrate noise.

 With the advance of semiconductor technology, the circuit scale tends to become larger and larger. When various circuits are formed on a single semiconductor integrated circuit device, it is difficult to determine which circuit causes noise and which path affects other circuits. Therefore, the inventors of the present application can rationally adapt to the above-mentioned circuit complexity and increase in circuit scale, which would be a problem when applied to an actual semiconductor integrated circuit device. Investigation of the improvement of the invention proposed earlier led to the invention of the present application.

An object of the present invention is to solve the above-mentioned problems and to provide a semiconductor integrated circuit device and a noise reduction method in which AC noise is reduced more effectively. Another object of the present invention is to provide a user-friendly noise reduction method. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

 The outline of a typical invention disclosed in the present application is briefly described as follows. In other words, the semiconductor device includes a semiconductor region or a substrate that DC-separates a first semiconductor (gauge) region formed with a circuit element for handling a signal or an analog signal relatively small with respect to an operating voltage. The potential of the semiconductor region or substrate around the region is AC-coupled using the first capacitive element, and the output signal amplified by the inverting amplifier circuit is output to the first

The semiconductor region or the substrate around the 1-perimeter region is AC-coupled to the semiconductor region or the substrate by a second capacitive element, and the change in the semiconductor region or the substrate potential is canceled out and stabilized.

 The outline of other typical inventions disclosed in the present application will be briefly described as follows. That is, the first rail region in which a circuit element for handling a signal or an analog signal relatively small with respect to the operating voltage is formed is separated DC using a semiconductor region or a substrate, and the first rail is separated. The noise component of the semiconductor region or the substrate around the semiconductor region is inverted and amplified and transmitted to the semiconductor region or the substrate around the first shell region so that the noise components cancel each other, thereby suppressing or suppressing the noise component. Reduce. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a main part configuration diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.

 FIG. 4 is an equivalent circuit diagram of the embodiment of FIG.

 FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 5 is an equivalent circuit of the embodiment of FIG. 4,

 FIG. 6 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

 FIG. 7 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

 FIG. 8 is an overall configuration diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention,

 FIG. 9 is a configuration diagram showing one embodiment of a PLL circuit to which the present invention is applied.

 FIG. 10 is a block diagram showing an embodiment of an ADC circuit to which the present invention is applied.

 FIG. 11 is a block diagram showing one embodiment of the comparator of FIG. 10. FIG. 12 is a circuit diagram showing one embodiment of an inverting amplifier circuit used in the noise reduction circuit according to the present invention. Yes,

 FIG. 13 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit according to the present invention,

 FIG. 14 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit according to the present invention,

 FIG. 15 is a timing chart for explaining an example of the operation of the inverting amplifier circuit of FIG.

 FIG. 16 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit according to the present invention,

 FIG. 17 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit according to the present invention,

FIG. 18 shows an inverting amplifier circuit used in the noise reduction circuit according to the present invention. FIG. 9 is a circuit diagram showing another embodiment of

 FIG. 19 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit according to the present invention,

 FIG. 20 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

 FIG. 21 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

 FIG. 22 is a main part configuration diagram showing another embodiment of the semiconductor integrated circuit device according to the present invention.

 FIG. 23 is a configuration diagram for explaining an example of the prior art, and FIG. 24 is a configuration diagram showing another embodiment of the noise reduction circuit according to the present invention;

 FIG. 25 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention.

 FIG. 26 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention.

 FIG. 27 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention.

 FIG. 28 is a configuration diagram showing still another embodiment of the noise reduction circuit according to the present invention.

 FIG. 29 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention.

 FIG. 30 is a simulation configuration diagram for explaining the present invention.

FIG. 31 is a characteristic diagram showing a simulation result of the effect of the arrangement of the guard bands in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

 The present invention will be described in more detail with reference to the accompanying drawings.

 FIG. 1 shows a main part configuration diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 1 shows the device structure of an integrated circuit and an equivalent circuit as a configuration diagram. Although not particularly limited, the semiconductor integrated circuit device includes a deep n-type semiconductor region (cell) 51 formed on the p-type substrate 4 and an element formation formed in the n-type well 51. The shallow n-type semiconductor region (well) 52 and the p-type semiconductor region (well) 71

3

 In this embodiment, the analog circuit 2 is configured in an n-well having a polarity opposite to that of the p substrate 4. The n-well region may be composed of a deep n-well 51 for separating the substrate as described above, and a shallow n-well 52 in which a connection point or a circuit with the substrate is formed. These n ゥ ells 5 1 and 5 2 will be described as one type of n ゥ ell.

 The n level is connected to a bias power supply V na on the substrate surface. The noise reduction circuit 8 shown in the circuit notation includes an input capacitance 10 (C 1), an output capacitance 11 (C 2), and an inverting amplifier 9. The capacitors C 1 and C 2 are connected to the n-pole 51 in the analog circuit area and the input and output terminals of the inverting amplifier circuit, respectively. Here, from a digital circuit (not shown) formed on the semiconductor substrate 4, the noise transmitted to the p substrate 4 is represented by V n, the junction capacitance with the n ゥ ell is represented by C 0, The substrate resistance of the substrate is represented by R1, R2, and the substrate resistance of the p substrate is represented by R0.

In this embodiment, the digital circuit which is the noise source is not specified as in the above publication, and the noise Vn which will be supplied from any of the digital circuits is assumed. However, a noise reduction circuit 8 is provided for the n-level circuit for separating the circuit which will be affected by the noise vn or the circuit which is not preferably affected from the substrate 4 from the substrate 4. In other words, a noise reduction circuit is provided in a circuit that requires noise reduction without specifying the digital circuit that is the noise source and its transmission path.

 This configuration can be used if there is actually less noise, if there is more noise than expected, if it occurs in a limited manner during specific signal processing, or if the noise level differs due to process variations. Under any of the various conditions, the noise reduction circuit 8 operates according to the noise at that time. For this reason, in the analog circuit 2 and the like, it is possible to guarantee high-quality signal processing of an aronag signal and the like which is hardly affected by noise.

 The noise reduction circuit 8 can be formed by a relatively small element because it is only necessary to form a cancellation signal for noise reduction by using the n-well 51 having a relatively small circuit scale as a load such as a specific analog circuit. In addition, since the current consumption there can be reduced, the above-described effective and rational noise reduction can be achieved.

 FIG. 2 shows an equivalent circuit diagram of the embodiment of FIG. In the figure, for the sake of simplicity, assuming that R 0 = R 1 = R 2 = R, the ratio X a of the noise vx to the noise vn at the terminal nx in the shell with respect to the noise vn is given by the following equation (1). Is represented.

 A a = v x ÷ vn

= ((C0C 2R ² ) s ² + (C0R) s)

÷ ((2C0C2R ² + (1 + A) C0C 2R ² ) s ² + (C2R + 2C0R + (HA) C2R) s + l)

· · · · ("Analog circuit area on the grid is also stable by reducing noise vx The capacitive coupling noise vn from the p substrate 4 can be prevented. Further, the noise reduction effect at that time is represented as a characteristic diagram in FIG. In the conventional example that stabilizes n levels by using only the bias power supply, the noise propagation increases due to capacitive coupling as the frequency increases. On the other hand, in the present embodiment, the noise at the n X terminal can be suppressed by providing a noise reduction circuit and performing feedback control on the n-degree region. According to this embodiment, the stabilization of the cell can be achieved without being affected by the external current noise to the bias power supply Vna, so that the effect of the noise on the analog circuit in the cell can be effectively reduced. .

 FIG. 4 is a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the noise reduction circuit 8 is provided in the n-pel region where the digital circuit 3 is configured. That is, the inverting amplification circuit 9 of the noise reduction circuit 8 has its input / output terminals connected to the substrate surface of the n-pole region 61 including the digital circuit 3 via the input capacitance C1 and the output capacitance C2.

 In this embodiment, the digital circuit 3 is formed in an n-well region and a p-well having a polarity opposite to that of the p-substrate 4. As described above, the n-well region is formed by a deep n-well 61 for separating the substrate and a shallow n-well 62 formed by a connection point with the substrate or a circuit power such as a P-channel type M0 SFET. Become . On the deep n-layer 61, a shallow p-layer 72 for forming a circuit such as an N-channel type MOS FET is formed.

The n-well is connected to the bias power supply V nd on the substrate surface. The noise reduction circuit 8 shown in the circuit notation includes an input capacitance 10 (C 1), an output capacitance 11 (C 2), and an inverting amplifier 9. The capacitors C1 and C2 are connected to the n-channel 61 in the digital circuit area and the input terminal and output terminal of the inverting amplifier circuit, respectively. Here, let the noise of digital circuit 3 be vnx, The noise transmitted to the n-pole 61 is vx, the junction capacitance between the n-well and the substrate is C0, the substrate resistance in the n-well 61 is R1, R2, and the resistance of the n-well 62 is Rn, p The junction capacitance with the well 72 is represented by C p, and the substrate resistance of the p substrate is represented by R 0.

 FIG. 5 shows an equivalent circuit of the embodiment of FIG. The ratio X d of the noise V X s at the n X s terminal on the p substrate to the digital input noise v n x is expressed by the following equation (2).

 A d = V X s / V n X

= C0R (C2Rs ² Is) ÷ ((3 + A) C0C2 R ² s ² + (3C0 + (2 + A) C2) Rs + l)

 (2) Contrary to the embodiment of FIG. 1, this configuration is useful when a digital circuit which is considered to be a noise source is specified. In other words, when a digital circuit that can be regarded as such a noise generating source is specified, noise is generated by using the n-channel 61 having a relatively small circuit scale as a load, such as the specific digital circuit. Since it is only necessary to form a cancellation signal for reduction, it can be formed with relatively small elements, and the current consumption there can be reduced, so that effective and rational noise reduction is possible as described above. become.

In this embodiment, the generation of noise in the digital circuit region 3 can be suppressed by feedback-controlling and reducing the noise in the digital circuit region 3 which is a noise source. As a result, propagation of substrate noise to an analog circuit region in an n-well region different from the p substrate region 4 and the digital circuit region 3 can be reduced, and those regions can be stabilized. Further, as shown by a broken line in the figure, the capacitance C 2 can be connected to the p-type region 72 in the n-type well 61. In this case, the feedback control is performed by connecting the junction capacitance C p between the n-pole and the p-well in series with C 2. Is possible.

 FIG. 6 shows a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the noise reduction circuit 8 is provided on the p-substrate between the circuit areas of the digital circuit 8 and the analog circuit 2, and the propagation of noise from the digital circuit 8 to the analog circuit 1 in the substrate 4 is performed. It is to keep it down. In this embodiment, the inverting amplifier circuit 9 of the noise reduction circuit 8 has an input terminal connected to the p-substrate 4 via an input capacitor 10 (C 1) and an output terminal connected to the output capacitor 11 (C 2). Connected to the p-substrate 4.

 In this embodiment, an n-well region 12 is provided as a dummy between the substrate regions to which the capacitors C1 and C2 are connected. By providing such n-pole region 12, the resistance value of the substrate resistance R3 is equivalently increased, and the feedback control of the inverting amplifier circuit can be more easily performed.

 Further, as indicated by a broken line, the capacitance C2 or the capacitance C1 can be connected to the p-substrate via the resistor R4 and the junction capacitance Cp. At this time, since the junction capacitance C p forms a low-pass filter together with the well resistance R 0, high frequency noise can be reduced. By applying the noise reduction circuit 8 to this, the propagation of higher frequency noise can be suppressed by feedback control, and the reduction effect can be enhanced at the same frequency.

 In the case where the n-pole region 12 is independent without supplying a bias power from another, the output terminal of the inverting amplifier circuit 9 can be directly connected to the n-pole 11 without using the capacitor C described above. Also, by forming independent n-poles of opposite polarity in the P-substrate on the input terminal side of the inverting amplifier circuit 9, the input terminal can be directly connected to the n-well without using the capacitor C1.

A noise reduction circuit of a semiconductor integrated circuit device is constructed by combining or combining the embodiments shown in FIGS. 1, 4 and 6, respectively. And a higher reduction effect can be obtained.

 FIG. 7 shows a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. This embodiment is directed to noise reduction of a circuit on an isolation type (SOI) substrate. In this embodiment, the analog circuit 2 and the digital circuit 3 are formed on a buried oxide film 13 on a silicon substrate. The p-wells 71, 72 and the n-wells 52, 62, on which the N-channel type MOSFET and the P-channel type MOSFET of the analog circuit 2 and the digital circuit 3 are formed, are separated by the p-type separation oxide film 14.

 As a result of the separation of the surface and depth of these MOSFETs by an oxide film, DC and low-frequency noise are cut off. However, the high frequency noise generated in the digital circuit 3 is transmitted to the analog circuit 2 through the junction capacitance of the oxide film. Here, the noise reduction circuit 8 is used as a cell region 52, 71 configured with the P-channel type MOS FET or the N-channel type MOS FET of the analog circuit 2 or a cell region 62 configured with the digital circuit 3; By applying to 72, noise propagation or generation can be suppressed.

FIG. 8 shows an overall configuration diagram of one embodiment of the semiconductor integrated circuit device according to the present invention. In the figure, circuits formed in a semiconductor integrated circuit device are provided separately for each function. The arrangement of each circuit block is shown corresponding to the actual geometrical arrangement on the semiconductor substrate. The integrated circuit 1 of this embodiment has a memory circuit 21, a microcomputer core (CPU) 22, and logic 23. Digital circuit 3 such as control bus 14, analog / digital converter (ADC) 25, digital / analog converter (DAC) 26, phase lock loop circuit (PLL) 27, filter 28 etc. Be composed. Analog circuit 2 and digital circuit If a noise reduction circuit is provided for each circuit in the area of the road 3, noise generated in each digital circuit area can be reduced.

 In particular, in the memory circuit 21 in the area of the digital circuit 3, the clock delay control circuit (DLL) 29 that controls the clock is easily affected by noise, and the noise reduction circuit 81 should be applied to the DLL circuit 29. Is effective for accurate clock generation. Since one analog circuit is easily affected by noise, it is effective to provide noise reduction circuits 82 and 83 in correspondence with the PLL circuit 27 and the ADC circuit 25.

 FIG. 9 shows a configuration diagram of one embodiment of a PLL circuit to which the present invention is applied. For example, the PLL circuit 27 includes a phase comparator 271, a charge pump 272, a loop filter 273, a frequency divider 274, and a voltage controlled oscillator (VCO) 275. When the VCO is affected by noise, the output clock signal is modulated. Therefore, if a noise reduction circuit 82 is provided in the n level where VCO is formed to reduce noise, clock signals used in ADCs and DACs can be accurately generated, which is effective. FIG. 10 is a block diagram showing an embodiment of an ADC circuit to which the present invention is applied. The ADC 25 of this embodiment is mainly composed of a comparator 25 1 and an encoder 25. The comparator 25 1 compares the input analog signal V in based on the reference voltages vr-1, vr-2 to vr-n. The comparison results of these comparators are input to an encoder, and a digital signal having binary weights is formed.

FIG. 11 is a block diagram showing one embodiment of the comparator shown in FIG. In the comparator, a switch for transmitting a reference voltage vr and an input signal vin by a switch, two capacitors and two inverter circuits are connected in series. A switch is provided between the input and the output of the inverter circuit. Turn on the switch and turn on the inverter Supply the input signal vin with the input and output of the circuit shorted. As a result, the input signal Vin is held in the capacitor in a state where the input and the output of the above-mentioned circuit are short-circuited.

 Next, when these switches are turned off and the switches for transmitting the reference signal vr are turned on, a low-level output signal is formed if the input signal Vin is larger than the reference voltage Vr, and the reference voltage If the input signal Vin is smaller than Vr, a high-level output signal is formed. This output signal is amplified by an inverter circuit and held in a latch circuit. If the input section 253 of the comparator is affected by noise, an offset occurs in the conversion result or a bit error occurs. Therefore, it is effective to provide a noise reduction circuit 83 in the n-level in which the input section 253 of the comparator is formed to stabilize the signal.

 As described above, in one semiconductor integrated circuit device, one or a plurality of noise reduction circuits are provided in a digital circuit or an analog circuit, and the voltage in the pail region where the noise reduction circuit is formed is stabilized. The performance of a circuit provided in the integrated circuit device can be improved.

FIG. 12 is a circuit diagram of an embodiment of the inverting amplifier circuit used in the noise reduction circuit. In this embodiment, the inverting amplifier circuit 9 is composed of a CMOS inverter 30 composed of a pair of N-channel MOSFETs Mni1 and a P-channel MOSFETMpi1 and two N-channel MOSFETs Mns1 and Mns2. The source follower output circuit 31 is configured. The output terminal OUT 1 of the inverter 30 is connected to the gate terminal of the N-channel MOSFET Mns 1 of the source follower output circuit 31. Also, the bias voltage Vbn is supplied to the gate terminal of the N-channel MOS FET Mns 2 of the source follower 31 to operate as a constant current load. By installing such a source follower output circuit 31 after the inverter 30, the load on the inverter can be reduced, and noise can be reduced in the inverter using the small-sized MO SF ETMpi 1 and Mni 1. An inverting amplifier circuit having the required gain can be realized. Such an inverting amplifier circuit can be formed by using a standard process of the MS integrated circuit that forms the digital circuit. In addition, since it has a simple configuration and can easily respond to changes in processes and the like, it can be used for general purposes.

 Since the inverting amplifier circuit 9 is connected to the substrate via the capacitors C1 and C2, the inverting amplifier circuit 9 can generally be connected to either n-level power supply potential or p-level ground potential. A feedback resistor 32 (Rf) is provided between the input and output terminals of the inverter 30 to stably set the DC operating point. This feedback resistor Rf can be configured using the on-resistance value of the MOSFET as described later, in addition to a passive element such as polysilicon. At this time, an arbitrary resistance value can be given as R f by controlling the gate voltage of the MOS FET.

FIG. 13 is a circuit diagram of another embodiment of the inverting amplifier circuit used in the noise reduction circuit. In this embodiment, a source follower 33 is provided at the input of the inverter 30. The source follower 33 includes two N-channel MOSFETs Mns3 and Mns4, and a gate terminal of the N-channel MOSFET Mns4 is supplied with a bias voltage Vbn2. The gate terminal of the N-channel MOSFET Mns3 is connected to a detection region in the n-type region on the integrated circuit substrate. The gate capacitance of the N-channel MOSFET Mns3 also functions as the input capacitance C1, and also serves as current amplification of noise. If the source follower 33 provided at the input section is composed of two P-channel MOS FETs as in this embodiment, the input is connected to the ground potential p. Since it can be connected to the p-well, the noise in the p-well or p-well region formed in the p-well on the board is detected, and the noise is reduced if the inverted amplified signal is fed back by the capacitor C2 as described above. You can do it.

 FIG. 14 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit. In this embodiment, the switch 34 is a switch for controlling the DC operating point of the inverter 30. When this switch 34 is composed of an N-channel type M0 SFET as shown in the figure, when the switch signal Vc is at a high level, the switch 34 is turned on, and when the switch signal Vc is at a low level, Switches 34 are turned off. At the start of the operation of the inverting amplifier circuit, the switch signal Vc is set to the high level to set the operating point of the inverter 30. Thereafter, the switch 34 is opened (off state) to operate the inverting amplifier circuit.

 Since the noise reduction circuit 8 constitutes a feedback loop using the substrate and the capacitance as feedback elements together with the inverting amplifier circuit, the signal AV at the input section of the inverting amplifier circuit is slightly suppressed by negative feedback. That is, since the signal is supplied via the capacitor C1 as described above, the DC bias voltage due to the ON state of the switch 34 is held in the capacitor C1, and the The operating point is set in the high gain linear region. As long as the bias voltage is maintained in such a linear region, that is, as long as the bias voltage is held in the capacitor C1, the feedback operation can be performed even when the switch 34 is opened. If the operating point shifts due to the loss of the holding voltage of the capacitor C1 due to leakage current or the like, the switch 34 is turned on again to reset the inverter 30 to the original state. You can go back. Further, the switch signal V c may be controlled by a clock and reset periodically.

FIG. 15 shows an example of the operation of the inverting amplifier circuit of FIG. Is shown in FIG. For example, in the ADC shown in FIG. 10, the comparator shown in FIG. 11 performs a sample (sw on) and a hold (sw off) operation by switching the switch sw as shown in FIG. During such operation of the ADC, the noise reduction circuit 8 is operated to reduce the influence of noise from the substrate side. That is, the switch signal VC for controlling the switch 34 provided in the inverting amplifier circuit shown in FIG. 14 is turned on (reset) and turned off (operated) in accordance with the operation of the ADC, so that the comparator is sampled. The effect of noise that is easily captured can be suppressed. The reset may not be performed every time, but may be performed at appropriate intervals.

 The reset MOS switch shown in Fig. 14 does not need to be as high as the feedback resistance of the passive element, and can be reduced in size, thus reducing the chip occupation area of the noise reduction circuit. In other words, when a high resistance is realized by a MOSFET, the channel length needs to be increased, so that the size is relatively large. In this embodiment, the case where the switch 34 is configured by using an N-channel MOSFET is shown. Instead, the P-channel MOSFET FET or the N-channel M〇 SF ET and the P-channel MOSFET M〇 are used. The switch 34 can be configured by using an SFET together.

FIG. 16 shows a circuit diagram of another embodiment of the inverting amplifier circuit used in the noise reduction circuit. In this embodiment, the inverting amplifier circuit includes an inverter 30, a source follower 31, and an inverter 35 for setting an operating point. The P-channel type MO SFETMp i 1 that forms Invar 35 The N-channel type MOSFET Mn i 2 is the same size as the P-channel type M〇 SFET Mp i 1 and N-channel type MOSFET Mn i 1 that form Invar 30 . Since the input and output of the inverter 35 are short-circuited, the DC operating point is set at the highest sensitivity. If the input of the inverter 30 is connected to the input and output of the inverter 35 by resistance, the voltage at the DC operating point of the inverter 35 is transmitted to the input terminal of the inverter 30 by force and resistance. The operating point of the inverter 30 can be automatically set to the highest sensitivity as with the inverter 35. That is, the operating point of the inverter 30 can be automatically set at the highest sensitivity without being affected by the variation in the manufacturing process of the semiconductor element. This is the same for temperature changes and voltage changes.

 FIG. 17 is a circuit diagram showing another embodiment of the inverting amplifier circuit used in the noise reduction circuit. This embodiment is basically the same as the bias setting method shown in FIG. 16 described above, but in order to achieve high integration and low power consumption, the inverter 35 is set to 10 minutes, for example, 10 minutes. It can also be realized by configuring the inverting amplifier circuit by connecting in parallel one of the 30 units of the inverters 35 and 35 together. As a result, the same performance can be realized with a smaller area than the inverting amplifier circuit of FIG.

 In this embodiment, the current that constantly flows through the inverter 35 to obtain the bias voltage can be greatly reduced. In this embodiment, an M0S resistor 36 is provided between the inverter 35 and the inverter 30. The gate is supplied with an intermediate voltage Vr in order to obtain the required resistance value of the MOS FET in a small size. The MOS resistor 36 can operate as the switch 34 as in the embodiment of FIG.

FIG. 18 is a circuit diagram of another embodiment of the inverting amplifier circuit used in the noise reduction circuit. This embodiment shows a contrivance concerning the sleep operation (non-operation) of the inverting amplifier circuit. In the present embodiment, the inverting amplifier circuit operates in the same manner as the clock 30 controlled by the clock F1. It is composed of a source follower 31 controlled by F1. When the clock F1 is at a low level, the MOSFETs Mpf, Mnf, and Msf are off, and the inverter 30 and the source follower 31 are in a sleep state. Thereby, the current consumption in the inverting amplifier circuit can be reduced to zero. When the clock F1 is at a high level, the MOSFETs Mpf, Mnf, and Msf are turned on, and the inverting amplifier circuit including the inverter 30 and the source follower 31 operates. Here, since the MOSFETs Mpf and Mnf also serve as feedback resistors of the inverter, an inverting amplifier circuit can be configured without adding a new circuit for setting the operating point. As a result, low power consumption and circuit simplification can be realized.

 FIG. 19 shows a circuit diagram of another embodiment of the inverting amplifier circuit used in the noise reduction circuit. In this embodiment, a device relating to non-operation of the inverting amplifier circuit is shown. In this embodiment, the inverting amplifier circuit is provided with a switch 37 using a P-channel MOSFET and a switch 38 using an N-channel MOSFET in addition to the inverter 30 and the source follower 31 similar to those described above. A clock signal F2 is supplied as a switch control signal to the gates of the MOSFETs constituting the switches 37 and 38.

When the clock signal F2 is at a low level, the switch 37 of the P-channel type MOSFET is turned on, and the switch 38 of the N-channel type MOSFET is turned off. As a result, the input of the inverter 30 is fixed at a high level, the input of the source follower 31 is fixed at a low level, and the inverting amplifier circuit is inactive. As a result, no DC current flows through the inverter 30 and the source follower 31, and low power consumption is achieved. On the other hand, when the clock signal F2 is at a high level, the switch 37 by the P-channel MOSFET is off, and the switch by the N-channel MOSFET is off. Switch 38 is turned on, and the inverting amplifier circuit operates as a noise reduction circuit. This makes it possible to reduce unnecessary current when the noise reduction circuit is not used.

 FIG. 20 is a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, the device structure of an integrated circuit and its circuit pattern are shown as a configuration diagram in the same manner as described above. Although not particularly limited, the semiconductor integrated circuit device may include a deep n-layer formed on the p-type substrate 4 as in the embodiment of FIG. 1 and an element formation region formed in the n-layer. Includes shallow n ゥ el and p ゥ ヱ l as The noise reduction circuit 8 includes an input capacitance 10 (C 1), an output capacitance 11 (C 2), and an inverting amplifier 9 as in FIG. Here, C 1 and C 2 can use an M 0 S capacitance or a polysilicon interlayer capacitance. For example, when reducing noise of 1 MHz or more, the capacitance values of C 1 and C 2 are about 0.1 pF and about 100 pF, respectively. The size of this capacitor is large enough to be easily realized on a chip.

 In FIG. 20, the MOSs C1 and C2 are provided in n levels in the analog circuit area, whereby the noise in the n levels in the analog circuit area is reduced by the noise reduction circuit. The substrate voltage under the MOS capacitance C1 arranged at the center of the layout is detected by the inverting amplifier circuit, and the feedback operation thereof stabilizes the substrate voltage at the point nx inside the substrate. Also, a P-cell is provided as a dummy near the substrate to which the MOS capacitors C1 and C2 are connected. As a result of the n ゥ ell separation by the dummy p ゥ ell, it is easier to consider the substrate resistance R 1 or R to a point in the deep region of n ゥ ell, nx as the resistance in the depth direction.

As a result, feedback control is performed in the deep region of n ゥ ell, and the fluctuation of noise can be further suppressed at nx. In other words, the above substrate resistances Rl and R2 Since the resistance value can be increased, and in particular, the voltage for suppressing noise is formed by R 2, the feedback control of the inverting amplifier circuit is made easier by increasing the resistance value of the resistor R 2. Thus, an inverted signal for canceling the noise Vn can be efficiently formed. By providing the capacitors C 1 and C 2 on the integrated circuit board in this way, the noise reduction circuit can be entirely configured on the chip, and the noise can be reduced without being affected by the parasitic element components outside the integrated circuit. .

 FIG. 21 is a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In the present invention, the substrate under the capacitance C 1 is stabilized by the feedback operation of the inverting amplifier circuit 9. Therefore, in this embodiment, the n + diffusion region below the MOS capacitor is extended and provided, and further connected to the wiring layer AL1, thereby stabilizing the substrate on the n-type surface over a wide range. . In other words, since the input terminal of the inverting amplifier circuit 9 is stabilized by the feedback action, the input terminal of the inverting amplifier circuit 9 is separated so as to surround the periphery of the n-element and the p-element where the circuit element is formed through the wiring layer AL1 and the n + diffusion layer. To stabilize the substrate on the n-level surface. The above description has been given of the case where the present invention is applied to the analog circuit area. However, the present invention can be similarly applied to the case where the present invention is applied to a digital circuit area or a substrate in an intermediate area between the two.

FIG. 22 shows a main part configuration diagram of another embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, when several different circuit areas are configured on one n-level, a plurality of noise reduction circuits 9 are arranged. For the circuit 41, the input capacitance C11, the output capacitance C21, and the inverting amplifier circuit 91, and for the circuit 42, the input C12, the output C22, and the inverting amplifier circuit 92, respectively. Construct a noise reduction circuit. Here, by providing a p-well region 43 between the above-mentioned C 11 -C 21 and between the above-mentioned C 12 -C 22, signal propagation on the n-well surface is prevented, and feedback operation is performed. Therefore, the effect of the noise reduction circuit can be enhanced. The inputs C 11 and C 12 are connected to the n diffusion layer on the n-well surrounding the circuits 41 and 42, and can stabilize the substrate over a wide area on the n-well surface.

 In the present embodiment, the input capacitance and the output capacitance are formed in the n-well of the analog circuit, but it is also possible to use the MOS capacitor formed in the outer well. In addition, the capacitance between metal wires can be used as the input capacitance and the output capacitance. Also, the inverting amplifier circuit can be formed on both the internal and external resistors. Note that a differential amplifier circuit can be used for the inverting amplifier circuit.

 FIG. 24 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention. This embodiment is a modification of the embodiment shown in FIG. The input and output of the noise reduction circuit are connected to guard bands (guard bands for noise detection and canceling signal input) on the integrated circuit board. This forms a feedback loop with the substrate as the feedback element. This is placed between the digital circuit that is the noise source and the analog circuit that is affected by the noise to reduce the noise.

 In this embodiment, the input and output of a noise reduction circuit (including an inverting amplifier circuit) are connected to a guard band on an integrated circuit board (a resistor for resistive connection with a bulk substrate and a cap for capacitive coupling). It detects noise and inputs a cancellation signal to reduce noise.

In this case, in order to secure the board impedance as a feedback element of the noise reduction circuit (set it to a high value), do not place a fixed distance between the two guard bands for detection and cancel signal input. It has been found that there is room for improvement, such as the fact that it must not be performed, or that it cannot respond to noise from unexpected circuits other than digital circuits. In other words, a more detailed study of the guard band arrangement has shown that the noise reduction effect It was found that it depends on the arrangement of the noise and the noise detection points.

 FIG. 25 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention. In this embodiment, the guard band for detecting the substrate noise to which the input terminal of the noise reduction circuit is connected and the guard band for inputting the cancellation signal to which the output terminal of the noise reduction circuit is connected are used as a noise source circuit or the influence of noise. Around the circuit area to be prevented. That is, two L-shaped guard bands are provided substantially symmetrically with respect to the diagonal line so as to surround the rectangular circuit region 2 and be separated by one diagonal line (upward to the right in the figure). As a result, noise propagation from outside including circuit region 1 or generated noise inside can be reduced irrespective of guard band arrangement.

 As a result of arranging the guard bands in an L-shape as described above, the symmetry of the substrate noise detection and the cancellation signal is maintained over a wide area of application, and the noise reduction effect is more uniform. Also, since a high value can be secured as the substrate impedance as a feedback element of the noise reduction circuit, the driving force of the noise reduction circuit is kept high, and the reduction effect is easily obtained. As a result, the board noise of the analog module is reduced, and the accuracy is assured to enable the on-chip.

Irrespective of the area and shape of the circuit area, arranging the guard bands in an L-shape can provide almost the same noise effect over a wide part of the circuit area, making design easy. In addition, guard bands can be placed in empty spaces between modules, and the increase in chip area can be minimized. As a result, analog modules can be deployed in system LSI products. For example, system-on-chip LSIs (ASICs, ASICs, ASICs, etc.) equipped with analog functions such as large-scale logic, memory, high-precision A / D (analog / digital) converters, and D / A (digital / analog) converters. System LSI) is applicable. In FIG. 15, the circuit area 2 where the guard ring is provided may be a digital circuit serving as a noise source, or a part of an analog circuit affected by noise may be any or all of them. In other words, when applied to an analog circuit, external noise such as the circuit area 1 can be reduced, and when applied to a digital circuit, noise is emitted to an external circuit such as the circuit area. Can be prevented. If applied to both

The above two effects act synergistically to greatly improve the noise reduction of analog circuits. In the guard band formed in the L-shape, two or more guard bands may be connected by a wire of aluminum or the like.

 FIG. 26 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention. In this embodiment, one embodiment of an L-shaped guard band arrangement is shown. In this embodiment, when a circuit element is formed on a triple cell on a p-substrate, the guard band of the noise reduction circuit is arranged in an L-shape in the same n-cell area as the target circuit. .

 FIG. 27 is a block diagram showing another embodiment of the noise reduction circuit according to the present invention. In this embodiment, another embodiment of the L-shaped guard band arrangement is shown. In the p bulk process, the guard band of the noise reduction circuit is arranged in an L-shape in the P region, which is connected to the bulk substrate around the circuit region by resistance. At this time, the entire circuit region may be configured as an n-parallel region that is connected to a capacitor, or may be configured in both a p-layer that is connected to a resistor and an n-parallel region that is connected to a capacitor.

FIG. 28 shows a configuration diagram of still another embodiment of the noise reduction circuit according to the present invention. In this embodiment, a guard band for detecting board noise to which the input terminal of the noise reduction circuit is connected, and a guard bar and an input for canceling signal to which the output terminal of the noise reduction circuit is connected, or a circuit serving as a noise source. Surround the circuit area where noise is to be prevented, and place the circuit area on the left One U-shaped guard band is provided symmetrically with respect to the above-mentioned center line, divided by the center line divided to the right. As a result, external noise propagation or internal noise generation can be reduced irrespective of the guard band arrangement.

 As a result of arranging the guard bands in a U-shape as described above, the symmetry of the substrate noise detection and the cancellation signal is maintained in a wide area of the application area, and the noise reduction effect is more uniform as in the case of the L-shape. Further, since a high value can be secured as the substrate impedance as a feedback element of the noise reduction circuit, the driving force of the noise reduction circuit is kept high, and the reduction effect is easily obtained. As a result, substrate noise of the analog module is reduced, and accuracy is ensured, enabling on-chip operation.

 Irrespective of the area and shape of the circuit area, arranging the guard band in a U-shape substantially equalizes the wide area in the circuit area, and the noise effect can be obtained, so the design is easy. In addition, guard bands can be placed in empty spaces between modules, and the increase in chip area can be minimized. As a result, the analog module can be applied to system LSI products. In this embodiment, in the p bulk process, the guard band of the noise reduction circuit is arranged in a U-shape in the P + region that is in resistance connection with the bulk substrate around the circuit region. At this time, the entire circuit region may be configured as an n-well region for capacitance connection, or may be configured for both a p-well for resistance connection and an n-well region for capacitance connection.

FIG. 29 is a block diagram of another embodiment of the noise reduction circuit according to the present invention. In this embodiment, another embodiment of the L-shaped guard band arrangement is shown. In this embodiment, when a circuit element is formed on a triple-well on a p-substrate, the guard band of the noise reduction circuit is arranged in an L-shape on the p-substrate around the triple-pellet region. FIG. 30 is a simulation configuration diagram for explaining the present invention.

 Type 1 provides a guard ring for inputting a canceling signal and for detecting noise between a noise source and a circuit area, and corresponds to the embodiment shown in FIG. In type 2, a guard ring for inputting a canceling signal is placed between the fiber sound source and the circuit area, and a guard ring for noise detection is placed on the opposite side.In type 3, as shown in Fig. 25 above An L-shaped guard ring is symmetrically arranged on the front. In each of the types 1 to 3, the monitor terminals mon1 and mon2 are arranged at the same location. FIG. 31 shows a characteristic diagram of a simulation result of the effect of the arrangement of the guard bands in FIG. In the type 1, the noise reduction effect is recognized, but the noise reduction rate is small in the above embodiment, and the difference between the two monitor terminals mon1,2 is relatively large. That is, the noise reduction effect varies within the circuit area.

 Type 2 has an overall improved force compared to Type 1, and the difference in the reduction effect between the two monitor terminals mon 1, 2 is relatively large, causing variations in the noise reduction effect within the circuit area.

 In Type 3, the noise reduction effect is large even at high frequencies, and the difference in the reduction effect is small at one monitor terminal m on l, 2. This is because, as described above, by arranging the guard ring so as to surround the circuit area and symmetrically arranging it in an L-shape or a U-shape, it is possible to detect the substrate noise in a wide area of the application area. The symmetry of the cancellation signal is maintained, the noise reduction effect is made more uniform, and a high value can be secured as the substrate impedance, which is the feedback element of the noise reduction circuit, so that the driving power of the noise reduction circuit is kept high. This proves that a reduction effect is easily obtained.

The operational effects obtained from the above embodiment are as follows. (1) The first gap above the first gap area with respect to the semiconductor area or substrate that separates the first gap area in which circuit elements for handling signals or analog signals relatively small with respect to the operating voltage are formed. The first capacitive element is AC-coupled in the vicinity of the first capacitive element, the voltage change through the first capacitive element is amplified by the inverting amplifier circuit, and the second capacitive element is surrounded by the first capacitive element. By transmitting the information via the interface, the effect can be obtained that the noise can be effectively reduced as necessary without considering the noise source and the transmission path.

 (2) In addition to the above, a circuit element that handles a digital signal having a signal amplitude corresponding to the operating voltage is formed, and the first element area is DC-separated from the first cell area.

By additionally providing a 2-cell region, a circuit that can be regarded as a noise generation source and a circuit easily affected by the noise can be formed in one semiconductor integrated circuit device.

 (3) In addition to the above, a first conductivity type well region in which the first conductivity type MOSFET is formed and a first conductivity type well in which the first conductivity type MOSFET is formed in each of the first and second shell regions. Forming a region, forming the first and second conductive type sealing region in a deeper first conductive type sealing region for cell separation, and forming the above first and second conductive type sealing region. By forming on a semiconductor substrate of the second conductivity type, there is obtained an effect that various circuits can be realized on one semiconductor substrate.

 (4) In addition to the above, the first capacitive element and the second capacitive element are respectively provided for the first conductive type sealing region for the cell isolation, so that the effect is provided only at necessary locations. The effect is that the noise can be reduced by arranging them in a random fashion.

(5) In addition to the above, the first capacitive element and the first capacitive element are provided on the semiconductor substrate sandwiched between the first and second modules, respectively. This has the effect of blocking noise in the noise path through the substrate.

 (6) In addition to the above, by providing the first conductivity type sealing region as a dummy region in a part of the periphery of the first capacitance element and the second capacitance element, the resistance of the substrate connected thereto is reduced. As the value becomes larger, it is possible to obtain the effect that the feedback control of the inverting amplifier circuit can be more easily performed and the noise in the deep region inside the cell can be more effectively reduced.

 (7) In addition to the above, the first capacitance element and the second capacitance element are connected to each other by providing the first conductivity type sealing region for gel separation as a dummy region around the first capacitance element and the second capacitance element. As the resistance value of the substrate increases, it is possible to obtain effects that the feedback control of the inverting amplifier circuit can be more easily performed and noise in a deep region inside the substrate can be more effectively reduced.

 (8) In addition to the above, the first capacitance element and the second capacitance element use a MOSFET manufacturing process by forming a MOS capacitance having the semiconductor region or the substrate to which it is connected as one electrode. The advantage is that it can be configured with -

(9) For the semiconductor region or substrate that separates the DC voltage from the second module region in which the circuit element that handles the digital signal having the signal amplitude with respect to the operating voltage is formed, the third capacitor element is provided in the vicinity of the first cell region. By coupling the voltage change through the third capacitance element with an inverting amplifier circuit and transmitting the voltage change to the periphery of the second cell region through the fourth capacitance element, noise is reduced. Noise diffusion from the digital circuit that can be regarded as a source can be prevented, and a signal or analog signal that is separated from the above-mentioned second shell region by DC and made relatively small with respect to the operating voltage can be prevented. The effect is obtained that the first level region in which the circuit element for handling the signal is formed can be provided. (10) In addition to the above, a first conductive type MOS region in which the first conductive type MOSFET is formed and a second conductive type MOS FET in which the second conductive type MOSFET is formed in each of the first and second shell regions. Forming a first conductive type gel region, forming the first and second conductive type gel regions in a deeper first conductive type gel region for cell separation, and forming the first conductive type gel region for deeper separation; Forming the mold well region on the semiconductor substrate of the second conductivity type has an effect that various circuits can be realized on one semiconductor substrate.

 (11) In addition to the above, a first capacitance element that is AC-coupled to the semiconductor region or the substrate potential around the first cell region is provided, and a voltage change through the first capacitance element is detected. By amplifying by the inverting amplifier circuit and transmitting the periphery of the first well region to the semiconductor region or the substrate via the second capacitive element, a signal relatively small with respect to the operating voltage Alternatively, an effect is obtained that a circuit for handling an analog signal can be further stabilized.

 (1 2) In addition to the above, the inverting amplifier circuit can reduce noise with a simple circuit by using a CMOS inverter circuit and a source follower output circuit that receives the amplified signal. The effect is obtained.

 (1 3) In addition to the above, by providing a resistor between the input and output of the CMOS inverter circuit, the inverting amplification operation can be performed in the linear region with the highest sensitivity. The effect is obtained.

(14) In addition to the above, the high-resistance element can be configured as an M〇SFET with an intermediate voltage lower than the power supply voltage applied to the gate, so that a small-sized resistance element with the required resistance can be configured. Is obtained.

(1 5) In addition to the above, the input terminals of the CMOS inverter circuit The bias voltage formed by the CM〇S inverter circuit in which the input and the output are coupled is transmitted through the resistor element. The effect is obtained that the inversion amplification operation can be performed in the region.

 (16) In addition to the above, the size of the CMOS inverter that forms the bias voltage and the size of the P-channel M〇SFET and N-channel M〇SFET of the CMOS inverter used in the inverting amplifier circuit By using the P-channel type M〇 SF ET and N-channel type MOSF ET, which have the same size ratio as that of the above, and each size is reduced, while reducing the area and power consumption, The effect is obtained that the optimum bias can be automatically set.

 (17) In addition to the above, between the input and the output of the CMOS inverter circuit, when the inverting amplifier circuit is in a non-operating state, it is turned on, and the inverting amplifier circuit is in an operating state. By eliminating the need for a MOSFET that is sometimes turned off, it is possible to obtain the effect that the optimal bias can be automatically set while reducing the area and power consumption. It is.

 (18) In addition to the above, the CMOS inverter circuit and the source follower output circuit include a MOS FET that turns on when the inverting amplifier circuit is in operation and turns off when not in operation. By providing a function of blocking the direct current flowing when the device is not in operation, an effect of reducing power consumption can be obtained.

(19) In addition to the above, between the input and output of the CMOS inverter circuit, the inverting amplifier circuit is turned on with a high resistance when the inverting amplifier circuit is in operation, A first MOSFET that is sometimes turned off is provided, and the inverting amplifier circuit operates at the input of the CMOS inverter circuit. Power consumption can be reduced by providing a second MOS FET that supplies power supply voltage or circuit ground potential, which is turned off when in operation and turned off when not in operation. The effect is obtained.

(20) In addition to the above, the first MOSFET is constituted by a first conductivity type MOS FET, the second M〇SFET is constituted by a second conductivity type MOS FET, and a gate of the first MOSFET and the second MOSFET is provided. By supplying a control signal for performing the above operation in common, an effect is obtained that the above control operation can be easily performed.

 (21) In addition to the above, when the inverting amplifier circuit is activated, the corresponding circuit formed in the first level or second level area is activated, and the inverting amplifier circuit is activated. When the amplifier circuit is deactivated, the corresponding first level or the circuit formed in the first level area is activated, thereby providing an efficient and effective noise reduction operation. Is achieved.

 (2 2) In addition to the above, a source follower circuit including an amplification MOSFET and a load means is further provided on the input side of the CMOS inverter circuit, and the gate capacitance of the amplification M〇SFET is used as the first capacitance element. As a result, an effect is obtained that the amplification operation can be performed efficiently.

(23) The first level region in which the circuit element that handles signals or analog signals relatively small with respect to the operating voltage is separated from the semiconductor region or substrate, and the first level region around the first level region is separated from the first level region. By inverting and amplifying the noise component of the semiconductor region or the substrate and transmitting the noise component to the semiconductor region or the substrate around the first cell region so that the noise components cancel each other, a noise source and a transmission path are considered. The effect is that it is possible to reduce the power consumption effectively as needed without performing the operation. (24) In addition to the above, the effect of inverting and amplifying the above-mentioned noise component by using a CM0S overnight circuit and a source follower output circuit can be achieved with a simple circuit. can get.

 (25) In addition to the above, the detection of the noise component of the semiconductor region or the substrate and the transmission of the inverted and amplified noise component to the semiconductor region or the substrate are performed through a capacitor means. However, the effect is obtained that only the noise component can be canceled at a level that does not affect the circuit operation.

(26) As a result of arranging the guard bands in an L-shape or U-shape, the symmetry of the board noise detection and the cancellation signal is maintained over a wide area of application, the noise reduction effect is more uniform, and the noise is reduced. Since a high value can be secured as the substrate impedance as a feedback element of the circuit, the effect is obtained that the driving force of the noise reduction circuit is kept high and the reduction effect is easily obtained.

 Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even. For example, a circuit that is easily affected by noise can be similarly applied to a circuit that handles a digital signal whose amplitude is relatively small in relation to an operating voltage, in addition to an analog circuit. The present invention relates to a semiconductor integrated circuit device in which a digital circuit or a circuit in which a large noise is generated by its operation and a circuit susceptible to noise such as an analog circuit are formed on one semiconductor substrate, and a semiconductor integrated circuit device including the same. It can be widely used as a noise reduction method. Industrial applicability

 INDUSTRIAL APPLICABILITY The present invention can be widely used as a semiconductor integrated circuit device in which noise is reduced and a noise reduction method thereof.

Claims

The scope of the claims  1. a first semiconductor region in which a circuit element for handling a signal or an analog signal relatively small with respect to an operating voltage is formed;  A semiconductor region or a substrate that separates the first semiconductor region in a DC manner, and a first capacitive element that is AC-coupled to a potential of the semiconductor region or the substrate around the first semiconductor region.  An inverting amplifier circuit for amplifying a voltage change passing through the first capacitive element; and a second capacitive element for ac coupling an output signal of the inverting amplifier circuit with the semiconductor region or substrate around the first semiconductor region. A semiconductor integrated circuit device, comprising:  2. In Claim 1,  A semiconductor integrated circuit device, comprising: a circuit element for handling a digital signal having a signal amplitude corresponding to an operation voltage; and a second semiconductor region separated from the first semiconductor region by a direct current.  3. In Claim 2,  Each of the first and second semiconductor regions includes a second conductivity type semiconductor region in which the first conductivity type MISFET is formed, and a first conductivity type semiconductor region in which the first conductivity type MISFET is formed.  The first and second conductivity type semiconductor regions are formed deeper than the first and second conductivity type semiconductor regions, and are formed in the first conductivity type semiconductor region for semiconductor isolation.  A semiconductor integrated circuit device, wherein the first conductivity type semiconductor region for semiconductor separation is formed on a first conductivity type semiconductor substrate. 4. In Claim 3, The first capacitance element and the first capacitance element are provided for the first conductivity type semiconductor region for semiconductor isolation, respectively. 5. In Claim 3,  A semiconductor integrated circuit device, wherein the first capacitance element and the second capacitance element are provided on the semiconductor substrate sandwiched between a first semiconductor region and a first semiconductor region, respectively.  6. In Claim 4,  A semiconductor integrated circuit, wherein the first capacitive element and the second capacitive element are provided with the first conductive semiconductor region in a part of the periphery thereof. 7. In Claim 5,  The semiconductor device, wherein the first capacitance element and the second capacitance element are provided with the first conductivity type semiconductor region for semiconductor isolation around the first capacitance element and the second capacitance element. 8. In Claim 1,  The semiconductor device according to claim 1, wherein the first capacitor and the second capacitor each include a MOS capacitor having a semiconductor region or a substrate to which the first capacitor is connected as one electrode. 9. A second semiconductor region in which a circuit element for handling a digital signal having a signal amplitude with respect to an operating voltage is formed; A semiconductor region or a substrate that separates the ^second semiconductor region in a DC manner, and a third capacitive element that couples the potential of the semiconductor region or the substrate around the second semiconductor region in an AC manner.  An inverting amplifier circuit for amplifying a voltage change passing through the third capacitive element, a fourth capacitive element for coupling an output signal of the inverting amplifier circuit to the semiconductor region or the substrate around the second semiconductor region in an AC manner, The first semiconductor region in which a circuit element that handles a signal or an analog signal that is separated from the second semiconductor region by a direct current and relatively small with respect to the operating voltage is formed. A semiconductor integrated circuit device comprising: a semiconductor region. 10. In claim 9,  Each of the first and second semiconductor regions includes a second conductivity type semiconductor region in which the first conductivity type M OS F E T is formed and a first conductivity type semiconductor region in which the second conductivity type M OS F E T is formed,  The first and second conductivity type semiconductor regions are formed deeper than the first and second conductivity type semiconductor regions, and are formed in the first conductivity type semiconductor region for semiconductor isolation.  The semiconductor integrated circuit device according to claim 1, wherein the first conductivity type semiconductor region for semiconductor separation is formed on a second conductivity type semiconductor substrate. 1 1. In claim 9,  A first capacitive element that is AC-coupled to a potential of the semiconductor region or the substrate around the first semiconductor region;  An inverting amplifier circuit for amplifying a voltage change passing through the first capacitive element; and a second capacitive element for ac coupling an output signal of the inverting amplifier circuit with the semiconductor region or substrate around the first semiconductor region. A semiconductor integrated circuit device further provided.  1 2. In claim 9,  The above-mentioned inverting amplifier circuit comprises a CM ソ ー ス S inverter circuit and a source follower output circuit for receiving the amplified signal. 1 3. In Claims 1 and 2,  A semiconductor integrated circuit device, wherein a resistance element is provided between an input and an output of the CM inverter circuit.  1 4. In claim 13, The semiconductor integrated circuit device, wherein the high resistance element is constituted by a MOSFET in which an intermediate voltage equal to or lower than a power supply voltage is applied to a gate. 1 5. In Claims 1 and 2,  The input voltage of the CM〇S inverter circuit must be such that the noise voltage generated by the CM〇S inverter circuit, whose input and output are coupled, is transmitted through a resistor element. Semiconductor integrated circuit device characterized by the following 1 6. In claim 15,  The CM〇S inverter circuit that forms the bias voltage has the same size ratio as the P-channel MOSF ET and N-channel M〇SF ET of the CM〇S inverter circuit used in the inverting amplifier circuit. And a P-channel type M◦ SFET and an N-channel type MOSFET with reduced size. 1 7. In Claims 1 and 2,  Between the input and output of the CM 0 S inverter circuit, the inverting amplifier is turned on when the inverting amplifier is inactive or reset, and is turned off when the inverting amplifier is operating. A semiconductor integrated circuit device provided with a MOS FET.  1 8. In Claims 1 and 2,  The CM〇S inverter circuit and the source follower output circuit include a MOSFET that is turned on when the inverting amplifier circuit is in operation, and is turned off when not in operation or sleep. A semiconductor integrated circuit device provided with a function of blocking a direct current flowing in a non-operating state.  1 9. In Claims 1 and 2, Between the input and the output of the CMOS inverter circuit, the inverting amplifier circuit is turned on with high resistance when the inverting amplifier circuit is in the operating state, A first MOSFET, sometimes turned off,  The input of the CM〇S inverter circuit is turned off when the inverting amplifier circuit is operating, and turned on when the inverting amplifier circuit is not operating to supply the power supply voltage or the circuit ground potential. A semiconductor integrated circuit device comprising a second M.SFET. 20. In claim 19,  The first M0 SFET is composed of a first conductivity type MOSFET, the second MOSFET is composed of a second conductivity type MOSFET, and the gates of the first MOS FET and the second MOSFET are controlled to perform the above operation. A semiconductor integrated circuit device wherein signals are commonly supplied. 2 1. In Claim 17 of the Claims,  The inverting amplifier circuit is activated when the corresponding first semiconductor region or a circuit formed in the first semiconductor region is activated, and the inverting amplifier circuit is deactivated. A semiconductor integrated circuit device, wherein the operation is performed when a circuit formed in the corresponding first semiconductor region or the second semiconductor region is inactivated.  22. In Claims 1 and 2,  A source follower circuit comprising an amplification M 0 S FET and a load means is further provided on the input side of the C M 0 S inverter circuit,  A semiconductor integrated circuit device, wherein a gate capacitance of the amplification M〇S FET is used as the first capacitance element.  23. a first semiconductor region in which a circuit element that handles a signal or an analog signal relatively small with respect to an operating voltage is formed; A semiconductor region or a substrate that separates the first semiconductor region in a DC manner, and inverts and amplifies a noise component of the semiconductor region or the substrate around the first semiconductor region to amplify the noise component around the first semiconductor region; Tell the board A noise reduction method for a semiconductor integrated circuit device, characterized in that said noise components are canceled or reduced by canceling each other. 2 4. In Claim 23,  A circuit element for handling a digital signal having a signal amplitude corresponding to an operating voltage is formed, and further includes a third semiconductor region which is separated from the first semiconductor region in a direct current manner. Reduction method.  25. In claim 23,  A noise reduction method for a semiconductor integrated circuit device, wherein the inverting amplification operation of the noise component is performed by a CMOS inverter circuit and a source follower output circuit.  26. In claim 23,  Wherein the detection of the noise component of the semiconductor region or the substrate and the transmission of the inverted and amplified noise component to the semiconductor region or the substrate are performed through a capacitor means. A method for reducing noise of a device. 27. A first semiconductor region in which a circuit element for handling a signal or an analog signal relatively small with respect to an operating voltage is formed;  A semiconductor region or a substrate that separates the first semiconductor region in a DC manner, and a first capacitive element that is AC-coupled to a potential of the semiconductor region or the substrate around the first semiconductor region.  An inverting amplifier circuit for amplifying a voltage change passing through the first capacitive element; and a second capacitive element for ac coupling an output signal of the inverting amplifier circuit with the semiconductor region or substrate around the first semiconductor region. A semiconductor integrated circuit device, comprising: the first capacitive element and the second capacitive element surrounding a periphery of the first semiconductor region, and formed so as to have a substantially symmetrical shape. 2 8. In Claim 27, The first semiconductor region has a rectangular shape,  The first capacitance element and the second capacitance element are formed by guard rings including a pn junction, and are formed symmetrically in an L-shape corresponding to one diagonal line of the rectangular first semiconductor region. Semiconductor integrated circuit device.  2 9. In Claim 27,  The first semiconductor region has a rectangular shape,  The first capacitance element and the second capacitance element are formed by a guard ring including a pn junction, and divide the rectangular first semiconductor region into left and right or up and down symmetrically in a U-shape corresponding to a center line. A semiconductor characterized by being formed 30. a first semiconductor region in which a circuit element for handling a signal or an analog signal relatively small with respect to an operating voltage is formed;  A second semiconductor region in which a circuit element is formed by handling a digital signal corresponding to the operating voltage,  A third capacitive element that is AC-coupled to a potential of the semiconductor region or the substrate around the third semiconductor region; An inverting amplifier circuit for amplifying a voltage change passing through the third capacitive element; and a fourth capacitive element for coupling an output signal of the inverting amplifier circuit to the semiconductor region or the substrate around the second semiconductor region in an AC manner. A semiconductor integrated circuit device, comprising: the third capacitive element and the ^fourth capacitive element surrounding a periphery of the ^second semiconductor region, and formed so as to have a substantially symmetrical shape.  3 1. In claim 30,  The first semiconductor region has a rectangular shape, The first capacitance element and the second capacitance element are formed by guard rings including a pn junction, and are formed in an L-shape corresponding to one diagonal line of the rectangular first semiconductor region. A semiconductor integrated circuit device formed symmetrically.  3 2. In claim 30,  The first semiconductor region has a rectangular shape,  The first capacitance element and the second capacitance element are formed of a guard ring including a pn junction, and are formed symmetrically in a U-shape corresponding to a center line that divides the rectangular first semiconductor region into left and right or up and down. A semi-conductor characterized by being made 3 3. In claim 30,  A first capacitive element that is AC-coupled with a potential of the semiconductor region or the substrate around the first semiconductor region;  An inverting amplifier circuit for amplifying a voltage change passing through the first capacitive element; and a first capacitive element for coupling an output signal of the inverting amplifier circuit to the semiconductor region or the substrate around the first semiconductor region in an AC manner. A semiconductor integrated circuit device, further comprising: the first capacitive element and the second capacitive element surrounding a periphery of the first semiconductor region, and both are formed to have a substantially symmetrical shape. .