WO1998012750A1 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- WO1998012750A1 WO1998012750A1 PCT/JP1996/002722 JP9602722W WO9812750A1 WO 1998012750 A1 WO1998012750 A1 WO 1998012750A1 JP 9602722 W JP9602722 W JP 9602722W WO 9812750 A1 WO9812750 A1 WO 9812750A1
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- circuit
- substrate
- semiconductor substrate
- integrated circuit
- semiconductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/213—Design considerations for internal polarisation in field-effect devices
Definitions
- the present invention relates to a semiconductor integrated circuit device, and more particularly to an analog-to-analog gnodigital mixed semiconductor in which an analog circuit (analog module) and a digital circuit (digital module), which are functional circuit units, are integrated on the same semiconductor chip.
- the present invention relates to an effective technique for reducing the influence of noise generated by a digital circuit on an analog circuit via a common semiconductor substrate.
- analog to digital converters have analog modules such as pumps and digital modules such as microcomputers and memories mounted on the same semiconductor chip.
- ADCs analog to digital converters
- the demand for digital mixed-type semiconductor integrated circuits is expanding.
- analog-Z mixed digital type semiconductor integrated circuit device the noise is generated by a digital module (for example, a noise caused by a transient current generated when a digital clock rises or falls). Degradation of the performance of analog modules has become a major problem and needs to be solved.
- JP-A-58-70565 and JP-A-59-193046 disclose that noise generated in a digital circuit portion is mixed with an analog circuit portion. It states that the power supply wiring for the digital circuit and the analog circuit should be provided independently to prevent malfunction of the analog circuit.
- FIG. 1 shows the configuration of such a conventional integrated circuit.
- a low impurity concentration substrate 12 composed of an epitaxy layer is formed on a high impurity concentration bulk substrate 11 and has a low impurity concentration.
- An analog section 1 and a digital section 2 are formed inside the pure substance concentration board 12 to constitute an analog / digital mixed integrated circuit.
- the substrate bias power is supplied to the substrate 11 or the substrate 12, and the potential of the substrate 12 is maintained.
- the analog section 1 and the digital section 2 are coupled via the resistors of the common boards 12 and 11, the digital noise generated in the digital section 2 due to the board resistance coupling is transmitted to the analog section 1. Transmitted, often causing malfunctions in analog circuits.
- n-type wells are provided for an analog circuit and a digital circuit on a substrate of an integrated circuit.
- the n-type well contains a p-type well and forms an analog [one-way or digital circuit].
- This double cell structure separates the circuit parts from each other, and prevents digital noise from entering the analog part through the common substrate.
- Japanese Patent Application Laid-Open No. 2-27171567 describes a technique for insulating and separating a digital part and an analog part by using a substrate having an SOI structure and a separation groove reaching an insulating layer of the substrate having the SOI structure. Is described.
- guard band or guard ring As a circuit solution, a high impurity concentration diffusion layer called guard band or guard ring is provided on the surface of the substrate between the analog circuit and the digital circuit, and this is connected to an external power ground. It has been used to absorb digital noise and to suppress the transmission of noise to analog circuits. These methods are described in "Monthly Semiconductor World", 1993, 1 Jj (p.174-177). Disclosure of the invention
- the power supply wiring (V cc) and the ground wiring (GND) formed on the surface of the semiconductor chip are independent of the analog circuit and the digital circuit, respectively. It is formed so that direct noise from the power supply wiring (V cc) and the ground wiring (GND) rarely affect each other.
- the encapsulant (LSI package) is mounted on a mounting substrate such as a printed wiring board, the ground wiring (GND) of the analog circuit and digital circuit is sealed (LSI package).
- the grounding wire (GND) on the mounting board has a much lower impedance than the grounding wire (GND) formed on the semiconductor chip, the effect of noise is small.
- noise transmitted through the inside of a semiconductor chip, further transmitted through a metal lead frame on which a semiconductor chip is mounted, and further transmitted through a metallic lead frame mounted with a semiconductor chip. Is not taken into account and is not enough to reduce and prevent noise.
- the semiconductor chip 21 is usually mounted on a metal lead frame, and a conductive material 23 such as silver paste is used to attach the chip support portion (die pad) 22 of the lead frame. Fixed.
- a sealing material such as a lead portion of a lead frame and a resin is omitted for convenience of explanation.
- the resistance of the silicon integrated circuit board 3 in the vertical direction is the lower part of the digital module 25.
- the resistance of the silicon integrated circuit board 3 in the horizontal direction is about 100 ⁇ in the digital module section 25 and about 10 ⁇ in the lower part of the analog module 24. It is about 50 ⁇ between digital modules 25.
- the path 2 The resistance of 6 is about 16.5 ⁇ .
- the noise generated by the digital module 25 is transmitted in the vertical direction, reaches the chip support 22 once, propagates through the chip support 22, and is transmitted from the lower part of the analog module 24.
- the total resistance of the path 27, which reenters the silicon integrated circuit board 3 and is transmitted to the analog module in the vertical direction, is sufficient for the resistance of the metal chip support portion 12 to be greater than the resistance of the silicon integrated circuit board 3. , It is about 15 ⁇ . This is less than 1 ⁇ 10 of the resistance of the path 26.
- Encapsulant LSI package
- the digital module or al noise transmitted to the chip supporting portion 2 2 there is a problem that the probability of returning to the surface of the silicon substrate is high, and the electrical reliability of the mixed analog / digital type semiconductor integrated circuit is further reduced.
- the thickness of the epitaxial layer 12 corresponding to the silicon integrated circuit substrate 3 shown in FIG. 2 is thin, the resistance in the vertical direction with respect to the horizontal direction is further reduced. Become smaller.
- the bottom surface of the epitaxial layer 12 is in contact with the high impurity concentration substrate, that is, the low-resistance impurity semiconductor 11, which serves as a metal chip support portion 22 of the silicon integrated circuit substrate 3 in FIG. .
- the noise generated by the digital module is more likely to be propagated to the analog module, and the reliability of the mixed analog / digital semiconductor integrated circuit device is reduced.
- the SOI structure substrate for insulation membrane separation is effective in decoupling of the low-frequency signal c, however, the SOI structure substrate is of relatively high frequency thin insulating film with ⁇ noise generated by the digital module There is a problem that noise cannot be cut off sufficiently due to capacitive coupling.
- the SOI structure substrate is economically disadvantageous, such as requiring a special process for forming an insulating film.
- the SOI structure substrate cannot supply ground potential (GND) from the back side of the substrate due to its structure, it is disadvantageous in terms of noise absorption efficiency, and it is also difficult to use analog modules that are strictly accurate. It is also disadvantageous in stabilizing the substrate potential. For this reason, when an SOI structure substrate is used, there is a problem that the electrical reliability of a mixed analog / digital type semiconductor integrated circuit device is reduced.
- GND ground potential
- the substrate between the digital circuit and the analog circuit is separated, so that the influence of noise due to the substrate coupling is reduced.
- the process steps are complicated, and a voltage gradient due to noise is apt to occur on the substrate of each separated circuit region structurally, and it is difficult to keep the substrate potential of each circuit region uniform.
- the non-uniformity of the substrate potential degrades the balance of, for example, a differential type analog circuit, and causes a problem of limiting the effect of reducing common mode noise.
- the digital module support is connected independently to the digital module support, and these analog module support and digital module support are connected via independent analog module ground leads and digital module ground leads.
- the method of connecting to the ground wiring (GND) of the mounting board was also studied by the present inventors.
- the analog module ground lead terminal and the digital module ground lead terminal each have a non-negligible lead 'inductance.
- the noise current due to the operation of the digital module is reduced from the digital module of the semiconductor chip to the ground wiring (GND) of the mounting board via the digital module support section and the lead of the digital module ground lead terminal.
- the digital module and the digital module support are not maintained at the virtual ground potential, and a noise voltage is generated due to the noise current flowing through the lead inductance.
- the analog module generates a large-amplitude output signal
- the noise current due to the operation of the digital module is transferred from the digital module of the semiconductor chip to the analog module supporting portion and the analog module ground lead terminal. Since the ground wiring (GND) of the mounting board flows through the lead's inductance, the analog module and the analog module support are not maintained at the virtual ground potential, and the noise due to the noise current flowing through the lead's inductance A voltage is generated.
- the present invention has been made based on the results of the study by the inventors of the present invention as described above, and an object of the present invention is to provide a semiconductor integrated circuit device capable of solving the problem of circuit performance degradation or malfunction. To do.
- a first functional circuit portion (2) is formed in a first surface region of the main surface, and a first voltage detection region (6a) and a first voltage control region (6b) are formed near the first surface region of the main surface.
- a first substrate support member (4b) made of a conductive material connected to a first back surface region of the back surface of the semiconductor substrate (3) located below the first functional circuit portion;
- a reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
- An inverting input terminal (1) of the amplifier circuit (7a) is connected to the first voltage detection region (6a) on the main surface of the semiconductor substrate (3);
- An output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6b) on the main surface of the semiconductor substrate (3) (see FIG. 3).
- the first substrate support member (4b) is not connected to the ground wiring (GND) of the mounting board via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplification board.
- the feedback operation of the circuit (7a), the first voltage detection area (6a), the first voltage control area (6b), and the first substrate support member (6) on the main surface of the semiconductor substrate (3) 4b) is virtually set to the above-mentioned reference voltage (GND).
- the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member (4b) to substantially the reference voltage (GND), and the feedback of the amplifier circuit (7a) does not contribute. The action contributes.
- the application of the reference voltage (GND) to the non-inverting input terminal (+) of the amplifier circuit (7a) is performed by the ground lead terminal of the semiconductor integrated circuit device. a) If the stray capacitance between the inverting input terminal (1) and the non-inverting input terminal (+) can be neglected, the lead of the ground lead terminal of the non-inverting input terminal (+). The noise power due to the noise current flowing through the device also becomes a negligible level.
- the first voltage detection area (6a) and the first voltage control area (6b) correspond to the first functional circuit section (2) of the first surface area of the main surface of the semiconductor substrate (3). ), Formed by a conductive double ring guard band formed around
- the first voltage detection area (6a) and the first substrate supporting member (4b) are set to substantially the reference voltage (GND), and the first function
- the feature is that it can reduce the complexity of the circuit section (2) (see Fig. 3 BB).
- the first voltage detection area (6a) and the first voltage control area (6b) are formed around the first functional circuit section (2). Since the guard band is a heavy ring guard band, the noise propagated between the first functional circuit section (2) and other portions of the semiconductor substrate (3) can be reduced more completely.
- a semiconductor integrated circuit device according to a more specific embodiment of the present invention
- a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
- the first voltage detection area (6a) and the first substrate support member (4b) are set to substantially the reference voltage (GND). (See Fig. 3).
- noise propagated between the first functional circuit unit (2) and the second functional circuit unit (1) can be reduced.
- a second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the second substrate support member (4a) is set to approximately the reference voltage (GND) (see FIG. 3).
- Another conductive guard band (6c) is formed around (1),
- the other guard band (6c) is set to approximately the reference voltage.
- Another conductive guard band (6c, 6d) is formed around (1) around the second functional circuit portion in the second surface region of the main surface of the semiconductor substrate (3),
- a second substrate support member (4a) made of a conductive material connected to a second back surface area located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the semiconductor substrate includes another amplifier circuit (7b),
- the other guard bands are a second voltage detection region (6c) and a second voltage control region (6d) composed of the guard band of another double ring.
- the above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
- the inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second voltage detection area (6c) on the main surface of the semiconductor substrate (3),
- the output terminal of the other amplifier circuit (7b) is connected to the second voltage control region (6d) on the main surface of the semiconductor substrate (3),
- the second voltage detection area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 6). According to such a more specific embodiment, it is possible to reduce noise propagated between the first functional circuit section (2) and the second functional circuit section (1).
- One and the other of the first functional circuit section (2) and the second functional circuit section (1) are a circuit for processing a digital signal and a circuit for processing an analog signal. 3 to 6).
- a first functional circuit portion (2, 1) is formed in a first surface region of the main surface, and a first voltage control region (6a, 6c) is formed in the vicinity of the first surface region of the main surface,
- a first substrate support member (4b, 4b) made of a conductive material connected to a first back surface region located below the first functional circuit portion (2, 1) on the back surface of the semiconductor substrate (3).
- the reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a, 7b).
- the inverting input terminal (1) of the amplifier circuit (7a, 7b) is connected to the first substrate support member (4b, 4a),
- the output terminal of the amplifier circuit (7a, 7b) is connected to the first voltage control region (6a, 6c) on the main surface of the semiconductor substrate (3). See Figures 7 and 8.)
- the first substrate support member (4b, 4a) is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplifier circuit (7a 7b) is virtually set to the above-mentioned reference power (GND) virtually.
- the first substrate supporting members (4b, 4a) are substantially the same in phase opposite to the generated noise as virtually set to the reference voltage (GND).
- An amplitude cancellation signal is applied from the output terminal of the amplifier circuit (7a, 7b) to the first voltage control area (6a, 6c).
- the potential fluctuation of the first substrate support member (4b, 4a) is also reduced, and even if the stray capacitance cannot be ignored, the ground lead terminal of the non-inverting input terminal (+) can be used.
- the noise voltage due to the noise current flowing through the lead ⁇ inductance is also at a negligible level.
- the first voltage control region (6c) is formed by a guard band of a conductive ring formed around the first functional circuit portion (1) on the first surface region on the main surface of the semiconductor substrate (3). Composed,
- the first voltage control area (6c) and the first substrate support member (4a) are set to substantially the reference voltage (GND), and noise can be reduced. (See Fig. 8).
- the first voltage control area (6c) is a guard band of a ring formed around the first functional circuit section (1). Noise transmitted between the functional circuit section (1) and other parts of the semiconductor substrate (3) can be reduced more completely.
- a second functional circuit portion (2) is formed in a second surface region of the main surface of the semiconductor substrate (3);
- the feedback operation of the amplifier circuit (7b) sets the first voltage control area (6c) and the first substrate support member (4a) to approximately the reference voltage (GND). (See Figure 8).
- the second substrate support member (4b) made of a conductive material connected to the second back surface region located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the second substrate support member (4b) is set to approximately the reference voltage (GND) (see FIG. 9).
- the other guard band (6a) is set to approximately the above-mentioned reference voltage (GND) (see Fig. 9).
- Another conductive guard band (6a) is formed around the second functional circuit portion (2) in the second surface region on the main surface of the semiconductor substrate (3), A second substrate support member (4b) made of a conductive material connected to a second back surface area located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the semiconductor substrate (3) includes another amplifier circuit (7a),
- the other guard band is a second voltage control region (6a) composed of a ring guard band,
- the reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7a),
- the inverting input terminal (1) of the other amplifier circuit (7a) is connected to the second substrate support member (4b) of the semiconductor substrate (3),
- the output terminal of another amplifier circuit (7a) is connected to the second voltage control region (6a) on the main surface of the semiconductor substrate (3).
- the second voltage control region (6a) and the second substrate support member (4b) are set to substantially the reference voltage (GND) by a feedback operation of the other amplifier circuit (7a). (See Figure 9).
- One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
- a first functional circuit portion (2) is formed in a first surface region of the main surface, a first voltage control region (6a) is formed in the vicinity of the first surface region of the main surface, and an amplifier circuit (7a) is formed. ) Containing a semiconductor substrate (3);
- a first substrate support member (4b) made of a conductive substance connected to a first back surface region located below the first functional circuit portion (2) on the back surface of the semiconductor substrate (3);
- the first voltage control region (6a) is constituted by a guard band of a conductive ring formed around the first functional circuit portion (2) in the first surface region of the main surface of the semiconductor substrate.
- a reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
- the inverting input terminal (-) of the amplifier circuit (7a) is connected between the semiconductor substrate (3) and the first substrate support member (4b) so that the amplifier circuit (7a) detects noise due to circuit operation. Connected to at least one of them, The output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6a) on the main surface of the semiconductor substrate (3) by connecting the output terminal of the amplifier circuit (7a). The output signal of the terminal is characterized by reducing the noise (see FIGS. 3 and 7).
- the first voltage control area (6a) is provided with the first function. Since it is constituted by a guard band of a conductive ring formed around the circuit section (2), the gap between the first functional circuit section (2) and the other portion of the semiconductor substrate (3) is provided. Propagated noise can be reduced more completely.
- a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
- the second substrate support member (4a) made of a conductive material connected to the second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the second substrate support member (4a) is set to approximately the first voltage (see FIGS. 3 and 7).
- a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
- Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region on the main surface of the semiconductor substrate (3);
- the other guard band (6c) is set to approximately the reference voltage (G ND) (see Figs. 4 and 7).
- a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
- Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region of the main surface of the semiconductor substrate,
- a second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
- the semiconductor substrate (3) includes another amplifier circuit (7b),
- the other guard band (6c) is the second voltage composed of the ring guard band. Control area,
- the above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
- the inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second substrate support member of the semiconductor substrate (3),
- An output terminal of the other amplifier circuit (7b) is connected to the second voltage control region on the main surface of the semiconductor substrate.
- the second voltage control area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 9).
- One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
- the substrate support member is constituted by a packaged metal lead frame.
- the above semiconductor substrate is a low impurity concentration semiconductor layer formed on a silicon substrate (13).
- the configuration of the present invention can be achieved by a simple process, it is possible to improve the electrical reliability of a semiconductor device including a mixed analog / digital semiconductor integrated circuit device and to reduce the cost.
- FIG. 1 is a diagram for explaining a conventional integrated circuit structure in a mixed analog / digital type semiconductor integrated circuit device.
- FIG. 1 is a model diagram of a conventional semiconductor integrated circuit device including a semiconductor integrated circuit.
- FIG. 3 is a diagram illustrating an analog / digital Z-mixed semiconductor integrated circuit device according to a first embodiment of the present invention.
- FIG. 4 is a diagram for explaining a diagram for explaining another analog / digital Z-mixed semiconductor integrated circuit device according to the first embodiment of the present invention.
- FIG. 5 is a diagram for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a second embodiment of the present invention.
- FIG. 6 is a view for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a third embodiment of the present invention.
- FIG. 7 is a diagram illustrating a mixed analog / digital semiconductor integrated circuit device according to a fourth embodiment of the present invention.
- FIG. 8 is a diagram illustrating an analog-Z digital mixed type semiconductor integrated circuit device according to a fifth embodiment of the present invention.
- FIG. 9 is a diagram illustrating a mixed analog / digital type semiconductor integrated circuit device according to a sixth embodiment of the present invention.
- FIG. 10 is a diagram illustrating an analog / digital mixed semiconductor integrated circuit device according to a seventh embodiment of the present invention.
- FIG. 1 is a view for explaining a substrate structure of an analog / digital Z-type mixed semiconductor integrated circuit device according to an eighth embodiment of the present invention.
- FIG. 12 is a view for explaining another substrate structure of an analog / digital mixed semiconductor integrated circuit device according to a ninth embodiment of the present invention. -Best mode for carrying out the invention
- FIGS. 3 and 4 show a semiconductor integrated circuit device according to a first embodiment of the present invention.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of the present embodiment.
- the analog section 1 is configured with a circuit that handles weak analog signals such as an amplifier and an A / D converter
- the digital section 2 is configured with digital circuits such as logic and memory.
- a low-concentration p-type or n-type silicon substrate force f is used for the integrated circuit substrate 3.
- independent conductor parts 4a and 4b which are electrically separated from each other, are connected to positions corresponding to the lower part of the analog part 1 and the digital part 2 area, respectively. Is done.
- the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
- the conductor portions 4a and 4b can be connected to the substrate 3 using a conductive adhesive such as silver paste, for example.
- a conductive adhesive such as silver paste, for example.
- ring-shaped guard bands 6a and 6b of a high concentration p-type or n-type diffusion layer are arranged and formed.
- guard bands 6a and 6b are integrated circuit boards 3 W
- they serve as electrodes of the integrated circuit substrate 3 composed of the resistors 5a and 5b.
- the board noise generated in the digital section 2 is canceled, and the noise canceling signal generating circuit 73 is connected to the guard bands 6a and 6b.
- the noise canceling signal generation circuit 7a is composed of a circuit such as an operational amplifier.
- the inverting input terminal (1) is connected to the guard band 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the ground. Connect to band 6b.
- the noise canceling signal generating circuit 7a is formed inside the integrated circuit board 3, and is preferably formed inside the analog section 1 in order to make it insensitive to noise.
- the noise canceling signal generating circuit 7a can generate a canceling signal for canceling the original noise generated in the digital section.
- a signal is generated at the output terminal so that the potential of the guard band 6a connected to the inverting human input terminal (1) becomes a virtual ground.
- the guard band 6a force 5 ' is ideally virtual grounded because the conductor 4b is grounded via the force resistance 5a. It means that it becomes a potential. Therefore, since the noise canceling signal that comprehensively cancels the noise voltage source generated in the digital section 2 is generated by the noise canceling signal generation circuit 7a, the conductor section 4 is maintained at the ground potential free of flicker noise. Will be.
- the first substrate support member 4b is not connected to the ground wiring GND of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the ground of the amplification circuit 7a.
- the first voltage detection region 6a, the first voltage control region 6b, and the first substrate support member 4b on the main surface of the semiconductor substrate 3 are virtually set to the reference voltage GND by the feedback operation.
- the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member 4b to the substantially reference voltage GND, but the feedback operation of the amplifier circuit 7a contributes.
- the reference voltage GND is applied to the non-inverting input terminal + of the amplifier circuit 7a by the ground lead terminal of the semiconductor integrated circuit device. If the stray capacitance between them can be neglected, the noise voltage due to the noise current flowing through the lead and inductance of the ground lead terminal of the non-inverting input terminal will also be at a negligible level.
- the substrate potential of the analog section 1 may be obtained by directly grounding the conductor section 4a connected to the bottom surface of the integrated circuit board 3 of the analog section 1 as shown in FIG. As described above, by directly grounding the guard band 6c of the analog section 1, the substrate potential of the analog section 1 can be supplied, and a stable constant potential can be maintained.
- noise generated by the digital circuit is canceled in the area of the digital section 2 of the integrated circuit board 3 by the noise canceling signal generation circuit 7a and the conductor section 4b. Since the data is erased, digital noise applied to the analog circuit of the analog unit 1 can be suppressed. Further, the ground potential is supplied to the bottom surface of the integrated circuit board 3 of the analog section 1 by the conductor section 4a independent of the digital section, so that the board potential can be kept stable and uniform. For this reason, analog circuits are often used to prevent degradation of characteristics due to noise, such as deterioration of the balance of the high-precision differential circuits used, and to provide a stable and highly reliable analog / digital mixed integrated circuit device. it can.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3.
- ring-shaped guard bands 6c and 6d made of a diffusion layer having a high impurity concentration and serving as electrodes of the integrated circuit board 3 are arranged.
- Independent conductor sections 4a and 4b are connected to the positions corresponding to section 1 and digital section 2, respectively.
- the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
- the guard bands 6c and 6d are connected to a noise canceling signal generation circuit 7 '.
- the noise canceling signal generation circuit 7b is composed of a circuit such as an operational amplifier.
- the inverting input terminal (1) is connected to the guard band 6c, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard band 6d.
- the noise canceling signal generation circuit 7b generates an output signal on the guard band 6d by the feed knock operation so that the guard band 6c is always at the virtual ground.
- the conductor 4a is also fixed to the ground potential, and the noise canceling signal generating circuit 7b generates a canceling signal to cancel the noise arriving from the digital section. And apply to guard band 6d.
- the substrate of the analog section 1 can be maintained at a stable potential without noise.
- the substrate potential of the digital section 2 is connected to the conductor section 4 b connected to the bottom of the board or the guard band 6 a formed on the board surface to a stable ground potential, and biased independently of the analog section 1. Power can be supplied to suppress noise generated on the board.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG.
- End Ring guard bands 6c and 6d and ring guard bands 6a and 6b are arranged around the ring section 1 and the digital section 2, respectively.
- the independent conductor portions 4a and 4b are connected to the positions corresponding to the analog portion 1 and the digital portion 2, respectively.
- the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
- the noise canceling signal generation circuit 7b is connected to the guard bands 6c and 6d of the analog section 1, and the noise canceling signal generation circuit 7a is connected to the guard bands 6a and 6b of the digital section 2. .
- the noise cancellation signal generation circuit is composed of circuits such as an operational amplifier.
- the inverting input terminal (1) is connected to guard bands 6c and 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard bands 6 d and 6 b respectively.
- the noise canceling signal generating circuit 7b generates an optimal noise canceling signal by feedback operation so that the guard band 6c of the analog opening section 1, that is, the conductor section 4a is always at virtual ground. And apply it to guard band 6d.
- the noise canceling signal generating circuit 7a of the digital section 2 generates an optimal digital noise canceling signal by a feedback operation and applies the signal to the guard band 6b.
- the guard band 6a that is, the conductor portion 4b is held at the virtual ground, and the original substrate noise generated in the digital portion 2 can be eliminated.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
- independent conductor portions 4a and conductor portions 4b are respectively connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively.
- the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
- a ring-shaped guard band 6a is arranged around the digital section 2, and a ring-shaped guard band 6c is arranged around the analog section 1.
- the noise canceling signal generating circuit 7a is composed of a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor 4b of the digital section 2.
- the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6a of the digital section.
- the noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6a, and the conductor 4b, that is, the bottom surface of the substrate of the digital section 2 is virtually grounded. It works to keep the potential. This is because the conductor portion 4b is virtually grounded, so that the conductor portion 4b is not easily affected by parasitic elements of the external lead wiring. This is because a steady ground current does not flow compared to the case where the ground is directly grounded.
- the substrate potential of the analog section 1 is set by grounding the guard band 6c disposed around the analog section 1 or by grounding the conductor section 4a on the bottom surface of the integrated circuit board 3 of the analog section 1. Supply a constant voltage. Even if noise remains in the conductor section 4b of the digital section 1, the influence of the board noise on the analog section 1 can be reduced by independently controlling the conductor section 4a.
- the first substrate support member 4b is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is substantially referenced by the feedback operation of the amplifier circuit 7a. Virtually set to voltage (GND). At this time, even if noise is generated, the first substrate supporting member 4b generates a canceling signal having substantially the same phase and the same amplitude as that of the generated noise so that it is virtually set to the substantially reference voltage (GND).
- the output terminal of a is applied to the first voltage control area 6a.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
- the conductor portion 4a is connected only to the position corresponding to the analog portion 1, and the conductor portion is not formed at the position corresponding to the digital portion 2.
- the semiconductor integrated circuit is fixed and mounted on a package via the conductor portion 4a.
- a guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2.
- the noise canceling signal generating circuit 7 b is configured by a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor section 4 a of the analog section 1.
- the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to guard band 6c of analog section 1.
- the noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6c, so that the conductor portion 4a, that is, the bottom surface of the analog portion 1 is virtually grounded. It works to keep the potential.
- the substrate potential of the digital section 2 supplies a constant voltage by grounding the guard band 6a disposed around the digital section 2.
- the conductor section 4a provided on the lower surface of the analog section 1 is virtually grounded, so that the substrate potential of the analog section 1 is directly constant. Therefore, the effect of substrate noise from the digital section can be suppressed.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG.
- Ring-shaped guard bands 6c and 6d and ring-shaped guard bands 6a and 6b are arranged around the antenna opening section 1 and the digital signal section 2, respectively.
- independent conductor portions 4a and 4b are connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively.
- the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
- a guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2.
- the noise canceling signal generation circuits 7b and 7a are composed of circuits such as operational amplifiers.
- the inverting input terminal (1) is directly connected to the conductor 4a of the analog unit 1 and the conductor 4b of the digital unit 2, respectively. It is connected.
- the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6c of the analog unit 1 and the guard band 6a of the digital unit 2.
- the noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation, applies these signals to the guard band 6c, and applies the conductor portion 4a, that is, the bottom surface force of the analog portion 1 to the virtual ground. It works to keep the potential.
- the noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by the feedback operation, applies these to the guard band 6a, and the conductor 4b, that is, the bottom of the substrate of the digital section 2 It works to keep the virtual ground potential.
- An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
- a ring-shaped guard band 6a is arranged around the digital section 2
- a conductor section 4 is provided on the bottom of the integrated circuit board 3, and the board bottoms of the analog section 1 and the digital section 2 are connected in common. Is done.
- the semiconductor integrated circuit is fixed to an insulating package via the conductor portion 4 and mounted.
- the inverting input terminal (1) of the noise canceling signal generation circuit 7a is directly connected to the conductor section 4, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is the guard band 6a of the digital section 2. It is connected to the.
- the noise canceling signal generation circuit 7a performs a feedback operation so that the bottom surface force of the integrated circuit board common to the conductor portion 4, that is, the analog portion 1 and the digital portion 2, is imaginary, and is always optimal. Generate a noise canceling signal and apply it to guard band 6a.
- the signal is generated on the board of the digital section 2 by the noise canceling signal generation circuit 7a.
- the digital noise generated is canceled out and reduced, and the substrate noise of the digital unit 2 is reduced even on the substrate of the analog unit 1, whereby a stable substrate bias potential is obtained.
- the substrate noise generated by these digital circuit areas is generally a sum of positive and negative digital noises, and thus has a small value centered at 0. Since the noise is reduced by canceling the noise, the noise canceling signal may be a relatively small value. Therefore, the noise canceling signal generation circuit 7a can be configured with low power consumption.
- FIG. 11 eighth and ninth embodiments of the present invention relating to the configuration of the conductor portion will be described with reference to FIGS. 11 and 12.
- FIG. 11 eighth and ninth embodiments of the present invention relating to the configuration of the conductor portion will be described with reference to FIGS. 11 and 12.
- a high impurity concentration layer 8a of ap + type semiconductor is provided inside or on the bottom of a low impurity concentration substrate 10 of a p-type semiconductor, which is a silicon substrate, corresponding to the analog section 1 and the digital section 2. , 8b respectively.
- These high-concentration layers 8a and 8b serve as the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and reduce the substrate noise together with the noise canceling signal generation circuits 7a and 7b. Can be achieved.
- the low impurity concentration substrate 14 consisting of an epitaxy layer on the high impurity concentration silicon substrate 13 of p + type semiconductor, which is a silicon bulk substrate, corresponds to the analog unit 1 and the digital unit 2.
- the high impurity concentration buried layers 9a and 9b are formed.
- These high impurity concentration buried layers 9a and 9b play the role of the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and the substrate noise together with the noise canceling signal generating circuits 7a and 7b. Can be reduced.
- the high-concentration layers 8a and 8b or the buried layers 9a and 9b act as a conductor, Join.
- the boards of the digital section 2 and the analog section 1 are not separated, but in combination with a noise canceling signal generation circuit, the board noise of the digital section is reduced, noise transmission is suppressed, and the board potential of the analog section is reduced. Can be kept constant.
- the high impurity concentration layers 8a and 8b and the high impurity concentration buried layers 9a and 9b of this embodiment can be applied to the lower surface of the well of the integrated circuit to stabilize the well substrate. It can also be applied to a substrate. According to this embodiment, it is possible to always obtain the same noise suppression effect regardless of the mounting conditions.
- the noise cancellation signal generation circuits 7a and 7b according to the embodiment of the present invention are configured on the same integrated circuit to reduce the substrate noise of the digital circuit, prevent the propagation to the analog circuit, and reduce the substrate potential of the analog circuit. It is possible to maintain the stability and improve the electrical reliability of the analog-Z digital mixed integrated circuit.
- the present invention relates to a semiconductor integrated circuit device, in particular, an analog / digital mixed semiconductor integrated circuit in which an analog circuit (analog module) and a digital circuit (digital module) which are functional circuit units are integrated on the same semiconductor chip. It can be used to reduce the effects of noise generated by digital circuits on analog circuits via a common semiconductor substrate.
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Abstract
Description
明 細 書 Specification
半導体集積回路装置 技術分野 Semiconductor integrated circuit device
本発明は、 半導体集積回路装置に関し、 特に、 機能回路部であるアナログ回路 (アナログモジュール) とデジタル回路 (デジタルモジュール) とを同一半導体 千ップ上に集積してなるアナ口グノデジタル混在形半導体集積回路装置において、 デジタル回路の発生する雑音が共通半導体基板を経由してアナログ回路に及ぼす 影響などを低減するための有効な技術に関する。 背景技術 The present invention relates to a semiconductor integrated circuit device, and more particularly to an analog-to-analog gnodigital mixed semiconductor in which an analog circuit (analog module) and a digital circuit (digital module), which are functional circuit units, are integrated on the same semiconductor chip. In an integrated circuit device, the present invention relates to an effective technique for reducing the influence of noise generated by a digital circuit on an analog circuit via a common semiconductor substrate. Background art
近年、 移動体無線やビデオカメラの小型化が要求されており、 それに内蔵され る電子部品としての半導体装置の小型化の要求が大きくなっている。 それに伴い、 アナ口グーデジタル変換器 ( Analog to Digital Converter: 以下、 ADCという) ゃァ ンプ等のアナ口グモジュールとマイコンやメモリ等のデジタルモジュールとが同 一半導体チップ上に搭載されたアナログ Zデジタル混在形半導体集積回路の需要 が拡大してきている。 さらに、 最近では、 上記アナログノデジタル混在形半導体 集積回路のアナログモジュールの高精度化が要求されている。 そのため、 上記ァ ナ口グ Zデジタル混在形半導体集積回路装置の内部において、 デジタルモジュ一 ルで発生する雑音 (例えば、 デジタルクロックの立上り、 あるいは、 立ち下がり 時に発生する過渡電流による雑音) に起因するアナログモジュールの性能劣化が 大きな問題となり、 その解決が必要とされている。 In recent years, there has been a demand for miniaturization of mobile radios and video cameras, and there has been an increasing demand for miniaturization of semiconductor devices as electronic components incorporated therein. Accordingly, analog to digital converters (hereinafter referred to as ADCs) have analog modules such as pumps and digital modules such as microcomputers and memories mounted on the same semiconductor chip. The demand for digital mixed-type semiconductor integrated circuits is expanding. Furthermore, recently, there has been a demand for higher precision analog modules of the above-mentioned analog / digital mixed semiconductor integrated circuit. For this reason, in the above-described analog-Z mixed digital type semiconductor integrated circuit device, the noise is generated by a digital module (for example, a noise caused by a transient current generated when a digital clock rises or falls). Degradation of the performance of analog modules has become a major problem and needs to be solved.
上記アナログ Zデジタル混在形半導体集積回路装置に関しては、 例えば、 特開 昭 5 8— 7 0 5 6 5号公報、 特開昭 5 9— 1 9 3 0 4 6号公報、 特開平 2— 2 5 1 9 7 0号公報、 特開平 2— 2 7 1 5 6 7号公報に記載されている。 Regarding the analog-Z digital mixed type semiconductor integrated circuit device, see, for example, JP-A-58-70565, JP-A-59-193046, and JP-A-2-25. This is described in Japanese Patent Application Laid-Open No. 970/1990 and Japanese Patent Application Laid-Open No. 2-271715 / 1990.
上記特開昭 5 8— 7 0 5 6 5号公報と上記特開昭 5 9— 1 9 3 0 4 6号公報に は、 デジタル回路部で発生した雑音がアナログ回路部に混人して、 アナログ回路 が誤動作することを防止するために、 デジタル回路とアナ口グ回路の電源配線を 独立して設ける旨が記載されている。 JP-A-58-70565 and JP-A-59-193046 disclose that noise generated in a digital circuit portion is mixed with an analog circuit portion. It states that the power supply wiring for the digital circuit and the analog circuit should be provided independently to prevent malfunction of the analog circuit.
アナログ回路とデジタル回路とを同一基板上に形成するアナ口グ /デジタル混 在形集積回路においては、 デジタル回路動作にともなって発生する雑音が、 集積 回路基板を介してアナログ回路に到達し、 アナログ回路に誤動作を与える問題が ある。 また、 アナログ回路が大振幅出力信号を発生する場合には、 アナログ回路 動作にともなってデジタル回路が、誤動作する場合もある。 In a mixed analog / digital integrated circuit in which an analog circuit and a digital circuit are formed on the same substrate, noise generated by the operation of the digital circuit reaches the analog circuit via the integrated circuit board, and the analog circuit There is a problem of malfunctioning the circuit. When an analog circuit generates a large-amplitude output signal, a digital circuit may malfunction due to the operation of the analog circuit.
図 1は、 このような従来の集積回路の構成を示す。 高不純物濃度のバルク基板 1 1の上に、 ェピタキシャル層からなる低不純物濃度基板 1 2が形成され、 低不 純物濃度基板 1 2の内部にアナ口グ部 1 とデジタル部 2とが形成され、 アナログ ノデジタル混在集積回路が構成される。 基板バイアス電源は基板 1 1あるいは基 板 1 2に供給され、 基板 1 2の電位が保たれる。 この場合、 アナログ部 1とデジ タル部 2は共通基板 1 2、 1 1の抵抗を介して結合されているため、 この基板抵 抗結合によってデジタル部 2で発生したデジタル雑音は、 アナログ部 1に伝達さ れ、 しばしば、 アナログ回路に誤動作を与えることになる。 FIG. 1 shows the configuration of such a conventional integrated circuit. A low impurity concentration substrate 12 composed of an epitaxy layer is formed on a high impurity concentration bulk substrate 11 and has a low impurity concentration. An analog section 1 and a digital section 2 are formed inside the pure substance concentration board 12 to constitute an analog / digital mixed integrated circuit. The substrate bias power is supplied to the substrate 11 or the substrate 12, and the potential of the substrate 12 is maintained. In this case, since the analog section 1 and the digital section 2 are coupled via the resistors of the common boards 12 and 11, the digital noise generated in the digital section 2 due to the board resistance coupling is transmitted to the analog section 1. Transmitted, often causing malfunctions in analog circuits.
また、 従来のアナログ デジタル混在形集積回路においては、 ェピタキシャル 餍を用いず、 図 2のようにバルクシリコンの集積回路基板 3を用いることも多い c この場合も、 図 1 と同様に基板を介した結合雑音が問題になる。 Conventional analog / digital mixed type integrated circuits often use bulk silicon integrated circuit boards 3 as shown in Fig. 2 without using epitaxy c . The combined noise becomes a problem.
従来、 この問題を解決するために、 プロセス的には二重ゥエル構造や S 0 I (Silicon On Insulator)構造等が提案されている。 Conventionally, in order to solve this problem, a double-well structure or an S0I (Silicon On Insulator) structure has been proposed as a process.
上記特開平 2— 2 5 1 9 7 0号公報には、 集積回路の基板上にアナログ问路用 とデジタル回路用にそれぞれ独立の n形ゥエルを設ける旨が記載されている。 n 形ゥエルの内部には p形ゥエルが含まれ、 アナログ [口 1路あるいはデジタル回路が 構成される。 この二重のゥヱル構造によって、 互いの回路部の基板分離を図り、 デジタル雑音が、 共通基板を通してアナログ部に混入することを防ぐ。 The above-mentioned Japanese Patent Application Laid-Open No. 2-251970 describes that independent n-type wells are provided for an analog circuit and a digital circuit on a substrate of an integrated circuit. The n-type well contains a p-type well and forms an analog [one-way or digital circuit]. This double cell structure separates the circuit parts from each other, and prevents digital noise from entering the analog part through the common substrate.
上記特開平 2— 2 7 1 5 6 7号公報には、 S O I構造の基板及び上記 S O I構 造の基板の絶縁層に達する分離溝を用いて、 デジタル部とアナ口グ部を絶縁分離 する技術が記載されている。 Japanese Patent Application Laid-Open No. 2-27171567 describes a technique for insulating and separating a digital part and an analog part by using a substrate having an SOI structure and a separation groove reaching an insulating layer of the substrate having the SOI structure. Is described.
また、 回路的解決方法としては、 アナログ回路とデジタル回路との間の基板表 面にガ一ドバンドあるいはガ一ドリングと呼ばれる高不純物濃度の拡散層を設け て、 これを外部電源グランドに接続し、 デジタル雑音を吸収しアナログ回路への 雑音の伝達を抑制する方法など力'用いられている。 これらの方法は、 " 月刊セミ コンダクタワールド" 1 9 9 3年 1 Jj ( p 1 7 4 - 1 7 7 ) などに記載されてい る。 発明の開示 As a circuit solution, a high impurity concentration diffusion layer called guard band or guard ring is provided on the surface of the substrate between the analog circuit and the digital circuit, and this is connected to an external power ground. It has been used to absorb digital noise and to suppress the transmission of noise to analog circuits. These methods are described in "Monthly Semiconductor World", 1993, 1 Jj (p.174-177). Disclosure of the invention
本発明に関して本願発明者等が上記アナログノデジタル混在形半導体集積回路 の電気的信頼性を検討した結果を、 以下に述べる。 The results of the present inventors' studies on the electrical reliability of the analog / digital mixed semiconductor integrated circuit in the present invention are described below.
上記従来技術のアナログ Zデジタル混在形半導体集積回路においては、 半導体 チップ表面に形成された電源配線 (V c c ) と接地配線 (G N D ) とは、 アナ口 グ回路とデジタル回路とで各々独立して形成されており、 電源配線 (V c c ) と 接地配線 (G N D ) とから直接雑音が相互に影響することは少ない。 また、 プリ ント配線基板等の実装基板上に封止体 ( L S Iパッケージ) 力'実装された状態で は、 アナログ回路とデジテル回路の各接地配線 (G N D ) は、 封止体 (L S Iノ ッケージ) 外部において上記実装基板上で共通の接地配線 (G N D ) に接続され る力、 実装基板状の共通の接地配線 (G N D ) は、 半導体チップ上に形成された 接地配線 (G N D ) よりも非常に低インピーダンスであるので雑音の影響は小さ い o In the conventional analog Z digital mixed type semiconductor integrated circuit described above, the power supply wiring (V cc) and the ground wiring (GND) formed on the surface of the semiconductor chip are independent of the analog circuit and the digital circuit, respectively. It is formed so that direct noise from the power supply wiring (V cc) and the ground wiring (GND) rarely affect each other. In addition, when the encapsulant (LSI package) is mounted on a mounting substrate such as a printed wiring board, the ground wiring (GND) of the analog circuit and digital circuit is sealed (LSI package). Externally connected to the common ground wiring (GND) on the mounting board Since the grounding wire (GND) on the mounting board has a much lower impedance than the grounding wire (GND) formed on the semiconductor chip, the effect of noise is small.
しかしながら、 上記従来技術では、 半導体チップ内部を伝わる雑音、 さらには、 半導体チップを搭載する金属製のリードフレームを伝わる雑音、 さらには、 半導 体チップを搭載する金属性のリードフレームを伝わる雑音に関しては考慮されて おらず、 雑音の低減、 防止には不十分である。 However, in the above conventional technology, noise transmitted through the inside of a semiconductor chip, further transmitted through a metal lead frame on which a semiconductor chip is mounted, and further transmitted through a metallic lead frame mounted with a semiconductor chip. Is not taken into account and is not enough to reduce and prevent noise.
図 2に示すように、 通常、 半導体チップ 2 1は、 金属製のリードフレーム上に 搭載され、 銀ペースト等の導電性材料 2 3によって、 リードフレームのチップ支 持部 (ダイパッ ド) 2 2に固定される。 尚、 リードフレームのリード部、 樹脂等 の封止材料は、 説明の便宜上省略する。 アナログ部 2 4 (アナログモジュール) とデジタル部 2 5 (デジタルモジユール) とを半導体チップ 2 1上に混在した場 合、 半導体チップ 2 1が搭載されたチップ支持部 2 2は、 全面が非常に低い抵抗 の導電体であるため、 デジタルモジュール 2 5で発生した雑音は、 チップ支持部 2 2を介する経路でアナログモジュール 2 4へ容易に伝達され、 アナログモジュ ール 2 4の性能劣化、 誤動作を引き起こす問題力 ^本願発明者等の検討により明ら かになつた。 As shown in FIG. 2, the semiconductor chip 21 is usually mounted on a metal lead frame, and a conductive material 23 such as silver paste is used to attach the chip support portion (die pad) 22 of the lead frame. Fixed. In addition, a sealing material such as a lead portion of a lead frame and a resin is omitted for convenience of explanation. When the analog section 24 (analog module) and the digital section 25 (digital module) are mixed on the semiconductor chip 21, the entire surface of the chip support section 22 on which the semiconductor chip 21 is mounted is very Due to the low resistance of the conductor, the noise generated by the digital module 25 is easily transmitted to the analog module 24 via the path through the chip support 22, and the performance of the analog module 24 may be degraded and malfunction may occur. Probable cause ^ The study has been made clear by the inventors of the present application.
図 2に示す寸法のシリコンからなる半導体チップ 2 1を考えた場合、 シリコン 集積回路基板 3の各抵抗 Rを試算すると、 シリコン集積回路基板 3の縦方向の抵 抗は、 デジタルモジュール 2 5の下部で約 5 Ω、 アナログモジュール 2 4の下部 で約 1 0 Ωであり、 一方、 シリコン集積回路基板 3の横方向の抵抗は、 デジタル モジュール部 2 5で約 1 0 0 Ω、 アナログモジュール 2 4 とデジタルモジュール 2 5の間で約 5 0 Ωである。 Considering the semiconductor chip 21 made of silicon having the dimensions shown in FIG. 2, when the resistance R of the silicon integrated circuit board 3 is estimated, the resistance of the silicon integrated circuit board 3 in the vertical direction is the lower part of the digital module 25. The resistance of the silicon integrated circuit board 3 in the horizontal direction is about 100 Ω in the digital module section 25 and about 10 Ω in the lower part of the analog module 24. It is about 50 Ω between digital modules 25.
以上の試算値をもとに、 デジタルモジュール 2 5で発生した雑音がシリコン集 積回路基板 3を介してアナログモジュール 2 4へ伝搬する経路を考慮すると、 シ リコン基板内部を横方向に伝わる経路 2 6の抵抗は約 1 6 5 Ωである。 これに対 して、 デジタルモジュール 2 5で発生した雑音が縦方向へ伝わり、 一旦チップ支 持部 2 2に到達してから、 このチップ支持部 2 2を伝搬し、 アナログモジュール 2 4の下部より再びシリコン集積回路基板 3中に進入して縦方向にアナログモジ ユールに伝わる経路 2 7の全抵抗は、 金属製のチップ支持部 1 2の抵抗がシリコ ン集積回路基板 3の抵抗に比べて十分に小さいので、 約 1 5 Ωとなる。 これは経 路 2 6の抵抗の 1 Ζ 1 0以下である。 Based on the above estimated values, considering the path in which the noise generated in the digital module 25 propagates through the silicon integrated circuit board 3 to the analog module 24, the path 2 The resistance of 6 is about 16.5 Ω. On the other hand, the noise generated by the digital module 25 is transmitted in the vertical direction, reaches the chip support 22 once, propagates through the chip support 22, and is transmitted from the lower part of the analog module 24. The total resistance of the path 27, which reenters the silicon integrated circuit board 3 and is transmitted to the analog module in the vertical direction, is sufficient for the resistance of the metal chip support portion 12 to be greater than the resistance of the silicon integrated circuit board 3. , It is about 15 Ω. This is less than 1 抵抗 10 of the resistance of the path 26.
従って、 図 2の半導体チップにおいては、 デジタルモジュール 2 5で発生した 雑音は、 シリコン集積回路基板 3の内部を伝わるよりも、 金属製のチップ支持部 2 2を伝わるものが大部分を占める。 このように、 金属製のチップ支持部 2 2力 半導体チップの下部全面にある封止体 (L S Iパッケージ) 構造では、 デジタル モジュ一ルで発生した雑音がァナログモジユールに影響を及ぼすことを十分に防 止することはできない。 Therefore, in the semiconductor chip of FIG. 2, most of the noise generated in the digital module 25 is transmitted through the metal chip supporting portion 22 rather than transmitted inside the silicon integrated circuit substrate 3. In this way, the metal chip supporting part 22 The force (LSI package) structure on the entire lower surface of the semiconductor chip is It is not possible to sufficiently prevent the noise generated by the module from affecting the analog module.
さらに、 金属製のチップ支持部 2 2カ?封止体 (L S Iパッケージ) 内において、 電気的にフローティング状態で封止されている場合には、 デジタルモジュールか らチップ支持部 2 2に伝わった雑音は、 シリコン基板の表面に戻っていく確率が 高く、 アナ口グ /デジタル混在形半導体集積回路の電気的信頼性がさらに低下す るという問題がある。 Further, in a metal chip support 2 2 months? Encapsulant (LSI package), electrically when sealed in a floating state, the digital module or al noise transmitted to the chip supporting portion 2 2 However, there is a problem that the probability of returning to the surface of the silicon substrate is high, and the electrical reliability of the mixed analog / digital type semiconductor integrated circuit is further reduced.
また、 図 1のピタキシャル層を用いた半導体チップにおいては、 図 2のシリコ ン集積回路基板 3に相当するェピタキシャル層 1 2の厚さが薄いため、 横方向に 対して縦方向の抵抗は更に小さくなる。 また、 ェピタキシャル層 1 2の底面は高 不純物濃度基板すなわち低抵抗の不純物半導体 1 1に接しており、 これが図 2の シリコン集積回路基板 3の金属製のチップ支持部 2 2の役割を果している。 この 構造の半導体チップでは、 デジタルモジュ一ルで発生した雑音は更にアナログモ ジュールに伝搬されやすく、 アナログ/デジタル混在形半導体集積回路装置の信 頼性が低下するという問題がある。 Further, in the semiconductor chip using the epitaxial layer shown in FIG. 1, since the thickness of the epitaxial layer 12 corresponding to the silicon integrated circuit substrate 3 shown in FIG. 2 is thin, the resistance in the vertical direction with respect to the horizontal direction is further reduced. Become smaller. The bottom surface of the epitaxial layer 12 is in contact with the high impurity concentration substrate, that is, the low-resistance impurity semiconductor 11, which serves as a metal chip support portion 22 of the silicon integrated circuit substrate 3 in FIG. . In a semiconductor chip having this structure, the noise generated by the digital module is more likely to be propagated to the analog module, and the reliability of the mixed analog / digital semiconductor integrated circuit device is reduced.
S O I構造基板は絶縁膜分離のために、 低周波信号の結合防止には有効である c しかし、 この S O I構造基板は、 デジタルモジュールの発生する比較的高周波の 雑音に衬しては薄い絶縁膜の容量結合により雑音を十分に遮断できないという問 題がある。 例えば、 半導体ゥヱーハプロセスで用いられるシリコン酸化膜の厚さ を 1 rnとして、 絶縁膜のィンピーダンス Z ( = 1 / 2 7Γ f C ) を試算すると、 雑音の周波数が 1 0 0 M H zの場合、 絶縁膜のィンピ一ダンスは 1 0 Ω以下とな り、 高周波的には十分な絶縁ができない。 また、 S 0 I構造基板は絶縁膜形成の ために特殊なプロセスを必要とする等、 経済的に不利である。 The SOI structure substrate for insulation membrane separation, is effective in decoupling of the low-frequency signal c, however, the SOI structure substrate is of relatively high frequency thin insulating film with衬noise generated by the digital module There is a problem that noise cannot be cut off sufficiently due to capacitive coupling. For example, assuming that the thickness of the silicon oxide film used in the semiconductor wafer process is 1 rn, and the impedance Z (= 1 / 27Γf C) of the insulating film is estimated, when the noise frequency is 100 MHz, The impedance of the film is less than 10 Ω, and sufficient insulation cannot be obtained at high frequencies. In addition, the SOI structure substrate is economically disadvantageous, such as requiring a special process for forming an insulating film.
さらに、 S O I構造基板は、 その構造上、 基板の裏面側から、 接地電位 (G N D ) を供給することができないので、 雑音の吸収効率の点で不利であり、 また精 度的に厳しいアナログモジュールの基板電位の安定化においても不利である。 こ のため、 S O I構造基板を用いた場合にはアナログ/デジタル混在形半導体集積 回路装置の電気的信頼性が低下するという問題がある。 Furthermore, since the SOI structure substrate cannot supply ground potential (GND) from the back side of the substrate due to its structure, it is disadvantageous in terms of noise absorption efficiency, and it is also difficult to use analog modules that are strictly accurate. It is also disadvantageous in stabilizing the substrate potential. For this reason, when an SOI structure substrate is used, there is a problem that the electrical reliability of a mixed analog / digital type semiconductor integrated circuit device is reduced.
このように S O I構造や二重ゥヱル構造を用いれば、 デジタル回路の基板とァ ナログ回路の基板との間が分離されるため、 基板結合による雑音の影響は小さく なる。 しかし、 プロセス工程は複雑となり、 また、 分離された各回路領域の基板 には、 構造的に雑音による電圧勾配が生じやすく、 それぞれの回路領域の基板電 位を一様に保つことが難しい。 この基板電位の不均一性は、 例えば、 差動形のァ ナ口グ回路などのバランスを悪化し、 コモンモード雑咅の低減効果を制限すると いう問題を生ずる。 If the SOI structure or the double-hole structure is used in this way, the substrate between the digital circuit and the analog circuit is separated, so that the influence of noise due to the substrate coupling is reduced. However, the process steps are complicated, and a voltage gradient due to noise is apt to occur on the substrate of each separated circuit region structurally, and it is difficult to keep the substrate potential of each circuit region uniform. The non-uniformity of the substrate potential degrades the balance of, for example, a differential type analog circuit, and causes a problem of limiting the effect of reducing common mode noise.
一方、 本願発明に先立って、 半導体チップの主表面にアナログモジュールとデ ジタルモジュールとを形成して、 半導体チップの裏面のアナログモジュールとデ ジタルモジユールのそれぞれの下部に位置するアナログモジユール裏面領域とデ ジタルモジュ一ル裏面領域とに金属製のアナ口グモジュ一ル支持部とデジタルモ ジュ一ル支持部とを独立に接続し、 これらのアナログモジュ一ル支持部とデジタ ルモジュール支持部とを独立のアナログモジュール接地リ一ド端子とデジタルモ ジュール接地リード端子とを介して実装基板の接地配線 ( G N D ) に接続する 方式も、 本願発明者等によって検討された。 On the other hand, prior to the present invention, an analog module and a A digital module and a metal module support on a back surface area of the analog module and a back surface area of the digital module located below the analog module and the digital module on the back surface of the semiconductor chip, respectively. The digital module support is connected independently to the digital module support, and these analog module support and digital module support are connected via independent analog module ground leads and digital module ground leads. The method of connecting to the ground wiring (GND) of the mounting board was also studied by the present inventors.
しかし、 この方式においては、 アナログモジュール接地リード端子とデジタル モジュ一ル接地リ一ド端子とはそれぞれ無視できないリード ' インダクタンスを 有する。 However, in this method, the analog module ground lead terminal and the digital module ground lead terminal each have a non-negligible lead 'inductance.
従って、 デジタルモジュ一ルの動作による雑音電流が半導体チップのデジ夕ル モジユールからデジタルモジユール支持部とデジタルモジユール接地リ一ド端子 のリード . イングクタンスとを介して実装基板の接地配線 (G N D ) が流れるの で、 デジタルモジユールとデジタルモジユール支持部とは仮想接地電位に保たれ ずリード · インダクタンスに流れる雑音電流による雑音電圧が生じる。 また、 ァ ナ口グモジュ一ルが大振幅出力信号を発生する場合には、 デジタルモジュールの 動作による雑音電流が半導体チップのデジタルモジュールからアナログモジュ一 ル支持部とアナログモジュ一ル接地リ一ド端子のリード ' インダクタンスとを介 して実装基板の接地配線( G N D ) が流れるので、 アナログモジュールとアナ口 グモジュ一ル支持部とは仮想接地電位に保たれずリード ' インダクタンスに流れ る雑音電流による雑音電圧が生じる。 Therefore, the noise current due to the operation of the digital module is reduced from the digital module of the semiconductor chip to the ground wiring (GND) of the mounting board via the digital module support section and the lead of the digital module ground lead terminal. ) Flows, the digital module and the digital module support are not maintained at the virtual ground potential, and a noise voltage is generated due to the noise current flowing through the lead inductance. When the analog module generates a large-amplitude output signal, the noise current due to the operation of the digital module is transferred from the digital module of the semiconductor chip to the analog module supporting portion and the analog module ground lead terminal. Since the ground wiring (GND) of the mounting board flows through the lead's inductance, the analog module and the analog module support are not maintained at the virtual ground potential, and the noise due to the noise current flowing through the lead's inductance A voltage is generated.
従って、 この方式においては、 デジタルモジュールとアナログモジュールとの 問で基板を経由して雑音が一方から他方へ伝搬され、 回路の性能劣化もしくは誤 動作の問題が十分に解決されないという問題も、 本願発明者等によつて検討され た。 Therefore, in this method, the problem that noise is propagated from one side to the other via the board between the digital module and the analog module, and the problem of circuit performance degradation or malfunction is not sufficiently solved. This was reviewed by the public.
本発明は上記の如き本願発明者等にる検討結果を基にしてなされたものであり、 その目的とするところは、 回路の性能劣化もしくは誤動作の問題を解決可能な半 導体集積回路装置を提供するることにある。 SUMMARY OF THE INVENTION The present invention has been made based on the results of the study by the inventors of the present invention as described above, and an object of the present invention is to provide a semiconductor integrated circuit device capable of solving the problem of circuit performance degradation or malfunction. To do.
本願で開示される発明の代表的な概要は、 下記の通りである。 A typical outline of the invention disclosed in the present application is as follows.
本発明の代表的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a representative embodiment of the present invention includes:
主表面の第 1表面領域に第 1機能回路部 (2 ) が形成され、 該主表面の該第 1 表面領域の近傍に第 1電圧検出領域 (6 a ) と第 1電圧制御領域 (6 b ) とが形 成され、 増幅回路 (7 a ) を含む半導体基板 (3 ) と、 A first functional circuit portion (2) is formed in a first surface region of the main surface, and a first voltage detection region (6a) and a first voltage control region (6b) are formed near the first surface region of the main surface. And a semiconductor substrate (3) including an amplifier circuit (7a);
上記半導体基板 (3 ) の裏面のうち上記第 1機能回路部の下部に位置する第 1 裏面領域と接続された導電性物質からなる第 1基板支持部材 (4 b ) とを具備し てなり、 上記増幅回路 (7 a) の非反転入力端子 (+ ) に基準電圧 (GND) が印加さ れ、 A first substrate support member (4b) made of a conductive material connected to a first back surface region of the back surface of the semiconductor substrate (3) located below the first functional circuit portion; A reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
上記増幅回路 (7 a) の反転入力端子 (一) が上記半導体基板 (3) の上記主 表面の上記第 1電圧検出領域 (6 a) に接続され、 An inverting input terminal (1) of the amplifier circuit (7a) is connected to the first voltage detection region (6a) on the main surface of the semiconductor substrate (3);
上記増幅回路 (7 a) の出力端子が上記半導体基板 (3) の上記主表面の上記 第 1電圧制御領域 (6 b) に接続されたことを特徴とする (図 3参照) 。 An output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6b) on the main surface of the semiconductor substrate (3) (see FIG. 3).
かかる代表的な発明によれば、 上記第 1基板支持部材 (4 b) は半導体集積回 路装置の接地リード端子を介して実装基板の接地配線 (GND) に接続されるの ではなく、 上記増幅回路 (7 a) のフィードバック動作によってヒ記半導体基板 ( 3 )の上記主表面の上記第 1電圧検出領域( 6 a ) と上記第 1電圧制御領域( 6 b) と上記第 1基板支持部材 (4 b) は略上記基準電圧 (GND) に仮想的に設 定される。 このように、 上記第 1基板支持部材 (4 b) の略上記基準電圧 (GN D) への設定に半導体集積回路装置の接地リード端子は直接寄与せず、 上記増幅 回路 (7 a) のフィードバック動作が寄与するものである。 この時、 上記増幅回 路 (7 a) の上記非反転入力端子 (+ ) への上記基準電圧 (GND) の印加は半 導体集積回路装置の接地リード端子により行われるが、 上記増幅回路 (7 a) の 上記反転入力端子 (一) と上記非反転入力端子 (+ ) との間の浮遊容量が無視で きる場合は、 上記非反転入力端子 (+) の接地リー ド端子のリード . インダクタ ンスに流れる雑音電流による雑音電压も無視できるレベルとなる。 According to this typical invention, the first substrate support member (4b) is not connected to the ground wiring (GND) of the mounting board via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplification board. By the feedback operation of the circuit (7a), the first voltage detection area (6a), the first voltage control area (6b), and the first substrate support member (6) on the main surface of the semiconductor substrate (3) 4b) is virtually set to the above-mentioned reference voltage (GND). Thus, the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member (4b) to substantially the reference voltage (GND), and the feedback of the amplifier circuit (7a) does not contribute. The action contributes. At this time, the application of the reference voltage (GND) to the non-inverting input terminal (+) of the amplifier circuit (7a) is performed by the ground lead terminal of the semiconductor integrated circuit device. a) If the stray capacitance between the inverting input terminal (1) and the non-inverting input terminal (+) can be neglected, the lead of the ground lead terminal of the non-inverting input terminal (+). The noise power due to the noise current flowing through the device also becomes a negligible level.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記第 1電圧検出領域 (6 a) と上記第 1電圧制御領域 (6 b) とは上記半導 体基板 (3) の上記主表面の上記第 1表面領域の上記第 1機能回路部 (2) の周 囲に形成された導電性の二重リングのガードバンドにより構成され、 The first voltage detection area (6a) and the first voltage control area (6b) correspond to the first functional circuit section (2) of the first surface area of the main surface of the semiconductor substrate (3). ), Formed by a conductive double ring guard band formed around
上記増幅回路 (7 a) のフィー ドバック動作により上記第 1電圧検出領域 ( 6 a) と上記第 1基板支持部材 (4 b) とは略上記基準電圧 (GND) に設定され、 上記第 1機能回路部 (2) の雑 の低減が可能であることを特徴とする (図 3参 BB) 。 By the feedback operation of the amplifier circuit (7a), the first voltage detection area (6a) and the first substrate supporting member (4b) are set to substantially the reference voltage (GND), and the first function The feature is that it can reduce the complexity of the circuit section (2) (see Fig. 3 BB).
かかるより具体的な実施形態によれば、 上記第 1電圧検出領域 (6 a) と上記 第 1電圧制御領域 (6 b) とは上記第 1機能回路部 (2) の周囲に形成された二 重リングのガードバン ドであるので、 上記第 1機能回路部 (2) と上記半導体基 板 (3) の他の部分との間で伝搬される雑音をより完全に低減することができる。 本発明のより具体的な実施形態の半導体集積回路装置は、 According to such a more specific embodiment, the first voltage detection area (6a) and the first voltage control area (6b) are formed around the first functional circuit section (2). Since the guard band is a heavy ring guard band, the noise propagated between the first functional circuit section (2) and other portions of the semiconductor substrate (3) can be reduced more completely. A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の第 2表面領域に第 2機能回路部 ( 1) が 形成され、 . A second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
上記増幅回路 (7 a) のフィードバック動作により上記第 1電圧検出領域 ( 6 a) と上記第 1基板支持部材 (4 b) とは略上記基準電 (GND) に設定され ることを特徴とする (図 3参照) 。 By the feedback operation of the amplifier circuit (7a), the first voltage detection area (6a) and the first substrate support member (4b) are set to substantially the reference voltage (GND). (See Fig. 3).
かかるより具体的な実施形態によれば、 上記第 1機能回路部 (2) と上記第 2 機能回路部 ( 1 ) との間で伝搬される雑音を低減することができる。 According to such a more specific embodiment, noise propagated between the first functional circuit unit (2) and the second functional circuit unit (1) can be reduced.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の裏面のうち上記第 2機能回路部 (1) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 a) を更 に具備してなり、 A second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記第 2基板支持部材 (4 a) を略上記基準電圧 (GND) に設定することを 特徴とする (図 3参照) 。 The second substrate support member (4a) is set to approximately the reference voltage (GND) (see FIG. 3).
かかるより具体的な実施形態によれば、 上記第 2機能回路部 ( 1) へ伝搬され る锥音の更なる低減が可能となる。 According to such a more specific embodiment, it is possible to further reduce the noise propagated to the second functional circuit section (1).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の上記第 2表面領域の上記第 2機能回路部 The second functional circuit portion in the second surface region of the main surface of the semiconductor substrate (3)
( 1 ) の周囲に導電性の他のガードバンド (6 c) が形成され、 Another conductive guard band (6c) is formed around (1),
上記他のガードバンド (6 c) を略上記基準電圧に設定することを特徴とする The other guard band (6c) is set to approximately the reference voltage.
(図 4参照) 。 (See Figure 4).
かかるより具体的な実施形態によれば、 上記第 2機能回路部 (1) へ伝搬され る雑音の更なる低減が可能となる。 According to such a more specific embodiment, it is possible to further reduce the noise transmitted to the second functional circuit section (1).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の上記第 2表面領域の上記第 2機能回路部 の周囲 (1) に導電性の他のガードバンド (6 c, 6 d) が形成され、 Another conductive guard band (6c, 6d) is formed around (1) around the second functional circuit portion in the second surface region of the main surface of the semiconductor substrate (3),
上記半導体基板 (3) の裏面のうち上記第 2機能回路部 (1 ) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 a) を更 に具備してなり、 A second substrate support member (4a) made of a conductive material connected to a second back surface area located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記半導体基板は他の増幅回路 (7 b) を含み、 The semiconductor substrate includes another amplifier circuit (7b),
上記他のガ一ドバンドは他の二重リングのガ一ドバンドで構成された第 2電圧 検出領域 (6 c) と第 2電圧制御領域 (6 d) とであり、 The other guard bands are a second voltage detection region (6c) and a second voltage control region (6d) composed of the guard band of another double ring.
上記他の増幅回路 (7 b) の非反転入力端子 (+ ) に上記基準電圧 (GND) が印加され、 The above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
上記他の増幅回路 (7 b) の反転入力端子 (一) が上記半導体基板 (3) の上 記主表面の上記第 2電圧検出領域 (6 c) に接続され、 The inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second voltage detection area (6c) on the main surface of the semiconductor substrate (3),
上記他の増幅回路 (7 b) の出力端子が上記半導体基板 (3) の上記主表面の 上記第 2電圧制御領域 (6 d) に接続され、 The output terminal of the other amplifier circuit (7b) is connected to the second voltage control region (6d) on the main surface of the semiconductor substrate (3),
上記他の増幅回路 (7 b) のフィードバック動作により上記第 2電圧検出領域 (6 c) と上記第 2基板支持部材 (4 a) とは略上記基準電圧 (GND) に設定 されることを特徴とする (図 6参照) 。 かかるより具体的な実施形態によれば、 上記第 1機能问路部 (2) と上記第 2 機能回路部 (1) との間で伝搬される雑音の低減が可能となる。 The second voltage detection area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 6). According to such a more specific embodiment, it is possible to reduce noise propagated between the first functional circuit section (2) and the second functional circuit section (1).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記第 1機能回路部 (2) と上記第 2機能回路部 (1) との一方と他方とは、 デジタル信号を処理する回路とアナログ信号を処理する回路とであることを特徴 とする (図 3乃至図 6参照) 。 One and the other of the first functional circuit section (2) and the second functional circuit section (1) are a circuit for processing a digital signal and a circuit for processing an analog signal. 3 to 6).
本発明の他の代表的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to another exemplary embodiment of the present invention includes:
主表面の第 1表面領域に第 1機能回路部 (2, 1) が形成され、 該主表面の該 第 1表面領域の近傍に第 1電圧制御領域(6 a, 6 c)が形成され、增幅回路( 7 a, 7 b) を含む半導体基板 (3) と、 A first functional circuit portion (2, 1) is formed in a first surface region of the main surface, and a first voltage control region (6a, 6c) is formed in the vicinity of the first surface region of the main surface, A semiconductor substrate (3) including a width circuit (7a, 7b);
上記半導体基板 (3) の裏面のうち上記第 1機能回路部 (2, 1) の下部に位 置する第 1裏面領域と接続された導電性物質からなる第 1基板支持部材 (4 b, 4 a) とを具備してなり、 A first substrate support member (4b, 4b) made of a conductive material connected to a first back surface region located below the first functional circuit portion (2, 1) on the back surface of the semiconductor substrate (3). a) and
h記増幅回路 (7 a, 7 b) の非反転入力端子 (+ ) に基準電圧 (GND) が 印加され、 The reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a, 7b).
ヒ記増幅回路 (7 a, 7 b) の反転入力端子 (一) が上記第 1基板支持部材 (4 b, 4 a) に接続され、 The inverting input terminal (1) of the amplifier circuit (7a, 7b) is connected to the first substrate support member (4b, 4a),
ヒ記増幅回路 (7 a, 7 b) の出力端子が上記半導体基板 (3) のヒ記主表面 の上記第 1電圧制御領域 (6 a, 6 c) に接続されたことを特徴とする (図 7、 図 8参照) 。 The output terminal of the amplifier circuit (7a, 7b) is connected to the first voltage control region (6a, 6c) on the main surface of the semiconductor substrate (3). See Figures 7 and 8.)
かかる他の代表的な発明によれば、 上記反転入力端子 (一) と上記非反転入力 端子 (+ ) との間の浮遊容量が無視できない場合でも、 上記非反転入力端子 (+ ) の接地リ一ド端子のリード · インダクタンスに流れる雑音電流による雑音電圧も 無視できるレベルとなる。 According to this other typical invention, even when the stray capacitance between the inverting input terminal (1) and the non-inverting input terminal (+) cannot be ignored, the grounding of the non-inverting input terminal (+) can be reduced. The noise voltage due to the noise current flowing through the lead and inductance of the 1st terminal is also negligible.
すなわち、 上記第 1基板支持部材 (4 b, 4 a) は半導体集積回路装置の接地 リード端子を介して実装基板の接地配線 (GND) に接続されるのではなく、 上 記増幅回路 (7 a, 7 b) のフィードバック動作によって略上記基準電压 (GN D) に仮想的に設定される。 この際に、 雑音力 s発生されても上記第 1基板支持部 材 (4 b, 4 a) は略上記基準電圧 (GND) に仮想的に設定される如く発生雑 音と逆位相で略同一振幅の相殺信号が上記増幅回路 (7 a, 7 b) の上記出力端 子から上記第 1電圧制御領域 (6 a, 6 c) へ印加される。 That is, the first substrate support member (4b, 4a) is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplifier circuit (7a 7b) is virtually set to the above-mentioned reference power (GND) virtually. At this time, even if a noise force s is generated, the first substrate supporting members (4b, 4a) are substantially the same in phase opposite to the generated noise as virtually set to the reference voltage (GND). An amplitude cancellation signal is applied from the output terminal of the amplifier circuit (7a, 7b) to the first voltage control area (6a, 6c).
この相殺の結果、 上記第 1基板支持部材 (4 b, 4 a) の電位変動も低減され、 上記の浮遊容量が無視できない場台でも、 上記非反転入力端子 (+ ) の接地リー ド端子のリード■ インダクタンスに流れる雑音電流による雑音電圧も無視できる レベルとなる。 As a result of this cancellation, the potential fluctuation of the first substrate support member (4b, 4a) is also reduced, and even if the stray capacitance cannot be ignored, the ground lead terminal of the non-inverting input terminal (+) can be used. The noise voltage due to the noise current flowing through the lead ■ inductance is also at a negligible level.
本発明のより具体的な実施形態の半導体集積回路装置は、 上記第 1電圧制御領域 (6 c) は上記半導体基板 (3) の上記主表面の上記第 1表面領域の上記第 1機能回路部 ( 1 ) の周囲に形成された導電性リングのガー ドバンドにより構成され、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention The first voltage control region (6c) is formed by a guard band of a conductive ring formed around the first functional circuit portion (1) on the first surface region on the main surface of the semiconductor substrate (3). Composed,
上記増幅回路 (7 b) のフィードバック動作により上記第 1電圧制御領域 (6 c) と上記第 1基板支持部材 (4 a) とは略上記基準電圧 (GND) に設定され、 雑音の低減が可能であることを特徴とする (図 8参照) 。 By the feedback operation of the amplifier circuit (7b), the first voltage control area (6c) and the first substrate support member (4a) are set to substantially the reference voltage (GND), and noise can be reduced. (See Fig. 8).
かかるより具体的な実施形態によれば、 上記第 1電圧制御領域 (6 c) は上記 第 1機能回路部 ( 1 ) の周囲に形成されたリングのガ一ドバンドであるので、 上 記第 1機能回路部 (1) と上記半導体基板 (3) の他の部分との間で伝搬される 雑音をより完全に低減することができる。 According to such a more specific embodiment, the first voltage control area (6c) is a guard band of a ring formed around the first functional circuit section (1). Noise transmitted between the functional circuit section (1) and other parts of the semiconductor substrate (3) can be reduced more completely.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の第 2表面領域に第 2機能回路部 (2) が 形成され、 A second functional circuit portion (2) is formed in a second surface region of the main surface of the semiconductor substrate (3);
上記増幅回路 (7 b) のフィードバック動作により上記第 1電圧制御領域 ( 6 c) と上記第 1基板支持部材 (4 a) とは略上記基準電圧 (GND) に設定され ることを特徴とする (図 8参照) 。 The feedback operation of the amplifier circuit (7b) sets the first voltage control area (6c) and the first substrate support member (4a) to approximately the reference voltage (GND). (See Figure 8).
かかるより具体的な実施形態によれば、 上記第 1機能回路部 U ) と上記第 2 機能回路部 (2) との間で伝搬される雑音の低減が可能となる。 According to such a more specific embodiment, it is possible to reduce noise propagated between the first functional circuit unit U) and the second functional circuit unit (2).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の裏面のうち上記第 2機能回路部 (2) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 b) を更 に具備してなり、 The second substrate support member (4b) made of a conductive material connected to the second back surface region located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記第 2基板支持部材 (4 b) を略上記基準電圧 (GND) に設定することを 特徴とする (図 9参照) 。 The second substrate support member (4b) is set to approximately the reference voltage (GND) (see FIG. 9).
かかるより具体的な実施形態によれば、 上記第 1機能回路部 (1) と上記第 2 機能回路部 (2) との間で伝搬される雑音の更なる低減が可能となる。 According to such a more specific embodiment, it is possible to further reduce noise propagated between the first functional circuit unit (1) and the second functional circuit unit (2).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の上記第 2表面領域の上記第 2機能回路部 (2) の周囲に導電性の他のガードバンド (6 a) 力 ?形成され、 The main surface of the other of the guard band (6 a) force conducting around the second functional circuit portion of the second surface region (2) of the semiconductor substrate (3)? Are formed,
上記他のガードバンド (6 a) を略上記基準電圧 (GND) に設定することを 特徴とする (図 9参照) 。 The other guard band (6a) is set to approximately the above-mentioned reference voltage (GND) (see Fig. 9).
かかるより具体的な実施形態によれば、 上記第 1機能回路部 (1) と上記第 2 機能回路部 (2) との間で伝搬される雑音の更なる低減力可能となる。 According to such a more specific embodiment, it is possible to further reduce noise transmitted between the first functional circuit unit (1) and the second functional circuit unit (2).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の上記第 2表面領域の上記第 2機能回路部 (2) の周囲に導電性の他のガードバンド (6 a) が形成され、 上記半導体基板 (3) の裏面のうち上記第 2機能回路部 (2) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 b) を更 に具備してなり、 Another conductive guard band (6a) is formed around the second functional circuit portion (2) in the second surface region on the main surface of the semiconductor substrate (3), A second substrate support member (4b) made of a conductive material connected to a second back surface area located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記半導体基板 (3) は他の増幅回路 (7 a) を含み、 The semiconductor substrate (3) includes another amplifier circuit (7a),
上記他のガードバンドはリングのガードバンドで構成された第 2電圧制御領域 (6 a) であり、 The other guard band is a second voltage control region (6a) composed of a ring guard band,
上記他の増幅回路 (7 a) の非反転入力端子 (+ ) に上記基準電圧 (GND) が印加され、 The reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7a),
上記他の増幅回路 (7 a) の反転入力端子 (一) が上記半導体基板 (3) の上 記第 2基板支持部材 (4 b) に接続され、 The inverting input terminal (1) of the other amplifier circuit (7a) is connected to the second substrate support member (4b) of the semiconductor substrate (3),
ヒ記他の増幅回路 (7 a) の出力端子が上記半導体基板 (3) の上記主表面の 上記第 2電圧制御領域 (6 a) に接続され The output terminal of another amplifier circuit (7a) is connected to the second voltage control region (6a) on the main surface of the semiconductor substrate (3).
上記他の増幅回路 (7 a) のフィードバック動作により上記第 2電圧制御領域 (6 a) と上記第 2基板支持部材 (4 b) とは略上記基準電圧 (GND) に設定 することを特徴とする (図 9参照) 。 The second voltage control region (6a) and the second substrate support member (4b) are set to substantially the reference voltage (GND) by a feedback operation of the other amplifier circuit (7a). (See Figure 9).
かかるより具体的な実施形態によれば、 上記第 2機能 路部と上記第 1機能回 路部との間で伝搬される雑音の低減が可能となる。 According to such a more specific embodiment, it is possible to reduce noise propagated between the second functional circuit unit and the first functional circuit unit.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記第 1機能回路部と上記第 2機能回路部との一方と他方とは、 デジタル信号 を処理する回路とアナログ信号を処理する回路とであることを特徴とする (図 7 乃至図 9参照) 。 One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
本発明の他の観点の実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to another embodiment of the present invention includes:
主表面の第 1表面領域に第 1機能回路部 (2) が形成され、 該主表面の該第 1 表面領域の近傍に第 1電圧制御領域 (6 a) が形成され、 増幅回路 (7 a) を含 む半導体基板 (3) と、 A first functional circuit portion (2) is formed in a first surface region of the main surface, a first voltage control region (6a) is formed in the vicinity of the first surface region of the main surface, and an amplifier circuit (7a) is formed. ) Containing a semiconductor substrate (3);
上記半導体基板 (3) の裏面のうち上記第 1機能回路部 (2) の下部に位置す る第 1裏面領域と接続された導電性物質からなる第 1基板支持部材 (4 b) とを 具備してなり、 A first substrate support member (4b) made of a conductive substance connected to a first back surface region located below the first functional circuit portion (2) on the back surface of the semiconductor substrate (3); And
上記第 1電圧制御領域 (6 a) は上記半導体基板の上記主表面の上記第 1表面 領域の上記第 1機能回路部 (2) の周囲に形成された導電性のリングのガードバ ンドにより構成され、 The first voltage control region (6a) is constituted by a guard band of a conductive ring formed around the first functional circuit portion (2) in the first surface region of the main surface of the semiconductor substrate. ,
上記増幅回路 (7 a) の非反転入力端子 (+ ) に基準電 ¾ (GND) が印加さ れ、 A reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
回路動作による雑音を上記増幅回路 (7 a) が検出する如く上記増幅回路 (7 a) の反転入力端子 (―) が上記半導体基板 (3) と上記第 1基板支持部材 (4 b) との少なくともいずれか一方と接続され、 上記増幅回路 (7 a) の出力端子が上記半導体基板 (3) の上記主表面の上記 第 1電圧制御領域 (6 a) に接続されることにより、 上記増幅回路 (7 a) の上 記出力端子の出力信号は上記雑音を低減することを特徴とする(図 3、図 7参照) c かかる他の観点の発明によれば、 上記第 1電圧制御領域 (6 a) は上記第 1機 能回路部 ( 2 ) の周囲に形成された導電性のリングのガードバンドにより構成さ れているので、 上記第 1機能回路部 (2) と上記半導体基板 (3) の他の部分と の間で伝搬される雑音をより完全に低減することができる。 The inverting input terminal (-) of the amplifier circuit (7a) is connected between the semiconductor substrate (3) and the first substrate support member (4b) so that the amplifier circuit (7a) detects noise due to circuit operation. Connected to at least one of them, The output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6a) on the main surface of the semiconductor substrate (3) by connecting the output terminal of the amplifier circuit (7a). The output signal of the terminal is characterized by reducing the noise (see FIGS. 3 and 7). C According to the invention of another aspect, the first voltage control area (6a) is provided with the first function. Since it is constituted by a guard band of a conductive ring formed around the circuit section (2), the gap between the first functional circuit section (2) and the other portion of the semiconductor substrate (3) is provided. Propagated noise can be reduced more completely.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の第 2表面領域に第 2機能回路部 (1 ) が 形成され、 A second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
上記半導体基板 (3) の裏面のうち上記第 2機能回路部 ( 1) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 a) を更 に具備してなり、 The second substrate support member (4a) made of a conductive material connected to the second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記第 2基板支持部材 (4 a) を略上記基 ¾1電圧に設定することを特徴とする (図 3、 図 7参照) 。 The second substrate support member (4a) is set to approximately the first voltage (see FIGS. 3 and 7).
かかるより具体的な実施形態によれば、 上記第 1機能回路部 (2) と上記第 2 機能回路部 (1) との間で伝搬される雑音の低減が可能でとなる。 According to such a more specific embodiment, it is possible to reduce noise propagated between the first functional circuit section (2) and the second functional circuit section (1).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の第 2表面領域に第 2機能回路部 (1 ) が 形成され、 A second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
上記半導体基板 (3) の上記主表面の上記第 2表面領域の上記第 2機能回路部 ( 1 ) の周囲に導電性の他のガ一ドバンド (6 c) が形成され、 Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region on the main surface of the semiconductor substrate (3);
上記他のガードバンド (6 c) を略上記基準電圧 (G ND) に設定することを 特徴とする (図 4、 図 7参照) 。 The other guard band (6c) is set to approximately the reference voltage (G ND) (see Figs. 4 and 7).
かかるより具体的な実施形態によれば、 上記第 1機能回路部と上記第 2機能回 路部との間で伝搬される雑音の低減が可能となる。 According to such a more specific embodiment, it is possible to reduce noise propagated between the first function circuit unit and the second function circuit unit.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板 (3) の上記主表面の第 2表面領域に第 2機能回路部 (1 ) が 形成され、 A second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
上記半導体基板の上記主表面の上記第 2表面領域の上記第 2機能回路部 ( 1 ) の周囲に導電性の他のガードバンド (6 c) が形成され、 Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region of the main surface of the semiconductor substrate,
上記半導体基板 (3) の裏面のうち上記第 2機能回路部 (1) の下部に位置す る第 2裏面領域と接続された導電性物質からなる第 2基板支持部材 (4 a) を更 に具備してなり、 A second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
上記半導体基板 (3) は他の増幅回路 (7 b) を含み、 The semiconductor substrate (3) includes another amplifier circuit (7b),
上記他のガードバンド (6 c) はリングのガードバンドで構成された第 2電圧 制御領域であり、 The other guard band (6c) is the second voltage composed of the ring guard band. Control area,
上記他の増幅回路 (7 b) の非反転入力端子 (+ ) に上記基準電圧 (GND) が印加され、 The above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
上記他の増幅回路 (7 b) の反転入力端子 (一) が上記半導体基板 (3) の上 記第 2基板支持部材に接続され、 The inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second substrate support member of the semiconductor substrate (3),
上記他の増幅回路 (7 b) の出力端子が上記半導体基板の上記主表面の上記第 2電圧制御領域に接続され An output terminal of the other amplifier circuit (7b) is connected to the second voltage control region on the main surface of the semiconductor substrate.
上記他の増幅回路 (7 b) のフィードバック動作により上記第 2電圧制御領域 (6 c) と上記第 2基板支持部材 (4 a) とは略上記基準電圧 (GND) に設定 されることを特徴とする (図 9参照) 。 The second voltage control area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 9).
かかるより具体的な実施形態によれば、 上記第 1機能回路部と上記第 2機能回 路部との間で伝搬される雑音の低減が可能となる。 According to such a more specific embodiment, it is possible to reduce noise propagated between the first function circuit unit and the second function circuit unit.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記第 1機能回路部と上記第 2機能回路部との一方と他方とは、 デジタル信号 を処理する回路とアナログ信号を処理する回路とであることを特徴とする (図 7 乃至図 9参照) 。 One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記基板支持部材をパッケ一ジの金属製リードフレームで構成したことを特徴 とする。 The substrate support member is constituted by a packaged metal lead frame.
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記基板支持部材を上記半導体基板 ( 1 0) の底面に形成した不純物半導体層 An impurity semiconductor layer in which the substrate support member is formed on the bottom surface of the semiconductor substrate (10)
(8 a, 8 b) で形成したことを特徴とする (図 1 1参照) 。 (8a, 8b) (see Fig. 11).
本発明のより具体的な実施形態の半導体集積回路装置は、 A semiconductor integrated circuit device according to a more specific embodiment of the present invention
上記半導体基板をシリコン基板 ( 1 3) 上に形成された低不純物濃度半導体層 The above semiconductor substrate is a low impurity concentration semiconductor layer formed on a silicon substrate (13).
( 1 4) で形成し、 上記基板支持部材を該低不純物濃度半導体層 (1 4) の底面 と上記シリコン基板 (1 3) との間に埋め込まれた高不純物濃度半導体層 (9 a, 9 b) で形成したことを特徴とする半 (図 1 2参照) 。 And a high impurity concentration semiconductor layer (9a, 9) embedded between the bottom surface of the low impurity concentration semiconductor layer (14) and the silicon substrate (13). b) The half formed by (2) (see Fig. 12).
本発明の構成は簡便なプロセスによって達成できるので、 アナログ/デジタル 混在形半導体集積回路装置を含む半導体装置の電気的信頼性を向上するとともに、 低コスト化を図ることが可能である。 Since the configuration of the present invention can be achieved by a simple process, it is possible to improve the electrical reliability of a semiconductor device including a mixed analog / digital semiconductor integrated circuit device and to reduce the cost.
本発明のその他の目的と新規な特徴は、 以下の実施例から明かとなろう。 図面の簡単な説明 Other objects and novel features of the present invention will become apparent from the following examples. BRIEF DESCRIPTION OF THE FIGURES
図 1はアナ口グ /デジタル混在形半導体集積回路装置における従来の集積回路 構造を説明する図である。 FIG. 1 is a diagram for explaining a conventional integrated circuit structure in a mixed analog / digital type semiconductor integrated circuit device.
図 2は本発明者が本発明をなす過程において検討したアナ口グノデジタル混在 形半導体集積回路を含む従来の半導体集積回路装置のモデル図である。 Fig. 2 shows a mixture of ana and gno digitals studied by the inventor in the process of making the present invention. FIG. 1 is a model diagram of a conventional semiconductor integrated circuit device including a semiconductor integrated circuit.
図 3は本発明の第 1の実施例であるアナ口グ Zデジタル混在形半導体集積回路 装置を説明する図である。 FIG. 3 is a diagram illustrating an analog / digital Z-mixed semiconductor integrated circuit device according to a first embodiment of the present invention.
図 4は本発明の第 1の実施例である他のアナ口グ Zデジタル混在形半導体集積 回路装置を説明する図を説明する図である。 FIG. 4 is a diagram for explaining a diagram for explaining another analog / digital Z-mixed semiconductor integrated circuit device according to the first embodiment of the present invention.
図 5は本発明の第 2の実施例であるァナ口グ Zデジタル混在形半導体集積回路 装置を説明する図である。 FIG. 5 is a diagram for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a second embodiment of the present invention.
図 6は本発明の第 3の実施例であるァナ口グ Zデジタル混在形半導体集積回路 装置を説明する図である。 FIG. 6 is a view for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a third embodiment of the present invention.
図 7は本発明の第 4の実施例であるアナログ/デジタル混在形半導体集積回路 装置を説明する図である。 FIG. 7 is a diagram illustrating a mixed analog / digital semiconductor integrated circuit device according to a fourth embodiment of the present invention.
図 8は本発明の第 5の実施例であるアナログ Zデジタル混在形半導体集積回路 装置を説明する図である。 FIG. 8 is a diagram illustrating an analog-Z digital mixed type semiconductor integrated circuit device according to a fifth embodiment of the present invention.
図 9は本発明の第 6の実施例であるアナ口グ /デジタル混在形半導体集積回路 装置を説明する図である。 FIG. 9 is a diagram illustrating a mixed analog / digital type semiconductor integrated circuit device according to a sixth embodiment of the present invention.
図 1 0は本発明の第 7の実施例であるアナログノデジタル混在形半導体集積回 路装置を説明する図である。 FIG. 10 is a diagram illustrating an analog / digital mixed semiconductor integrated circuit device according to a seventh embodiment of the present invention.
図 1 】は本発明の第 8の実施例であるアナ口グ Zデジタル混在形半導体集積回 路装置の基板構造を説明する図である。 FIG. 1 is a view for explaining a substrate structure of an analog / digital Z-type mixed semiconductor integrated circuit device according to an eighth embodiment of the present invention.
図 1 2は本発明の第 9の実施例であるアナ口グ デジタル混在形半導体集積回 路装置の他の基板構造を説明する図である。 - 発明を実施するための最良の形態 FIG. 12 is a view for explaining another substrate structure of an analog / digital mixed semiconductor integrated circuit device according to a ninth embodiment of the present invention. -Best mode for carrying out the invention
以下、 本発明の実施例を、 図面に沿って具体的に説明する。 Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
本発明の第 1の実施例である半導体集積回路装置を図 3、 図 4に示す。 FIGS. 3 and 4 show a semiconductor integrated circuit device according to a first embodiment of the present invention.
本実施例の集積回路基板 3には、 アナログ部 1とデジタル部 2とが形成される。 アナログ部 1には、 アンプ、 Aノ D変換器など微弱なアナ口グ信号を扱う回路が 構成され、 デジタル部 2には、 ロジック、 メモリなどのデジタル回路が構成され る。 集積回路基板 3には、 低濃度の p形あるいは n形シリコン基板力 f用いられる。 集積回路基板 3の底面には、 アナログ部 1、 デジタル部 2領域の下方に対応した 位置に、 それ自体は電気的に互いに分離された独立の導電体部 4 a、 4 bがそれ ぞれ接続される。 半導体集積回路はこれらの導電体部 4 a、 4 bを介して、 絶縁 パッケージに固定され、 実装される。 導電体部 4 a、 4 bは、 例えば、 銀ペース トなどの導電性の接着剤を利用して、 基板 3に接続することができる。 デジタル 部 2の回りには、 高濃度の p形あるいは n形拡散層のリング状のガ一ドバンド 6 a、 6 bが配置、 形成される。 いま、 ガードバンド 6 a、 6 bは集積回路基板 3 W An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of the present embodiment. The analog section 1 is configured with a circuit that handles weak analog signals such as an amplifier and an A / D converter, and the digital section 2 is configured with digital circuits such as logic and memory. For the integrated circuit substrate 3, a low-concentration p-type or n-type silicon substrate force f is used. On the bottom surface of the integrated circuit board 3, independent conductor parts 4a and 4b, which are electrically separated from each other, are connected to positions corresponding to the lower part of the analog part 1 and the digital part 2 area, respectively. Is done. The semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b. The conductor portions 4a and 4b can be connected to the substrate 3 using a conductive adhesive such as silver paste, for example. Around the digital section 2, ring-shaped guard bands 6a and 6b of a high concentration p-type or n-type diffusion layer are arranged and formed. Now, guard bands 6a and 6b are integrated circuit boards 3 W
14 14
と同一の p形、 あるいは n形不純物半導体とすると、 これらは抵抗体 5 a、 5 b からなる集積回路基板 3の電極としての役割を果たす。 If they are the same p-type or n-type impurity semiconductors, they serve as electrodes of the integrated circuit substrate 3 composed of the resistors 5a and 5b.
本実施例では特に、 デジタル部 2で発生する基板雑音を相殺する 的で、 ガー ドバンド 6 a、 6 bには雑音相殺信号発生回路 7 3カ;'接続される。 雑音相殺信号 発生回路 7 aは、 オペアンプなどの回路で構成され、 反転入力端子 (一) をガ— ドバンド 6 aに、 非反転入力端子 (+ ) を接地端子に接続し、 また出力端子をガ 一ドバンド 6 bに接続する。 尚、 この雑音相殺信号発生回路 7 aは集積回路基板 3内部に形成され、 雑音に不感応とするためには、 アナログ部 1の内部に形成す ることが望ましい。 In the present embodiment, in particular, the board noise generated in the digital section 2 is canceled, and the noise canceling signal generating circuit 73 is connected to the guard bands 6a and 6b. The noise canceling signal generation circuit 7a is composed of a circuit such as an operational amplifier. The inverting input terminal (1) is connected to the guard band 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the ground. Connect to band 6b. The noise canceling signal generating circuit 7a is formed inside the integrated circuit board 3, and is preferably formed inside the analog section 1 in order to make it insensitive to noise.
その結果、 雑音相殺信号発生回路 7 aはデジタル部で発生する本来の雑音を打 ち消すための相殺信号を発生することができる。 フィードバック動作により、 反 転人力端子 (一) に接続されたガ一ドバンド 6 aの電位が仮想接地となるように、 出力端子が信号が発生する。 縦方向の抵抗 5 aで代表される集積回路基板 3にお いては、 ガードバンド 6 a力5'理想的に仮想接地されることは、 導電体部 4 b力抵 抗 5 aを介して接地電位になることを意味する。 従って、 デジタル部 2で発生す る雑音電圧源を総合的に打ち消す雑音相殺信号が雑音相殺信号発生回路 7 aによ り発生されるので、 導電体部 4ヒカ雑音のない接地電位に保たれることになる。 このように、 導電体部 4 bが雑音のない安定な接地電位に保持されると、 デジタ ル部 2で発生する集積回路基板 3の雑音はこの基板領域で相殺されるため、 ァナ ログ部 1へ影響を及ぼすことがなくなる。 すなわち、 横方向の結合抵抗 5 b力 5'存 在しても、 これによつて伝搬される雑音は相殺により、 低減されることができる。 上述の本実施例によれば、 第 1基板支持部材 4 bは半導体集積回路装置の接地 リード端子を介して実装基板の接地配線 G N Dに接続されるのではなく、 増幅回 路 7 aのフィ一ドバック動作によつて半導体基板 3の主表面の第 1電圧検出領域 6 aと第 1電圧制御領域 6 bと第 1基板支持部材 4 bは略基準電圧 G N Dに仮想 的に設定される。 このように、 第 1基板支持部材 4 bの略基準電圧 G N Dへの設 定に半導体集積回路装置の接地リード端子は直接寄与せず、 増幅回路 7 aのフィ ードバック動作が寄与するものである。 この時、 増幅回路 7 aの非反転入力端子 +への基準電圧 G N Dの印加は半導体集積回路装置の接地リード端子により行わ れるカ 増幅回路 7 aの反転入力端子一と非反転入力端子十との間の浮遊容量が 無視できる場合は、 非反転入力端子十の接地リ一ド端子のリ—ド . インダクタン スに流れる雑音電流による雑音電圧も無視できるレベルとなる。 As a result, the noise canceling signal generating circuit 7a can generate a canceling signal for canceling the original noise generated in the digital section. By the feedback operation, a signal is generated at the output terminal so that the potential of the guard band 6a connected to the inverting human input terminal (1) becomes a virtual ground. In the integrated circuit board 3 represented by the longitudinal resistance 5a, the guard band 6a force 5 'is ideally virtual grounded because the conductor 4b is grounded via the force resistance 5a. It means that it becomes a potential. Therefore, since the noise canceling signal that comprehensively cancels the noise voltage source generated in the digital section 2 is generated by the noise canceling signal generation circuit 7a, the conductor section 4 is maintained at the ground potential free of flicker noise. Will be. As described above, when the conductor portion 4b is maintained at a stable ground potential without noise, the noise of the integrated circuit board 3 generated in the digital section 2 is canceled out in this board area, and thus the analog section is formed. No effect on 1 That is, even if the lateral coupling resistance 5 b force 5 ′ exists, noise propagated by this can be reduced by canceling. According to the present embodiment, the first substrate support member 4b is not connected to the ground wiring GND of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the ground of the amplification circuit 7a. The first voltage detection region 6a, the first voltage control region 6b, and the first substrate support member 4b on the main surface of the semiconductor substrate 3 are virtually set to the reference voltage GND by the feedback operation. Thus, the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member 4b to the substantially reference voltage GND, but the feedback operation of the amplifier circuit 7a contributes. At this time, the reference voltage GND is applied to the non-inverting input terminal + of the amplifier circuit 7a by the ground lead terminal of the semiconductor integrated circuit device. If the stray capacitance between them can be neglected, the noise voltage due to the noise current flowing through the lead and inductance of the ground lead terminal of the non-inverting input terminal will also be at a negligible level.
本発明は上記実施例に限定されるものではなく、 その基本的技術思想の範囲内 で種々の変形が可能であることは言うまでもない。 以下、 この変形実施例および その他の実施例を説明する力 特に上記実施例と同一の事項は説明を省略し、 相 違点のみを中心に説明する。 まず、 アナログ部 1の基板電位は、 図 3のようにアナログ部 1の集積回路基板 3の底面に接続された導電体部 4 aを直接接地しても良いし、 図 4の変形実施例 のようにアナログ部 1のガードバンド 6 cを直接接地することによって、 アナ口 グ部 1の基板電位供給し、 安定化な定電位に保つことができる。 The present invention is not limited to the above embodiment, and it goes without saying that various modifications are possible within the scope of the basic technical concept. Hereinafter, the power of explaining the modified embodiment and the other embodiments will be omitted, and the description of the same items as those of the above embodiment will be omitted, and only the differences will be mainly described. First, the substrate potential of the analog section 1 may be obtained by directly grounding the conductor section 4a connected to the bottom surface of the integrated circuit board 3 of the analog section 1 as shown in FIG. As described above, by directly grounding the guard band 6c of the analog section 1, the substrate potential of the analog section 1 can be supplied, and a stable constant potential can be maintained.
図 3、 図 4に示した本実施例により、 デジタル回路の発生する雑音は、 雑音相 殺信号発生回路 7 aと導電体部 4 bにより、 集積回路基板 3のデジタル部 2の領 域内で相殺、 消去されるため、 アナログ部 1のアナログ回路へ及ぼすデジタル雑 音を抑制することができる。 また、 アナログ部 1の集積回路基板 3の底面には、 デジタル部とは独立の導電体部 4 aによつて接地電位が供給され、 基板電位を安 定にかつ一様に保つことができる。 このため、 アナログ回路でしばいま、用いられ る高精度の差動回路のバランス悪化など、 雑音による特性劣化を防ぎ、 安定で信 頼性の高いアナログ/デジタル混在集積回路装置を提供することができる。 According to the present embodiment shown in FIGS. 3 and 4, noise generated by the digital circuit is canceled in the area of the digital section 2 of the integrated circuit board 3 by the noise canceling signal generation circuit 7a and the conductor section 4b. Since the data is erased, digital noise applied to the analog circuit of the analog unit 1 can be suppressed. Further, the ground potential is supplied to the bottom surface of the integrated circuit board 3 of the analog section 1 by the conductor section 4a independent of the digital section, so that the board potential can be kept stable and uniform. For this reason, analog circuits are often used to prevent degradation of characteristics due to noise, such as deterioration of the balance of the high-precision differential circuits used, and to provide a stable and highly reliable analog / digital mixed integrated circuit device. it can.
次に、 本発明の第 2の実施例を図 5により説明する。 Next, a second embodiment of the present invention will be described with reference to FIG.
集積回路基板 3には、 アナログ部 1とデジタル部 2とが形成される。 アナログ 部 1の回りには、 高不純物濃度の拡散層からなり集積回路基板 3の電極の役割を 果たすリング状のガードバンド 6 c、 6 dが配置され、 集積回路基板 3の底面に は、 アナログ部 1とデジタル部 2とに対応した位置に、 それぞれ独立の導電体部 4 aと導電体部 4 bが接続される。 半導体集積回路はこれらの導電体部 4 a、 4 bを介して、 絶縁パッケージに固定され、 実装される。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3. Around the analog section 1, ring-shaped guard bands 6c and 6d made of a diffusion layer having a high impurity concentration and serving as electrodes of the integrated circuit board 3 are arranged. Independent conductor sections 4a and 4b are connected to the positions corresponding to section 1 and digital section 2, respectively. The semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
ガードバンド 6 c、 6 dには雑音相殺信号発生回路 7ヒカ'接続される。 雑音相 殺信号発生回路 7 bは、 オペアンプなどの回路で構成され、 反転入力端子 (一) をガードバンド 6 cに、 非反転入力端子 (+ ) を接地端子に接続し、 また出力端 子をガ一ドバンド 6 dに接続する。 The guard bands 6c and 6d are connected to a noise canceling signal generation circuit 7 '. The noise canceling signal generation circuit 7b is composed of a circuit such as an operational amplifier. The inverting input terminal (1) is connected to the guard band 6c, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard band 6d.
いま、 アナログ部 1の下方の導電体部 4 aが、 デジタル部 2との基板抵抗結合 によって、 デジタル基板雑音を受けたとする。 雑音相殺信号発生回路 7 bはフィ ―ドノくック動作により、 ガードバンド 6 cが常に仮想接地になるようにガードバ ンド 6 dに出力信号を発生する。 ガー ドバン ド 6 cが理想的に仮想接地された場 合、 導電体部 4 aも接地電位に固定され、 雑音相殺信号発生回路 7 bはデジタル 部から到達した雑音を打ち消すための相殺信号を発生し、 ガ一ドバンド 6 dに印 加する。 これにより、 アナログ部 1の基板を雑音のない安定な電位に保つことが できる。 Now, it is assumed that the conductor portion 4a below the analog portion 1 has received digital substrate noise due to substrate resistance coupling with the digital portion 2. The noise canceling signal generation circuit 7b generates an output signal on the guard band 6d by the feed knock operation so that the guard band 6c is always at the virtual ground. When the guard band 6c is ideally grounded, the conductor 4a is also fixed to the ground potential, and the noise canceling signal generating circuit 7b generates a canceling signal to cancel the noise arriving from the digital section. And apply to guard band 6d. Thereby, the substrate of the analog section 1 can be maintained at a stable potential without noise.
尚、 デジタル部 2の基板電位は基板底面に接続された導電体部 4 b、 あるいは 基板表面に形成されたガ一ドバンド 6 aを安定な接地電位に接続し、 アナログ部 1とは独立にバイアス電源を供給し、 基板に発生する雑音を抑えることができる。 次に、 本発明の第 3の実施例を図 6により説明する。 Note that the substrate potential of the digital section 2 is connected to the conductor section 4 b connected to the bottom of the board or the guard band 6 a formed on the board surface to a stable ground potential, and biased independently of the analog section 1. Power can be supplied to suppress noise generated on the board. Next, a third embodiment of the present invention will be described with reference to FIG.
図 6の集積回路基板 3には、 アナログ部 1とデジタル部 2とが形成される。 了 ナ口グ部 1 とデジタル部 2の回りには、 それぞれ、 リング状のガードバンド 6 c、 6 dとリ ング状のガードバンド 6 a、 6 bが配置され、 集積回路基板 3の底面に は、 アナログ部 1 とデジタル部 2とに対応した位置に、 それぞれ独立の導電体部 4 aと導電体部 4 bが接続される。 半導体集積回路はこれらの導電体部 4 a、 4 bを介して、 絶縁パッケージに固定され、 実装される。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG. End Ring guard bands 6c and 6d and ring guard bands 6a and 6b are arranged around the ring section 1 and the digital section 2, respectively. The independent conductor portions 4a and 4b are connected to the positions corresponding to the analog portion 1 and the digital portion 2, respectively. The semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
アナログ部 1のガードバン ド 6 c、 6 dには雑音相殺信号発生回路 7 b力;'接続 され、 デジタル部 2のガードバンド 6 a、 6 bには雑音相殺信号発生回路 7 aが 接続される。 雑音相殺信号発生回路はオペアンプなどの回路で構成され、 反転入 力端子 (一) をそれぞれガードバン ド 6 c、 6 aに、 非反転入力端子 (+ ) を接 地端子に接続し、 出力端子をそれぞれガードバンド 6 d、 6 bに接続する。 雑 音相殺信号発生回路 7 bはフィードバック動作により、 アナ口グ部 1のガ—ドバ ン ド 6 c、 すなわち導電体部 4 aが常に仮想接地になるように最適な雑音相殺信 号を発生して、 ガードバン ド 6 dに印加する。 また、 デジタル部 2の雑音相殺信 号発生回路 7 aはフィードバック動作によって、 最適なデジタル雑音相殺信号を 発生して、 ガードバンド 6 bに印加する。 これによつて、 ガードバンド 6 a、 す なわち導電体部 4 bが仮想接地に保持され、 デジタル部 2で発生するの本来の基 板雑音を消去することができる。 The noise canceling signal generation circuit 7b is connected to the guard bands 6c and 6d of the analog section 1, and the noise canceling signal generation circuit 7a is connected to the guard bands 6a and 6b of the digital section 2. . The noise cancellation signal generation circuit is composed of circuits such as an operational amplifier. The inverting input terminal (1) is connected to guard bands 6c and 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard bands 6 d and 6 b respectively. The noise canceling signal generating circuit 7b generates an optimal noise canceling signal by feedback operation so that the guard band 6c of the analog opening section 1, that is, the conductor section 4a is always at virtual ground. And apply it to guard band 6d. The noise canceling signal generating circuit 7a of the digital section 2 generates an optimal digital noise canceling signal by a feedback operation and applies the signal to the guard band 6b. As a result, the guard band 6a, that is, the conductor portion 4b is held at the virtual ground, and the original substrate noise generated in the digital portion 2 can be eliminated.
このように、 デジタル部 2の基板においては発生するデジタル雑音が低減され、 アナログ部 1の基板においてはデジタル部 2から到来する基板結合雑音を抑える ことができる。 これらの基板雑音の低減は、 アナログ部 1 とデジタル部 2とで独 立に行われ、 より大きな雑音低減効果が得られる。 Thus, digital noise generated on the board of the digital section 2 is reduced, and board coupling noise coming from the digital section 2 can be suppressed on the board of the analog section 1. The reduction of these board noises is performed independently by the analog section 1 and the digital section 2, so that a greater noise reduction effect can be obtained.
次に、 本発明の第 4の実施例を図 7により説明する。 Next, a fourth embodiment of the present invention will be described with reference to FIG.
図 7の集積回路基板 3には、 アナログ部 1 とデジタル部 2とが形成される。 集 積回路基板 3の底面には、 アナログ部 1 とデジタル部 2とに対応した位置に、 そ れぞれ独立の導電体部 4 aと導電体部 4 b力'接続される。 半導体集積回路はこれ らの導電体部 4 a、 4 bを介して、 絶縁パッケージに固定され、 実装される。 デジタル部 2の回りにはリング状のガードバンド 6 aが配置され、 またアナ口 グ部 1の回りにはリング状のガードバンド 6 cが配置されている。 雑音相殺信号 発生回路 7 aはオペアンプなどの回路で構成され、 反転入力端子 (一) は、 直接 デジタル部 2の導電体部 4 bに接続されている。 非反転入力端子 (+ ) は接地端 子に、 出力端子はデジタル部のガ一ドバンド 6 aに接続される。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG. On the bottom surface of the integrated circuit board 3, independent conductor portions 4a and conductor portions 4b are respectively connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively. The semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b. A ring-shaped guard band 6a is arranged around the digital section 2, and a ring-shaped guard band 6c is arranged around the analog section 1. The noise canceling signal generating circuit 7a is composed of a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor 4b of the digital section 2. The non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6a of the digital section.
雑音相殺信号発生回路 7 aは、 フィードバック動作により、 常に最適な雑音相 殺信号を発生させてこれをガードバンド 6 aに印加し、 導電体部 4 bすなわちデ ジタル部 2の基板底面が仮想接地電位を保つように働く。 これは、 導電体部 4 b は仮想接地されるため、 外部リード配線の寄生素子等の影響を受けにくレ、。 直接 的に接地される場合に比べて、 定常的な接地電流が流れないからである。 一方、 アナログ部 1の基板電位は、 アナログ部 1の回りに配置したガードバン ド 6 cを接地したり、 アナログ部 1の集積回路基板 3の底面の導電体部 4 aを接 地することによ り、 一定電圧を供給する。 デジタル部 1の導電体部 4 bに雑音が 残っていても、 導電体部 4 aを独立に制御することにより、 アナログ部 1への基 板雑音の影響を低減することができる。 The noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6a, and the conductor 4b, that is, the bottom surface of the substrate of the digital section 2 is virtually grounded. It works to keep the potential. This is because the conductor portion 4b is virtually grounded, so that the conductor portion 4b is not easily affected by parasitic elements of the external lead wiring. This is because a steady ground current does not flow compared to the case where the ground is directly grounded. On the other hand, the substrate potential of the analog section 1 is set by grounding the guard band 6c disposed around the analog section 1 or by grounding the conductor section 4a on the bottom surface of the integrated circuit board 3 of the analog section 1. Supply a constant voltage. Even if noise remains in the conductor section 4b of the digital section 1, the influence of the board noise on the analog section 1 can be reduced by independently controlling the conductor section 4a.
かかる図 7の本発明の第 4の実施例によれば、 雑音相殺信号発生回路 7 aの反 転入力端子 (一) と非反転入力端子 (+ ) との間の浮遊容量が無視できない場合 でも、 以下のように非反転入力端子 (+ ) の接地リード端子のリード . インダク 夕ンスに流れる雑音電流による雑音電圧も無視できるレベルとなる。 According to the fourth embodiment of the present invention shown in FIG. 7, even if the stray capacitance between the inverting input terminal (1) and the non-inverting input terminal (+) of the noise canceling signal generation circuit 7a cannot be ignored. The noise voltage due to the noise current flowing through the lead of the ground lead terminal of the non-inverting input terminal (+) is also negligible as shown below.
すなわち、 第 1基板支持部材 4 bは半導体集積回路装置の接地リード端子を介 して実装基板の接地配線 (G N D ) に接続されるのではなく、 増幅回路 7 aのフ イードバック動作によって略基準電圧 (G N D ) に仮想的に設定される。 この際 に、雑音が発生されても第 1基板支持部材 4 b は略基準電圧 (G N D ) に仮想的 に設定される如く発生雑音と逆位相で略同--振幅の相殺信号が増幅回路 7 aの出 力端子から第 1電圧制御領域 6 aへ印加される。 That is, the first substrate support member 4b is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is substantially referenced by the feedback operation of the amplifier circuit 7a. Virtually set to voltage (GND). At this time, even if noise is generated, the first substrate supporting member 4b generates a canceling signal having substantially the same phase and the same amplitude as that of the generated noise so that it is virtually set to the substantially reference voltage (GND). The output terminal of a is applied to the first voltage control area 6a.
この相殺の結果、 第 1基板支持部材 4 bの電位変動も低減され、 上記の浮遊容 量が無視できない場合でも、 非反転入力端子 (+ ) の接地リード端子のリード - インダクタンスに流れる雑音電流による雑音電圧も無視できるレベルとなる。 次に、 本発明の第 5の実施例を図 8により説明する。 As a result of this cancellation, the potential fluctuation of the first substrate supporting member 4b is also reduced, and even if the above-mentioned stray capacitance cannot be ignored, the noise current flowing through the lead-inductance of the ground lead terminal of the non-inverting input terminal (+) The noise voltage is also at a level that can be ignored. Next, a fifth embodiment of the present invention will be described with reference to FIG.
図 8の集積回路基板 3には、 アナログ部 1とデジタル部 2とが形成される。 集 積回路基板 3の底面には、 アナログ部 1に対応した位置のみにに導電体部 4 aが 接続され、 デジタル部 2に対応した位置には導電体部は形成されていない。 半導 体集積回路はこの導電体部 4 aを介して、 パッケージに固定され、 実装される。 アナログ部 1の回りには、 ガ一ドバンド 6 cが配置され、 またデジタル部 2の 回りにはガ一ドバンド 6 aが配置されている。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG. On the bottom surface of the integrated circuit board 3, the conductor portion 4a is connected only to the position corresponding to the analog portion 1, and the conductor portion is not formed at the position corresponding to the digital portion 2. The semiconductor integrated circuit is fixed and mounted on a package via the conductor portion 4a. A guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2.
雑音相殺信号発生回路 7 bはオペアンプなどの回路で構成され、 反転入力端子 (一) は、 直接アナログ部 1の導電体部 4 aに接続されている。 非反転入力端子 ( + ) は接地端子に、 出力端子はアナログ部 1のガードバン ド 6 cに接続される。 雑音相殺信号発生回路 7 bは、 フィードバック動作により、 常に最適な雑音相殺 信号を発生させてこれをガードバンド 6 cに印加し、 導電体部 4 aすなわちアナ 口グ部 1の基板底面が仮想接地電位を保つように働く。 The noise canceling signal generating circuit 7 b is configured by a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor section 4 a of the analog section 1. The non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to guard band 6c of analog section 1. The noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6c, so that the conductor portion 4a, that is, the bottom surface of the analog portion 1 is virtually grounded. It works to keep the potential.
一方、 デジタル部 2の基板電位は、 デジタル部 2の回りに配置したガードバン ド 6 aを接地することにより、 一定電圧を供給する。 この場合、 デジタル部 1の 基板領域内に雑音が残っていても、 アナログ部 1の基板下面に設けられた導電体 部 4 aを仮想接地制御することにより、 直接アナログ部 1の基板電位は一定に抑 えられ、 デジタル部からの基板雑音の影響を抑えることができる。 次に、 本発明の第 6の実施例を図 9により説明する。 On the other hand, the substrate potential of the digital section 2 supplies a constant voltage by grounding the guard band 6a disposed around the digital section 2. In this case, even if noise remains in the substrate area of the digital section 1, the conductor section 4a provided on the lower surface of the analog section 1 is virtually grounded, so that the substrate potential of the analog section 1 is directly constant. Therefore, the effect of substrate noise from the digital section can be suppressed. Next, a sixth embodiment of the present invention will be described with reference to FIG.
図 9の集積回路基板 3には、 アナログ部 1 とデジタル部 2とが形成される。 ァ ナ口グ部 1とデジ夕ル部 2の回りには、 それぞれリング状のガ一ドバンド 6 c、 6 dとリング状のガードバンド 6 a、 6 bが配置され、 集積回路基板 3の底面に は、 アナログ部 1 とデジタル部 2とに対応した位置に、 それぞれ独立の導電体部 4 aと導電体部 4 b力—接続される。 半導体集積回路はこれらの導電体部 4 a、 4 bを介して、 絶縁パッケージに固定され、 実装される。 アナログ部 1の回りには、 ガードバンド 6 cが配置され、 またデジタル部 2の回りにはガードバンド 6 aが 配置されている。 雑音相殺信号発生回路 7 b、 7 aはオペアンプなどの回路で構 成され、 反転入力端子 (一) は、 直接アナログ部 1の導電体部 4 a、 デジタル部 2の導電体部 4 bにそれぞれ接続されている。 非反転入力端子 (+ ) は接地端子 に、 出力端子はアナ口グ部 1のガ一 ドバン ド 6 c、 デジタル部 2のガードバンド 6 aに接続されている。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG. Ring-shaped guard bands 6c and 6d and ring-shaped guard bands 6a and 6b are arranged around the antenna opening section 1 and the digital signal section 2, respectively. In this case, independent conductor portions 4a and 4b are connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively. The semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b. A guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2. The noise canceling signal generation circuits 7b and 7a are composed of circuits such as operational amplifiers. The inverting input terminal (1) is directly connected to the conductor 4a of the analog unit 1 and the conductor 4b of the digital unit 2, respectively. It is connected. The non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6c of the analog unit 1 and the guard band 6a of the digital unit 2.
雑音相殺信号発生回路 7 bは、 フィードバック動作により、 常に最適な雑音相 殺信号を発生させ、 これらをガードバン ド 6 cに印加し、 導電体部 4 aすなわち アナログ部 1の基板底面力 ί仮想接地電位を保つように働く。 同様に、 雑音相殺信 号発生回路 7 aは、 フィードバック動作により、 常に最適な雑音相殺信号を発生 させ、 これらをガードバンド 6 aに印加し、 導電体部 4 bすなわちデジタル部 2 の基板底面が仮想接地電位を保つように働く。 The noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation, applies these signals to the guard band 6c, and applies the conductor portion 4a, that is, the bottom surface force of the analog portion 1 to the virtual ground. It works to keep the potential. Similarly, the noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by the feedback operation, applies these to the guard band 6a, and the conductor 4b, that is, the bottom of the substrate of the digital section 2 It works to keep the virtual ground potential.
このようにデジタル部 2の基板においては発生するデジタル雑音が低減され、 アナログ部 1の基板においてはデジタル部 2から到来する基板結合雑音を抑える ことができる。 従って、 これらの基板雑音の低減は、 アナログ部 1 とデジタル部 2とで独立に行われ、 より大きな雑音低減効果が得られる。 In this manner, digital noise generated on the board of the digital section 2 is reduced, and on the board of the analog section 1, board coupling noise coming from the digital section 2 can be suppressed. Therefore, the reduction of the substrate noise is performed independently by the analog unit 1 and the digital unit 2, and a greater noise reduction effect can be obtained.
次に、 本発明の第 7の実施例を図 1 0により説明する。 Next, a seventh embodiment of the present invention will be described with reference to FIG.
図 1 0の集積回路基板 3には、 アナログ部 1 とデジ夕ル部 2とが形成される。 デジタル部 2の回りには、 リング状のガードバンド 6 aが配置され、 集積回路基 板 3の底面には導電体部 4が設けられ、 アナログ部 1とデジタル部 2の基板底面 が共通に接続される。 半導体集積回路はこの導電体部 4を介して、 絶縁パッケ一 ジに固定され、 実装される。 雑音相殺信号発生回路 7 aの反転入力端子 (一) は直接導電体部 4に接続され、 非反転入力端子 (+ ) は接地端子に接続され、 出 力端子はデジタル部 2のガードバン ド 6 aに接続されている。 An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG. A ring-shaped guard band 6a is arranged around the digital section 2, a conductor section 4 is provided on the bottom of the integrated circuit board 3, and the board bottoms of the analog section 1 and the digital section 2 are connected in common. Is done. The semiconductor integrated circuit is fixed to an insulating package via the conductor portion 4 and mounted. The inverting input terminal (1) of the noise canceling signal generation circuit 7a is directly connected to the conductor section 4, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is the guard band 6a of the digital section 2. It is connected to the.
この結果、 雑音相殺信号発生回路 7 aは、 導電体部 4すなわちアナログ部 1 と デジタル部 2とに共通な集積回路基板の底面力 反想接地となるようにフィードバ ック動作を行い、 常に最適な雑音相殺信号を発生させ、 ガードバンド 6 aに印加 する。 As a result, the noise canceling signal generation circuit 7a performs a feedback operation so that the bottom surface force of the integrated circuit board common to the conductor portion 4, that is, the analog portion 1 and the digital portion 2, is imaginary, and is always optimal. Generate a noise canceling signal and apply it to guard band 6a.
すなわち、 雑音相殺信号発生回路 7 aにより、 デジタル部 2の基板において発 生するデジタル雑音が打ち消されて低減され、 アナログ部 1の基板においても、 デジタル部 2の基板雑音が低減されることにより、 安定な基板バイァス電位が得 られる。 That is, the signal is generated on the board of the digital section 2 by the noise canceling signal generation circuit 7a. The digital noise generated is canceled out and reduced, and the substrate noise of the digital unit 2 is reduced even on the substrate of the analog unit 1, whereby a stable substrate bias potential is obtained.
特に、 デジタル部 2に複数のデジタル回路力;、存在する場合、 これらのデジタル 回路領域の発生する基板雑音は、 一般に正負のデジタル雑音の総和になるため、 0を中心とした小さな値となる。 これを打ち消すことによって雑音の低減が図ら れるため、 雑音相殺信号は比較的小さな値でよい。 従って、 雑音相殺信号発生回 路 7 aは、 低消費電力で構成されることができる。 In particular, when a plurality of digital circuit powers are present in the digital section 2, the substrate noise generated by these digital circuit areas is generally a sum of positive and negative digital noises, and thus has a small value centered at 0. Since the noise is reduced by canceling the noise, the noise canceling signal may be a relatively small value. Therefore, the noise canceling signal generation circuit 7a can be configured with low power consumption.
次に、 導電体部の構成に関する本発明の第 8、 第 9の実施例を図 1 1、 図 1 2 により説明する。 Next, eighth and ninth embodiments of the present invention relating to the configuration of the conductor portion will be described with reference to FIGS. 11 and 12. FIG.
図 1 1では、 シリコン基板である p形半導体の低不純物濃度基板 1 0の内部ま たは底面に、 アナログ部 1 とデジタル部 2に対応して、 p +形半導体の高不純物 濃度層 8 a、 8 bをそれぞれ形成する。 これらの高濃度層 8 a、 8 bは、 本発明 の導電体部 4 a、 4 b (図 3〜図 9 ) の役割を果たし、 雑音相殺信号発生回路 7 a、 7 bとともに基板雑音の低減を図ることができる。 In Fig. 11, a high impurity concentration layer 8a of ap + type semiconductor is provided inside or on the bottom of a low impurity concentration substrate 10 of a p-type semiconductor, which is a silicon substrate, corresponding to the analog section 1 and the digital section 2. , 8b respectively. These high-concentration layers 8a and 8b serve as the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and reduce the substrate noise together with the noise canceling signal generation circuits 7a and 7b. Can be achieved.
図 1 2では、 シリコンバルク基板である p +形半導体の高不純物濃度シリコン 基板 1 3上のェピタキシャル層からなる低不純物濃度基板 1 4内に、 アナログ部 1とデジタル部 2とに対応して、 高不純物濃度埋め込み層 9 a、 9 bを形成する。 これらの高不純物濃度埋め込み層 9 a、 9 bは、本発明の導電体部 4 a、 4 b (図 3〜図 9 ) の役割を果たし、 雑音相殺信号発生回路 7 a、 7 bとともに基板雑音 の低減を図ることができる。 In Fig. 12, the low impurity concentration substrate 14 consisting of an epitaxy layer on the high impurity concentration silicon substrate 13 of p + type semiconductor, which is a silicon bulk substrate, corresponds to the analog unit 1 and the digital unit 2. Then, the high impurity concentration buried layers 9a and 9b are formed. These high impurity concentration buried layers 9a and 9b play the role of the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and the substrate noise together with the noise canceling signal generating circuits 7a and 7b. Can be reduced.
本発明の第 6、 第 7の実施例においては、 導電体部の役割を果たす、 高濃度層 8 aと 8 bの問、 あるいは埋め込み層 9 aと 9 bの間力、 基板の寄生抵抗により 結合する。 デジタル部 2とアナログ部 1の基板は分離されていないが、 雑音相殺 信号発生回路と組み合わせて、 デジタル部の基板雑音を低減し、 雑音の伝達を抑 制し、 アナ口グ部の基板電位を一定に保つことができる。 In the sixth and seventh embodiments of the present invention, the high-concentration layers 8a and 8b or the buried layers 9a and 9b act as a conductor, Join. The boards of the digital section 2 and the analog section 1 are not separated, but in combination with a noise canceling signal generation circuit, the board noise of the digital section is reduced, noise transmission is suppressed, and the board potential of the analog section is reduced. Can be kept constant.
本実施例の高不純物濃度層 8 a、 8 bおよび高不純物濃度埋め込み層 9 a、 9 bは集積回路のゥエルの下面に適用してゥェル基板の安定化を図ることもでき、 また S O I構造における基板に適用することもできる。 本実施例によって、 実装 条件に依存せず、 常に等しい雑音抑制効果を得ることが可能である。 The high impurity concentration layers 8a and 8b and the high impurity concentration buried layers 9a and 9b of this embodiment can be applied to the lower surface of the well of the integrated circuit to stabilize the well substrate. It can also be applied to a substrate. According to this embodiment, it is possible to always obtain the same noise suppression effect regardless of the mounting conditions.
本発明の実施例の雑音相殺信号発生回路 7 a、 7 bは同一集積回路に構成する ことによって、 デジタル回路の基板雑音を低減し、 アナログ回路への伝搬を防止 し、 アナログ回路の基板電位を安定に保ち、 アナログ Zデジタル混在集積回路の 電気的信頼性を向上することが可能である。 The noise cancellation signal generation circuits 7a and 7b according to the embodiment of the present invention are configured on the same integrated circuit to reduce the substrate noise of the digital circuit, prevent the propagation to the analog circuit, and reduce the substrate potential of the analog circuit. It is possible to maintain the stability and improve the electrical reliability of the analog-Z digital mixed integrated circuit.
本発明により、 回路の性能劣化もしくは誤動作の問題を解決可能な半導体集積 回路装置を提供することが可能となる。 産業上の利用可能性 According to the present invention, it is possible to provide a semiconductor integrated circuit device capable of solving the problem of circuit performance degradation or malfunction. Industrial applicability
本発明は、 半導体集積回路装置、 特に、 機能回路部であるアナログ回路 (アナ ログモジュール) とデジタル回路 (デジタルモジュール) とを同 -半導体チップ 上に集積してなるアナログ デジタル混在形半導体集積冋路装置において、 デジ タル回路の発生する雑音が共通半導体基板を経由してアナログ回路に及ぼす影響 などを低減する際に利用することができる。 The present invention relates to a semiconductor integrated circuit device, in particular, an analog / digital mixed semiconductor integrated circuit in which an analog circuit (analog module) and a digital circuit (digital module) which are functional circuit units are integrated on the same semiconductor chip. It can be used to reduce the effects of noise generated by digital circuits on analog circuits via a common semiconductor substrate.
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1996/002722 WO1998012750A1 (en) | 1996-09-20 | 1996-09-20 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1996/002722 WO1998012750A1 (en) | 1996-09-20 | 1996-09-20 | Semiconductor integrated circuit device |
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| Publication Number | Publication Date |
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| WO1998012750A1 true WO1998012750A1 (en) | 1998-03-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| PCT/JP1996/002722 Ceased WO1998012750A1 (en) | 1996-09-20 | 1996-09-20 | Semiconductor integrated circuit device |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2003003461A1 (en) * | 2001-06-27 | 2003-01-09 | Renesas Technology Corp. | Semiconductor integrated circuit device and method for reducing noise |
| US6744112B2 (en) | 2002-10-01 | 2004-06-01 | International Business Machines Corporation | Multiple chip guard rings for integrated circuit and chip guard ring interconnect |
| JP2007514321A (en) * | 2003-12-10 | 2007-05-31 | ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア | Low crosstalk circuit board for mixed signal integrated circuits |
| JP2007531281A (en) * | 2004-03-26 | 2007-11-01 | ハネウェル・インターナショナル・インコーポレーテッド | Technology and RF circuit design to reduce substrate crosstalk for mixed signals |
| JP2009536788A (en) * | 2006-05-08 | 2009-10-15 | インターナショナル レクティファイアー コーポレイション | Noise free technology of PWM modulator combined with gate driver stage in a single die |
| WO2011086612A1 (en) * | 2010-01-15 | 2011-07-21 | パナソニック株式会社 | Semiconductor device |
| JP2014090187A (en) * | 2013-12-09 | 2014-05-15 | Renesas Electronics Corp | Semiconductor integrated circuit and pattern layout method thereof |
| JP2015092570A (en) * | 2001-08-10 | 2015-05-14 | 株式会社半導体エネルギー研究所 | Light emitting device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2003003461A1 (en) * | 2001-06-27 | 2003-01-09 | Renesas Technology Corp. | Semiconductor integrated circuit device and method for reducing noise |
| JP2015092570A (en) * | 2001-08-10 | 2015-05-14 | 株式会社半導体エネルギー研究所 | Light emitting device |
| US6744112B2 (en) | 2002-10-01 | 2004-06-01 | International Business Machines Corporation | Multiple chip guard rings for integrated circuit and chip guard ring interconnect |
| JP2007514321A (en) * | 2003-12-10 | 2007-05-31 | ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア | Low crosstalk circuit board for mixed signal integrated circuits |
| JP2007531281A (en) * | 2004-03-26 | 2007-11-01 | ハネウェル・インターナショナル・インコーポレーテッド | Technology and RF circuit design to reduce substrate crosstalk for mixed signals |
| JP2009536788A (en) * | 2006-05-08 | 2009-10-15 | インターナショナル レクティファイアー コーポレイション | Noise free technology of PWM modulator combined with gate driver stage in a single die |
| WO2011086612A1 (en) * | 2010-01-15 | 2011-07-21 | パナソニック株式会社 | Semiconductor device |
| US8450836B2 (en) | 2010-01-15 | 2013-05-28 | Panasonic Corporation | Semiconductor device |
| JP2014090187A (en) * | 2013-12-09 | 2014-05-15 | Renesas Electronics Corp | Semiconductor integrated circuit and pattern layout method thereof |
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