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WO2001009950A1 - Module de boitier a semiconducteurs - Google Patents

Module de boitier a semiconducteurs Download PDF

Info

Publication number
WO2001009950A1
WO2001009950A1 PCT/JP2000/005181 JP0005181W WO0109950A1 WO 2001009950 A1 WO2001009950 A1 WO 2001009950A1 JP 0005181 W JP0005181 W JP 0005181W WO 0109950 A1 WO0109950 A1 WO 0109950A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
semiconductor package
clad plate
package unit
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2000/005181
Other languages
English (en)
Japanese (ja)
Inventor
Kinji Saijo
Kazuo Yoshida
Hiroaki Okamoto
Shinji Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Kohan Co Ltd
Original Assignee
Toyo Kohan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Kohan Co Ltd filed Critical Toyo Kohan Co Ltd
Priority to AU63171/00A priority Critical patent/AU6317100A/en
Publication of WO2001009950A1 publication Critical patent/WO2001009950A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H10W70/60—
    • H10W70/05—
    • H10W90/811—
    • H10W70/63—

Definitions

  • the present invention relates to a semiconductor package unit capable of coping with multiple integration of semiconductors.
  • the present invention particularly relates to a novel semiconductor package unit capable of mounting and storing a semiconductor chip having at least twice the capacity of a memory in the same space volume as a conventional semiconductor package.
  • semiconductor modules are electrically connected via a plurality of joints and provided between the semiconductor modules.
  • a plurality of electrodes having a predetermined function are configured by electrically connecting the bonded junctions, and the connection pattern up to the terminal junction of the semiconductor chip is made different in each semiconductor module, thereby forming a plurality of electrodes.
  • One of the electrodes is configured as a unique electrode of each semiconductor chip, and a pad is provided on the semiconductor chip to be electrically connected to the joint, and the connection pattern from the terminal of the semiconductor chip to the pad is formed in each half.
  • One of the plurality of electrodes is configured as a unique electrode of each semiconductor chip by making the conductor module different and the connection pattern between the joints is made different in each semiconductor module.
  • each film is formed by interposing a spacer having a wiring pattern for chip selection at the outer lead position between the first film carrier semiconductor module and the second film carrier semiconductor module.
  • a spacer having a wiring pattern for chip selection at the outer lead position between the first film carrier semiconductor module and the second film carrier semiconductor module.
  • the proposal of Japanese Patent Application Laid-Open No. H10-2223683 proposes that the surface of the film carrier where the inner leads are located faces the surface where the input / output surface of the semiconductor chip is located, and that the semiconductor chip passes through the device hole. By making it too small, the layer spacing can be reduced until the semiconductor chip and the film carrier's insulating film come into contact with each other, so that the space volume increases and the capacity in the package increases substantially. You.
  • one semiconductor chip is electrically connected to one bump via one bump and the inner lead portion connected to the bump.
  • the space existing between the chips cannot be filled, and therefore, as the number of stacked layers increases, the volume of this space also increases. Therefore, the effect of the project cannot be fully utilized.
  • a circuit is formed on the surface of the clad plate by etching the clad plate for the package unit by a wet method, and the circuit is connected to semiconductor chips disposed above and below the clad plate to be integrated. It is characterized by having done. Further, by stacking the unit (0 unit) on a printed circuit board or the like, a unit in which a large number of semiconductor chips are integrated can be manufactured.
  • the clad plate for forming the unit of the present invention is preferably made of a clad plate obtained by combining a plurality of copper foils and nickel foils.
  • the material of the clad plate is copper (Cu) foil and nickel ( Ni) It is preferable to use a combination of foils, for example, a clad plate consisting of CuZNi / Cu / Ni / (5Cu).
  • FIG. 1 is a cross-sectional view of an unprocessed clad material in a process explanatory view of a method for manufacturing a semiconductor package unit according to one embodiment of the present invention.
  • FIG. 2 shows the first embodiment of the present invention.
  • FIG. 19 is a cross-sectional view showing a state in which a resist for forming a columnar conductor is applied on a copper layer in the process explanatory view of the method for manufacturing a semiconductor package unit according to the embodiment D.0.
  • FIG. 3 is a cross-sectional view showing a state where a columnar conductor is formed by performing selective etching of a surface copper layer in a process explanatory view of a method of manufacturing a semiconductor package unit according to a first embodiment of the present invention.
  • FIG. 4 shows a semiconductor package unit according to the first embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing a state after selective etching of the nickel layer has been performed in the process explanatory view of the method for manufacturing the nickel layer.
  • FIG. 5 shows a semiconductor package according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a state after the application of an insulating resin and the polishing of the surface layer in the process explanatory view of the method for manufacturing a jujutsu.
  • FIG. 6 is a cross-sectional view showing a state in which a columnar conductor is also formed on the opposite surface in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention.
  • FIG. 7 is a half view according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a state after selectively etching the nickel layer on the opposite side in the process explanatory view of the method for manufacturing a conductor package unit.
  • FIG. 8 is a cross-sectional view showing a state after a circuit pattern forming photoresist resin is ground in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention.
  • FIG. 9 shows a method for manufacturing a semiconductor package unit according to the first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a state after a circuit pattern is formed by etching in the process explanatory diagram of FIG.
  • FIG. 10 shows a state in which an insulating resin is applied to the opposite surface on which a circuit is formed and the upper surface is polished in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention.
  • FIG. FIG. 11 is a process explanatory view of a method of manufacturing a semiconductor package unit according to the first embodiment of the present invention, in which semiconductor chips are mounted on both sides of a mounting board, connected, and further mounted on a printed board.
  • FIG. 4 is a cross-sectional view showing a state where the state is completed.
  • the nickel layer 20 is removed by selective etching.
  • a commercially available nickel etching agent such as Melstrip N-950 manufactured by Meltex Corporation is used.
  • an epoxy resin or a polyimide resin is applied as an insulating resin 39, and then the surface of the insulating resin layer 39 is polished to be uniform. At this time, the head of the columnar conductor 18 is exposed on the surface, and at the same time, the remaining resist film is removed.
  • the space at the time of lamination can be effectively eliminated, and Can increase the capacity of the entire package

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

La présente invention concerne un module de boîtier constituant un boîtier à semi-conducteurs ayant deux fois la capacité. Les deux faces d'une plaque plaquée (34) sont sélectivement attaquées en utilisant comme agent d'attaque humide une solution aqueuse constituée d'une combinaison d'un ou de plusieurs des chlorure ferrique, chlorure de cuivre (II), et l'acide sulfurique plus le peroxyde d'hydrogène pour former une base ayant une couche conductrice intérieure. Une couche d'isolation et une couche conductrice extérieure sont formées sur la surface extérieure de la base. La couche conductrice extérieure porte un motif. Les couches conductrices de l'intérieur et de l'extérieur sont électriquement connectées par des colonnes conductrices formées par attaque chimique dans la base. Les microplaquettes de semi-conducteurs (1, 2) sont montées sur les deux faces de la plaque plaquée de façon à former un module de boîtier à semi-conducteurs intégré monobloc.
PCT/JP2000/005181 1999-08-02 2000-08-02 Module de boitier a semiconducteurs Ceased WO2001009950A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU63171/00A AU6317100A (en) 1999-08-02 2000-08-02 Semiconductor package unit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP21892999 1999-08-02
JP11/218929 1999-08-02

Publications (1)

Publication Number Publication Date
WO2001009950A1 true WO2001009950A1 (fr) 2001-02-08

Family

ID=16727543

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/005181 Ceased WO2001009950A1 (fr) 1999-08-02 2000-08-02 Module de boitier a semiconducteurs

Country Status (4)

Country Link
JP (1) JP5105625B2 (fr)
AU (1) AU6317100A (fr)
TW (1) TW522530B (fr)
WO (1) WO2001009950A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094419A (ja) * 2007-10-12 2009-04-30 Fujitsu Ltd 回路基板および半導体装置
WO2020240850A1 (fr) * 2019-05-31 2020-12-03 ウルトラメモリ株式会社 Module semi-conducteur et son procédé de fabrication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03188660A (ja) * 1989-12-19 1991-08-16 Toppan Printing Co Ltd 半導体装置用リードフレーム用材及び半導体装置用リードフレームの製造方法
JPH05190764A (ja) * 1992-01-17 1993-07-30 Hitachi Ltd 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08241945A (ja) * 1995-03-03 1996-09-17 Sony Corp リードフレーム、半導体装置及び半導体装置の製造方法
JP3988227B2 (ja) * 1997-12-01 2007-10-10 日立化成工業株式会社 半導体チップ搭載用基板の製造法および半導体装置
JP3497774B2 (ja) * 1999-08-13 2004-02-16 株式会社ノース 配線基板とその製造方法
JP3798597B2 (ja) * 1999-11-30 2006-07-19 富士通株式会社 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03188660A (ja) * 1989-12-19 1991-08-16 Toppan Printing Co Ltd 半導体装置用リードフレーム用材及び半導体装置用リードフレームの製造方法
JPH05190764A (ja) * 1992-01-17 1993-07-30 Hitachi Ltd 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094419A (ja) * 2007-10-12 2009-04-30 Fujitsu Ltd 回路基板および半導体装置
WO2020240850A1 (fr) * 2019-05-31 2020-12-03 ウルトラメモリ株式会社 Module semi-conducteur et son procédé de fabrication
JPWO2020240850A1 (fr) * 2019-05-31 2020-12-03
JP7222564B2 (ja) 2019-05-31 2023-02-15 ウルトラメモリ株式会社 半導体モジュール及びその製造方法

Also Published As

Publication number Publication date
AU6317100A (en) 2001-02-19
JP5105625B2 (ja) 2012-12-26
TW522530B (en) 2003-03-01
JP2010004064A (ja) 2010-01-07

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