WO2001009950A1 - Semiconductor package unit - Google Patents

Abstract

A package unit constituting a semiconductor package having at least twice the capacity. The both faces of a clad plate (34) are selectively etched using as a wet etchant an aqueous solution consisting of a combination of one or two or more of ferric chloride, copper (II) chloride, and sulfuric acid plus hydrogen peroxide to form a base having an inner conductor layer, an insulation layer and an outer conductor layer are formed on the outer surface of the base, the outer conductor layer is patterned, and the inner and outer conductor layers are electrically connected, via a columnar conductor formed in the base by etching, with semiconductor chips (1, 2) mounted on the both faces of the clad plate, thereby forming an integral-structure semiconductor package unit.

Description

 Description Semiconductor Package Unit Technical Field

 The present invention relates to a semiconductor package unit capable of coping with multiple integration of semiconductors. In addition, the present invention particularly relates to a novel semiconductor package unit capable of mounting and storing a semiconductor chip having at least twice the capacity of a memory in the same space volume as a conventional semiconductor package. Background art

 In recent years, high integration boards, high pin count, miniaturization of semiconductor devices, and miniaturization and weight reduction of electronic devices have required high-density mounting boards. In addition, research and development on multi-layered wiring boards, improved wiring densities, and chip stacking structures are becoming more active.

 Such multi-layering methods have changed somewhat with changes in the package form, but the conventional method generally incorporates one chip per package, and the capacity per package increases unless the chip capacity increases. It was pointed out that there was a problem of not being able to do so.

As a method of improving this state, for example, in Japanese Patent Application Laid-Open No. H10-164334, semiconductor modules are electrically connected via a plurality of joints and provided between the semiconductor modules. A plurality of electrodes having a predetermined function are configured by electrically connecting the bonded junctions, and the connection pattern up to the terminal junction of the semiconductor chip is made different in each semiconductor module, thereby forming a plurality of electrodes. One of the electrodes is configured as a unique electrode of each semiconductor chip, and a pad is provided on the semiconductor chip to be electrically connected to the joint, and the connection pattern from the terminal of the semiconductor chip to the pad is formed in each half. One of the plurality of electrodes is configured as a unique electrode of each semiconductor chip by making the conductor module different and the connection pattern between the joints is made different in each semiconductor module.

 That is, according to this proposal, each film is formed by interposing a spacer having a wiring pattern for chip selection at the outer lead position between the first film carrier semiconductor module and the second film carrier semiconductor module. By electrically connecting the carrier semiconductor module, it is possible to have twice the memory and memory capacity in the same mounting and mounting space as the conventional package. With the same thickness, two or more film 10 carrier semiconductor modules can be stacked through a spacer, so that the chip capacity per package can be further increased.

 Also, the proposal of Japanese Patent Application Laid-Open No. H10-2223683 proposes that the surface of the film carrier where the inner leads are located faces the surface where the input / output surface of the semiconductor chip is located, and that the semiconductor chip passes through the device hole. By making it too small, the layer spacing can be reduced until the semiconductor chip and the film carrier's insulating film come into contact with each other, so that the space volume increases and the capacity in the package increases substantially. You.

 However, according to the method proposed in Japanese Patent Application Laid-Open No. H10-1636414, one semiconductor chip is electrically connected to one bump via one bump and the inner lead portion connected to the bump. However, as long as this type of structure is adopted, the space existing between the chips cannot be filled, and therefore, as the number of stacked layers increases, the volume of this space also increases. Therefore, the effect of the project cannot be fully utilized.

In addition, the method proposed in Japanese Patent Application Laid-Open No. H10-2223683 has a problem that the space in this portion is insufficiently utilized because the connection between the layer and the via hole is performed by solder balls. There is. The present invention is intended to solve the conventional problem by minimizing the space volume existing between the chips, which is generated when a plurality of such chips are stacked. By adopting the method, the chip capacity in the semiconductor package can be at least doubled compared to the conventional method. Disclosure of the invention

 In the semiconductor package of the present invention, a circuit is formed on the surface of the clad plate by etching the clad plate for the package unit by a wet method, and the circuit is connected to semiconductor chips disposed above and below the clad plate to be integrated. It is characterized by having done. Further, by stacking the unit (0 unit) on a printed circuit board or the like, a unit in which a large number of semiconductor chips are integrated can be manufactured.

 The clad plate for forming the unit of the present invention is preferably made of a clad plate obtained by combining a plurality of copper foils and nickel foils. Specifically, the material of the clad plate is copper (Cu) foil and nickel ( Ni) It is preferable to use a combination of foils, for example, a clad plate consisting of CuZNi / Cu / Ni / (5Cu).

 FIG. 1 is a cross-sectional view of an unprocessed clad material in a process explanatory view of a method for manufacturing a semiconductor package unit according to one embodiment of the present invention. FIG. 2 shows the first embodiment of the present invention.

FIG. 19 is a cross-sectional view showing a state in which a resist for forming a columnar conductor is applied on a copper layer in the process explanatory view of the method for manufacturing a semiconductor package unit according to the embodiment D.0. FIG. 3 is a cross-sectional view showing a state where a columnar conductor is formed by performing selective etching of a surface copper layer in a process explanatory view of a method of manufacturing a semiconductor package unit according to a first embodiment of the present invention. . FIG. 4 shows a semiconductor package unit according to the first embodiment of the present invention.

FIG. 5B is a cross-sectional view showing a state after selective etching of the nickel layer has been performed in the process explanatory view of the method for manufacturing the nickel layer. FIG. 5 shows a semiconductor package according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a state after the application of an insulating resin and the polishing of the surface layer in the process explanatory view of the method for manufacturing a jujutsu. FIG. 6 is a cross-sectional view showing a state in which a columnar conductor is also formed on the opposite surface in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention. FIG. 7 is a half view according to the first embodiment of the present invention.

5 is a cross-sectional view showing a state after selectively etching the nickel layer on the opposite side in the process explanatory view of the method for manufacturing a conductor package unit. FIG. 8 is a cross-sectional view showing a state after a circuit pattern forming photoresist resin is ground in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention. . FIG. 9 shows a method for manufacturing a semiconductor package unit according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a state after a circuit pattern is formed by etching in the process explanatory diagram of FIG. FIG. 10 shows a state in which an insulating resin is applied to the opposite surface on which a circuit is formed and the upper surface is polished in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the first embodiment of the present invention. FIG. FIG. 11 is a process explanatory view of a method of manufacturing a semiconductor package unit according to the first embodiment of the present invention, in which semiconductor chips are mounted on both sides of a mounting board, connected, and further mounted on a printed board. FIG. 4 is a cross-sectional view showing a state where the state is completed. FIG. 12 is a cross-sectional view of an unprocessed clad material in the process explanatory diagram of the method for manufacturing a semiconductor package according to the second embodiment of the present invention. FIG. 13 is a cross-sectional view showing a state in which a columnar conductor and a lead frame forming resist are applied on a layer 0 in the process explanatory view of the method for manufacturing a semiconductor package unit according to the second embodiment of the present invention. It is. FIG. 14 is a process explanatory view of a method of manufacturing a semiconductor package unit according to the second embodiment of the present invention, showing a state in which a columnar conductor and a lead frame line are formed by selectively etching a surface copper layer. FIG. FIG. 15 is a cross-sectional view showing a state after performing selective etching of the nickel layer in the process explanatory view of the method for manufacturing a semiconductor package unit according to the second embodiment of the present invention. FIG. 16 is a process explanatory view of a method for manufacturing a semiconductor package unit according to the second embodiment of the present invention. It is sectional drawing which showed the state after grinding | polishing. FIG. 17 is a cross-sectional view showing a state in which a columnar conductor and a lead frame line are also formed on the opposite surface in the process explanatory view of the method for manufacturing a semiconductor package unit according to the second embodiment of the present invention. FIG. FIG. 18 shows the steps of the method for manufacturing a semiconductor package unit according to the second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a state after the nickel layer on the opposite surface is selectively etched in the explanatory diagram. FIG. 19 is a process explanatory view of a method for manufacturing a semiconductor package unit according to the second embodiment of the present invention, in which a circuit pattern and a lead resin for forming a lead frame line have been ground. It is sectional drawing which showed the state. FIG. 20 is a flowchart illustrating a method of manufacturing a semiconductor package unit according to the second embodiment of the present invention.

| FIG. 0 is a cross-sectional view showing a state after a circuit pattern is formed by etching in FIG. FIG. 21 is a cross-sectional view showing a state after the substrate is coated and filled with an insulating resin in the process explanatory diagram of the method for manufacturing a semiconductor package unit according to the second embodiment of the present invention. FIG. 22 is a process explanatory view of a method of manufacturing a semiconductor package unit according to the second embodiment of the present invention, showing a state where a semiconductor chip is mounted on a substrate and an end portion is processed by a lead frame. It is sectional drawing. FIG. 23 is a sectional front view of an apparatus for manufacturing a clad metal plate used in the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

 The clad plate is prepared by pressing at a rolling reduction of 0.1 to 3% together with a foil material forming a conductor layer and a nickel foil material or a nickel plating laminate forming an etching stop layer, After the preparation, the bonding surface of the copper foil and the nickel foil or the nickel-plated layer is activated in advance in a vacuum chamber, and then the copper foil and the nickel foil or the nickel layer are laminated. It is formed by cold welding at a reduction rate of 3%.

¾ At this time, the activation treatment is performed in an ultra-low pressure inert gas atmosphere of (13.3 to 0.013 Pa). (2) The copper foil and the nickel layer having the bonding surface are grounded respectively. Contact Apply a 1 to 50 MHz alternating current between one electrode A and the other electrode B, which is insulated and supported, to cause a glow discharge, and ③ and a plasma generated by the glow discharge It is preferable to use an electrode whose exposed area is 1 to 3 times or less of the area of the electrode B and which is obtained by performing a sputtering process.

 The surface of the clad plate is selectively etched using an aqueous solution composed of one or more of ferric chloride, cupric chloride, or sulfuric acid + hydrogen peroxide as a wet etching solution. To form a columnar conductor and further form a wiring layer. Also, by applying an insulating resin to the etched portion of the clad plate, the strength of the clad plate can be increased. It is particularly preferable in terms of strength when two or more package units are stacked and used as a multi-layer package. Further, the package unit of the present invention may be covered with an epoxy resin or the like to form a completely sealed package.

 Hereinafter, the present invention will be specifically described with reference to the embodiments shown in the accompanying drawings. First, the structure of a semiconductor package unit according to an embodiment of the present invention will be described with reference to FIG.

This will be described with reference to I0 and FIG. As shown in the figure, a nickel plating layer (thickness ◦.) Serving as an etching stopper is formed on both sides of a copper foil layer 19 serving as a wiring layer (preferably having a thickness of 100 to 100 μιη) formed of copper foil. Or 5 to 3 xm) or a nickel foil layer (thickness: 5 to 10 Aim) 20 and 21 are joined to form a base core.

 o Next, a bump 18 (preferably having a thickness of 10 to 100 / zm) for connecting to the semiconductor chip 1 is formed on the copper foil layer 19 serving as a wiring layer. On the side, a mounting board 41 made of insulating resin is formed, and the other chip 2 is connected to the lower part of the connecting bump 17 (preferably 10 to 100 // m). Further, solder bumps 3 are formed on the lower part of the printed circuit board.

^ Next, a method of manufacturing the above-described semiconductor package unit will be described with reference to FIGS. First, the formation of a three-layer clad plate will be described. First, the semiconductor package When manufacturing a cage knit, the copper layer 19 (preferably 10 to 100 / Xm in thickness) serving as an internal conductor layer is provided on both sides with a thickness of 0.5 to 3.0 serving as an etching stopper layer 20 and 21. Form a nickel plating layer of 0 μπι. In this nickel plating, nickel plating which is usually used is applied to both surfaces of the copper foil.

 & When using a nickel foil instead of a nickel plating layer, first use a cladding plate manufacturing device shown in Fig. 23 to crimp a nickel foil with a thickness of 5 to 10 μm on one side of the copper foil. I do. Further, a nickel foil is pressed on the opposite surface to form a three-layer clad plate of a Ni foil, a Cu foil, and a Ni foil. In the following description, the case of nickel-plated copper foil will be described for convenience of explanation.

 10 Next, a foil material (3-layer clad plate of NiZCuZNi) with nickel plating on both sides 22 was connected to one of the unwinding leads in the clad plate manufacturing apparatus shown in Fig. 23. And wrap it around Further, a copper foil material 24 to be the columnar conductor 17 is wound around the other rewinding reel 25.

 Nickel-plated copper foil material 2 2 and copper foil material 2 4

1 At the same time, the film is rewound and a part thereof is wound around electrode rolls 27 and 28 projecting into the etching chamber 26, and is sputter-etched and activated in the etching chamber 26. Thereafter, the nickel-plated copper foil material 22 and the copper foil material 24 are pressed by the rolling rolls 29 and 30, and the clad plate 31 is wound on the winding roll 32. By this pressure bonding, a four-layered clad plate of CuZNiN

20 In this case, the activation process is performed as described in (1) Japanese Patent Application Laid-Open No. 1-2224184, as described in (1) 13.3-0.013Pa In an active gas atmosphere, (2) nickel plating with a joint surface (2) The foil material 22 and the copper foil material 24 are each grounded to one electrode A, and between 1 and 5 between the other electrode B that is insulated and supported. A glow discharge is caused by applying an alternating current of 0 MHz, and ③ and generated by the glow discharge

^ 5 The area of the electrode exposed in the plasma is 1 Z3 or less of the area of the electrode B, and the sputtering is performed by ④ sputtering. Next, the clad plate having the four-layer structure is wound around the rewind reel 23 again. In addition, a copper foil material 33 (see FIG. 1) to be a connection bump 18 is wound around a rewind reel 25. Both rewinding reels 2, 3 and 25 The four-layer clad plate and foil material are rewound respectively, and a part of the electrode roll 2 is projected into the etching chamber 26.

^ 7 and 28, and in the etching chamber 26, the nickel surface of the clad plate and the surface of the copper foil material are activated by sputter etching.

 In this case as well, the activation treatment is performed in the same manner as in (1) in an extremely low pressure inert gas atmosphere of 13.3 to 0.33 Pa, (2) clad plate having a bonding surface and copper foil material. 3 is one electrode A grounded to each, and 1 to 5 between the other electrode B supported insulated.

! Apply an alternating current of 0 MHz to cause a glow discharge, and ③ and the area of the electrode exposed in the plasma generated by the glow discharge is not more than one-third of the area of the electrode B. ④ By performing a sputter etching process.

 After that, the nickel surface of the clad plate 22 and the copper foil material 24 are press-bonded by the rolling rolls 29 and 30, and are wound around the take-up opening 32. By this pressure bonding, a five-layer clad plate of Cu / Ni / Cu / NiZCu is formed.

 By the above operation, as shown in FIG. 1, a clad plate 34 having a five-layer structure is manufactured.

 In this way, by repeatedly performing pressure welding using the clad plate manufacturing apparatus shown in Fig. 23, a layer of 鏑 is provided on the front and back layers in the order of 鏑, ノ, and a nickel layer is interposed between the middle 20 layers. A multi-layer clad plate can be manufactured.

 In addition, three or more of the above-mentioned rewind reels are installed, and copper foil and nickel foil are installed on these reels, and the foil material is simultaneously supplied from the three or more reels. Thus, a clad plate having a multilayer structure can be manufactured.

Next, after the clad plate 34 is cut into a desired size, a semiconductor package unit is manufactured through the following steps described with reference to FIGS. 2 to 11. FIG. 2 to FIG. 11 are for explaining the first embodiment of the present invention. First, as shown in FIG. 2, after a photoresist film 35 is formed on the surface of the foil material 24, exposure and development are performed. Next, as shown in FIG. 3, the copper foil material 24 is selectively etched, and the copper foil material 24 is dissolved and removed while leaving the columnar conductor 18. In this case, it is preferable to use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of ammonium persulfate as the etching solution. Note that the etching process is performed by immersing the object to be processed in an aqueous solution of etching. Alternatively, the aqueous solution of etching may be sprayed or dropped on the surface to be etched. In the case of spraying or dropping, it is sufficient to perform the resist treatment only on the uppermost layer using a method such as spinner coating. When performing the etching treatment by immersion in the etching solution, immerse it in the etching solution bath (5) for about 1 to 10 minutes.

\ 0 Although the setting is performed, the optimum conditions for each bath temperature and immersion time can be determined by the amount of work and time.

 Next, as shown in FIG. 4, the nickel layer 20 is removed by selective etching. As the etching solution, a commercially available nickel etching agent such as Melstrip N-950 manufactured by Meltex Corporation is used. Thereafter, as shown in FIG. 5, an epoxy resin or a polyimide resin is applied as an insulating resin 39, and then the surface of the insulating resin layer 39 is polished to be uniform. At this time, the head of the columnar conductor 18 is exposed on the surface, and at the same time, the remaining resist film is removed.

 Next, as shown in FIG. 6, the same processing is performed on the other surface of the mounting board. That is, after forming a photoresist film (not shown) on the surface of the copper foil material 33, the film is exposed and developed, and then the copper foil material 33 is selectively etched to leave the columnar conductor 17. The foil material 3 3 is removed. In this case, it is preferable to use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of ammonium persulfate as the etching solution.

 Next, as shown in FIG. 7, the nickel layer 21 is further removed by selective etching. In this case, as the etching solution, a commercially available nickel etching agent such as Melstrip N-950 manufactured by Meltex Corporation is used as described above.

Next, in order to form a circuit on the surface of the substrate after these treatments, FIG. After the photoresist film 37 is applied, exposed, and developed as described above, the copper foil 19 is selectively etched to form a circuit as shown in FIG. In this case, as the selective etching solution, an aqueous solution of ferric chloride, an aqueous solution of sulfuric acid and hydrogen peroxide, or the like can be used. By this process, a wiring layer is formed. Thereafter, as shown in FIG. 10, an epoxy resin or a polyimide resin is applied as an insulating resin 39, and then the surface of the insulating resin layer 39 is polished to be uniform. At this time, the head of the columnar conductor 17 is exposed on the surface, and at the same time, the remaining resist film is removed.

 Finally, as shown in Fig. 11, commercially available semiconductor chips 1 and 2 are connected to both surfaces of the wiring layer with an anisotropic conductive adhesive containing conductive particles, and the mounting substrate 10 on which the chips are mounted on both sides is mounted. Is mounted on a printed circuit board 41 covered with an insulating layer to form a package unit. The lower part of the printed circuit board is connected to another board by the solder ball 3, and can be further laminated to form a semiconductor package. In addition, the semiconductor chips 1 and 2 on the mounting board can be embedded by using an insulating resin such as an epoxy resin or a polyimide resin as necessary.

Next, the manufacture of the package unit according to the second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the thickness of the clad plate is kept constant without removing both end portions of the clad plate by etching. The reason for this is to use the clad plate as a substitute for the lead frame of the semiconductor package unit as shown in FIG. This implementation

Also in the tenth embodiment, the method of manufacturing the clad plate is the same as that of the first embodiment, and therefore the description thereof is omitted.

First, as shown in FIG. 13, after a photoresist film 35 is formed on the surface of the foil material 24, exposure and development are performed. In this case, the difference from the first embodiment is that in the second embodiment, a photoresist film 36 for forming a lead frame is formed at both ends of the substrate. Next, as shown in FIG. 14, the copper foil material 24 is selectively etched, and the copper foil material 24 is dissolved and removed while leaving the columnar conductor 18 and the lead frame 38. . In this case, it is preferable to use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of ammonium persulfate as the etching solution. The etching conditions in this case are the same as those in the first embodiment.

 Next, as shown in FIG. 15, the nickel layer 20 is removed by selective etching and etching as in the first embodiment. Thereafter, as shown in FIG. 16, an epoxy resin or a polyimide resin is removed from the insulating resin 39. Then, polishing is performed to make the surface of the insulating resin layer 39 uniform. At this time, the head of the columnar conductor 18 is exposed on the surface, and at the same time, the remaining resist film is removed.

 Next, as shown in Fig. 17, the same process is performed on the other surface of the mounting board. That is, after a photoresist film (not shown) is formed on the surface of the copper foil material 33, exposure and development are performed, and then the copper foil material 33 is selectively etched to form the columnar conductor 17 and the lead frame 38. The copper foil material 33 is removed while leaving. In this case, it is preferable to use an aqueous solution of sulfuric acid and hydrogen peroxide or an aqueous solution of ammonium persulfate as the etching solution.

 Next, as shown in FIG. 18, the nickel layer 21 is further removed by selective etching. The etching liquid in this case is also the same as that in the first embodiment. Next, in order to form a circuit on the surface of the substrate after these processes, a photoresist film 37 was applied, exposed, and developed as shown in FIG. 19, and then, as shown in FIG. The copper foil 19 is selectively etched to form a circuit. The selective etching conditions in this case are the same as those in the first embodiment. Thereafter, as shown in FIG. 21, an epoxy resin or a polyimide resin is applied as an insulating resin 39, and then the insulating resin is applied.榭 Make the surface of the resin layer 39 uniform.

Finally, a commercially available semiconductor chip is connected to both surfaces of the wiring layer with an anisotropic conductive adhesive containing conductive particles in the same manner as in the first embodiment, and a mounting board on which the chip is mounted on both sides is used. I do. The mounting board with chips 1 and 2 mounted on both sides is as shown in Figure 22. In this case, chips 1 and 2 are made of insulating resin such as epoxy resin or polyimide resin. It is covered with a grease layer 42. In the second embodiment, the lead frame portion 38 in FIG. 18 and the like is bent and used as a package knit as shown at the end portion 43 in FIG. A large number of such package units with a lead frame are connected via a spacer or the like, and can be used as a semiconductor package. Industrial applicability

 As described above, by using the clad plate according to claim 1 to form a package unit having chips mounted on both sides thereof, the space at the time of lamination can be effectively eliminated, and Can increase the capacity of the entire package

. Further, since the clad plate used in the present invention uses a press-welded product, the production cost can be reduced, and the semiconductor package unit can be easily manufactured by performing selective etching using the clad plate. Production costs are low.

Claims

The scope of the claims 1. A semiconductor package unit in which a semiconductor chip connection bump and a wiring layer are formed by selectively etching a clad plate, and semiconductor chips are mounted on both surfaces of the clad plate. 2. The semiconductor package unit according to claim 1, wherein the clad plate is formed of five layers of copper / nickel copper Z nickel copper.