WO2000069108A1

WO2000069108A1 - Synchronization method and apparatus

Info

Publication number: WO2000069108A1
Application number: PCT/SE2000/000874
Authority: WO
Inventors: Christer Bohm; Bengt J. Olsson; Magnus Danielson
Original assignee: Net Insight AB
Current assignee: Net Insight AB
Priority date: 1999-05-06
Filing date: 2000-05-04
Publication date: 2000-11-16
Anticipated expiration: 2001-11-06
Also published as: SE9901655L; AU4792100A; SE9901655D0

Abstract

The present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network. According to the invention, two or more input frame synchronization signals are received and one of them is selected to be used as a current reference for frame synchronization. A node synchronization signal is generated to have a frame frequency that is controlled by a frame frequency control signal. A difference signal is provided to represent a current difference between a desired frame phase difference and the frame phase difference between a feedback version of said node synchronization signal and the selected input frame synchronization signal that is used as the current reference for frame synchronization. Said difference signal is low pass filtered, and the low pass filtered signal is then offset according to an offset signal, thereby to form said frame frequency control signal.

Description

SYNCHRONIZATION METHOD AND APPARATUS

Technical Field of the Invention

The present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network.

Background of the Invention

In all communication networks, an essential task to be addressed is how to synchronize the operation of the network and of the different equipment and components that form part of the network. Prior art provides many different approaches to address this task.

In most synchronous network systems, the operation of the entire network is strictly synchronized to a common synchronization source. In one such example, each node has its own direct connection to this common synchronization source, which is thereby connected to directly synchronize the operation at each node of the network. In another example, synchronization is forwarded from the common synchronization source through the network to reach all network nodes in a top-down manner, forming a so-called synchronization spanning-tree within the network. In the latter example, each output port of a node is typically strictly synchronized according to synchronization signals received at an input port of the node. In some type of networks, a node may furthermore be required to operate in relation to links that may not be exactly in phase, to handle occasional phase variations, and to keeping phase variations within acceptable limits.

Any system distributing a frequency from a synchro- nization source will experience phase distortions such as jitter and wander caused by different components showing different delays, different temperature dependencies, alignment jitters, quantization noise, and the like. In most cases, it may be assumed that all local components distributing the synchronization signal will be incor- rect, and this incorrectness must be handled, corrected for, or the error they causes must be suppressed, which often means complicated and expensive implementations.

An object of the invention is therefore to provide a simple and effective way of forwarding synchronization throught a node while limiting the effect caused by different components showing different characteristics.

Another object of the invention is to proide a solution that decreases the amount of phase deviations caused by the above mentioned and similar effects, thereby increasing the quality of synchronization within the network.

Summary of the Invention The above mentioned objects are achieved by the invention as defined in the accompanying claims.

According to the invention, two or more input frame synchronization signals are received and one of them is selected to be used as a current reference for frame synchronization. A node synchronization signal is generated to have a frame freqency that is controlled by a frame frequency control signal. A difference signal is provided to represent a current difference between a desired frame phase difference and the frame phase difference between a feedback version of said node synchronization signal and the selected input frame synchronization signal that is used as the current reference for frame synchronization. Said difference signal is low pass filtered, and the low pass filtered signal is then offset according to an offset signal, thereby to form said frame frequency control signal.

The precense of a non-zero steady state DC offset of the input/output signals of a low-pass loop filter limits the freedom of implementation of the loop filter and the possibilities of adjusting loop filter characteristics, which for example is desirable in order to accomodate for characteristics of other parts of the node design, thereby requiring complex loop filter designs.

The fact that the steady-state control signal to the generator is provided according to the invention as the sum of an offset signal and the low-pass filtered signal from the low-pass filter has the effect of reducing any steady-state non-zero DC components in the signal treated by the low-pass filter performing the low-pass filtering. The nominal steady-state input/output signal handled by the low-pass loop filter may thus be reduced from some arbitrary value forming the stability of the loop (in relation to the characteristics of the generator) into nominally zero. As this means that the loop filter characteristics, using the invention, can be ajdusted at a zero stady-state DC signal level, the implementation of the loop filter may be simplified and so may the components and methods used for adjusting the loop filter characteristics .

To be noted, in a steady state situation, the frequ- ency control signal, i.e. the used offset signal, will reflect the actual frequency of the network. The offset signal thus also provides a means for "memorizing" the network frequency.

Another advantage of the invention is that it ensures phase continuity in the distributed frame frequency during switches of synchronization input signal. The amount of frame phase distortions caused by, for example, alignment jitters and the like originating from changes in the selection of synchronization source will be redu- ced. Using the invention, a node will have the ability to make sure that the synchronization signal that it distributed to downstream nodes will remain continuous and essentially phase-shift free when the node is required to switch from using one input signal into using to another as reference for synchronization.

The node synchronization signal may as such be distributed to downstream nodes as an output frame synch- ronization signal of the node. However, according to a preferred embodiment of the invention, the phase-shift free node synchronization signal is used to synchronize transmission of two or more output frame synchronization signals. Preferably, this is performed in such a way that each one of said output frame synchronization signals is controlled to show a respective phase, in relation to the node synchronization signal, that is permissible to be controlled individually for each respective output frame synchronization signal, thereby accomodating for having different phases on different output links, and to adjucting the delays with respect to different input/output ports individually. This embodiment has the advantage of allowing different phase situations to exist simultaneously at different ports of a node.

For definition, a phase-shift herein refers to the situation wherein an essential discontinuity, or "jump", occurs or is generated in the phase of a signal if not desired, however not excluding the possibility of allowing the phase to be gradually and in a continuous manner be adjusted over time as desired.

The invention is especially advantageous in networks wherein the synchronization requirements are such that each frame synchronization signal may show a limited jitter and may be arbitrarily located in phase in relation to other frame synchronization signals, but may not show any persistent frame drift in relation to other frame synchronization signals.

Also, the invention is primarily conserned with the propagation of synchronization on a frame level, however not being limited thereto. To be understood means for providing synchronization on a bit or slot level, while synchronizing a bit frequency and/or a slot frequency, could be added as well. However, note that for example in a network such as DTM, a nominal bit frequency will be generated individually by each node for and will thus essentially not be propagated through the network. A frame synchronization signal according is prefer- rably, but not necessarily, a so-called start of frame signal that designates the start of a frame on a link and that is transmitted togehter with the frame on said link. Simliarily, the node synchronization signal could for example also, but not necessarily, be regarded as a frame start signal, although in many situations it need not itself designate the actual start of frames. Specifically, the invention is contemplated for use in a DTM- network. Further information on the basics of DTM technology is found in "The DTM Gigabit Network", Christer Bohm, Per Lindgren, Lars Ramfelt, and Peter Sjδdin, Journal of High Speed Networks, 3 (2 ): 109-126, 1994, and "Multi-gigabit networking based on DTM", Lars Gauffin, Lars Hakansson, and Bjorn Pehrson, Computer networks and ISDN Systems, 24 (2 ): 119-139, April 1992.

This application is one in a series of three applications that were filed at the Swedish Patent Office on the same day, having the same title, the same applicant, and all referring to related inventive ideas, the description of the other two hereby being incorporated herein by reference.

The above mentioned and other aspects, features and details of the invention will be more fully understood from the following description of a preferred embodiment thereof.

Brief Description of the Drawings

Exemplifying embodiments of the invention will now be described with reference to the accompanying drawings, wherein:

Fig. 1 schematically shows a network node according to an embodiment of the invention;

Figs. 2A and 2B schematically show respective exem- plifying embodiments of the node synchronization block shown in Fig. 1; Fig. 3A shows a time diagram illustrating the operation of the node synchronization block shown in Fig. 1;

Fig. 3B shows exemplifying characteristics of the generator of the node synchronization block illustrated in Figs. 3A and 3B; and

Fig. 4 schematically shows an exemplifying embodiment of the output port blocks shown in Fig. 1.

Detailed Description of Preferred Embodiments Fig. 1 schematically shows a network node 200 that comprises three input port blocks 250a-250c, a node synchronization block 300, a switch core 400, a node controller 450, and three output port blocks 500a-500c.

Each one of the input port blocks 250a-250c is arranged to receive regularly occurring frames of data, divided into time slots, from respective input links. The location of each frame on the respective link is identified by an input frame synchronization signal, also being referred to as a frame start signal while being located in the stream of data to mark the beginning of each frame, which is carried along with the frames on the respective link. In this example, it is assumed that the frame frequency is nominally 8 kHz, corresponding to a frame length of 125 μs . Consequently, the frame synchro- nization signal of each respective link will be nominally received each 125 μs at the respective input port block.

Each input port block 250a-250c is arranged to derive data from time slots of received frames and to transmit such slot data to the switch core 400. Also, each input port block 250a-250c is arranged to derive the respective input frame synchronization signal from the respective input stream of data and to transmit said signal to the node synchronization block 300 and to a respective output port block 500a-500c. The switch core 400 is arranged to switch slots of data from the input port blocks 250a-250c to the output port blocks 500a-500c in accordance with switching instructions defined by the node controller 450. Furthermore, the switch core 400 is arranged to switch slots of data received in one or more control channels at the input port blocks 250a-250c from the input port blocks 250a-250c to the node controller 450, and to switch time slots of data to be transmitted in one or more control channels at the output port blocks 500a-500c from the node controller 450 to the output port blocks 500a-500c.

Data received/transmitted in said control channels from/to other nodes of the network will typically include channel management information. Based upon such channel management information, the node controller 450 will provide the switch core 400 with said switching instructions . Data received/transmitted in said control channels may for example include synchronization messages which are evaluated by the node controller 450 and based on which it will select which input link, i.e. which input frame synchronization signal, that is to be used as synchronization source for synchronizing of the operation of the node 200. Based upon such a selection, the node controller 450 is connected to provide the node synchronization block 300 with a synchronization selection signal that identifies which input frame synchronization signal to use as synchronization source, the timing at which a switch to using another frame synchronization signal as synchronization source is to take place, and similar related information.

The node synchronization block 300 is connected to receive the input frame synchronization signals from the respective input port blocks 250a-250c and the synchronization selection signal from the node controller 450. Based upon these signals, the node synchronization block 300 is arranged to generate a node internal frame synch- ronization signal, also referred to below as node synchronization signal. The node synchronization signal is generated to have a continuous phase, i.e. to be essenti- ally phase-shift free, which means that a change of synchronization source for generating said node synchronization signal will not as such cause any essential discontinuities or phase-shifts in the node synchronization signal. The node syncnronization signal generated by the node synchronization block is transmitted to each one of the output port blocks 500a-500c. Examples on how the phase-shift free node synchronization signal is generated by the node synchronization block 300 will be described in detail below with reference to Figs. 2A and 2B.

Each one of the output port blocks 500a-500c typically receives data in slots from the switch core 400, input frame synchronization signals from a respective input port block 250a-250c, and the node synchronization signal from the node synchronization block 300. Using the node synchronization signal as synchronization source, optionally taking into account the phase of the respective received input frame synchronization signal, each output port will generate a respective output frame synchronization signal and will transmit said output frame synchronization signal as a frame start signal along with frames of time slot data received from the switch core 400 on a respective output link. An example on how this is performed will be described in detail below with reference to Fig. 4.

In operation, input port block 250a and output port block 500a could typically be configured as together forming a first input/output interface, input port block 250b and output port block 500b would be configured as together forming a second input/output interface, and input port block 250c and output port block 500c, would be configured as together forming a third input/output interface. Each interface would then optionally be connected to provide read and write access to a respective point-to-point link, or to a respective unidirectional bus, wherein frames of slots received at, for example, the input port 250a would be switched essentially as a whole by the switch core 400 to be transmitted essentially unaffected, with the exemption of specific slots being switch to/from other ports, at output port 500a. A first embodiment 300-A exemplifying an implementation the node synchronization block 300 shown in Fig. 1 will now be described with reference to Fig. 2A. The embodiment 300-A comprises a selection unit 343, a phase offset detector 313, a first sample-and-hold circuit 323, a subtracting circuit 324, a low-pass filter 325, an adding circuit 326, a second sample-and-hold circuit 327, and a node synchronization signal generator 348.

The block 300-A is connected to receive input frame synchronization signals from all input port blocks 250a- 250c. The block 300-A is moreover arranged to generate a phase-shift free node synchronization signal based thereupon, as controlled by control signals from the node controller 450, and to output this node synchronization signal to the output port blocks 500a-500c. For that purpose, the selection unit 343 is connected to receive the input frame synchronization signals from the three input port blocks 250a-250c, and to forward signals from one of these three input port blocks, as selected by the control signal from the node controller 450, to the phase offset detector 313.

The detector 313 is connected to receive the input frame synchronization signal from the selection unit 343 as well as a feedback copy of the node synchronization signal that is outputted from the generator 348. The detector 313 will determine the phase difference between the node synchronization signal and the input frame synchronization signal, said difference being outputted as a difference value to the first sample-and-hold circuit 323 and to the subtracting circuit 324. The first sample-and-hold circuit 323 is in turn connected to sample the difference value from the detector 313 and to output a fixed difference value to the subtracting circuit 324. The sampled difference value is in the sample-and-hold circuit 323 used to update the outputted fixed difference value at timings determined by the control signal from the node controller 450. The subtracting circuit 324 is arranged to subtract the fixed difference value, outputted by the first sample-and-hold circuit 323, from the difference value outputted by the detector 313, and to output a resulting deviation to the low-pass filter 325, which m turn outputs a low-pass filtered deviation to the adding circuit 326.

The adding circuit 326 is arranged to add the low- pass filtered deviation, as outputted by the low-pass filter 325, to the output from the second sample-and-hold circuit 327, thereby to offset the low-pass filtered deviation to the extent defined by the output from the second sample-and-hold circuit 327, and to output the thus resulting offset deviation as a frequency control signal to the generator 348 and to the second sample-and- hold circuit 327. The second sample-and-hold circuit 327 is furthermore arranged to sample said offset deviation and to update its fixed output to correspond the offset deviation at timings determined by control signals from the node controller 450. The generator 348 is arranged to generate said node synchronization signal, having a frequency of approximately 8 kHz, as a function of the received control signal, i.e. the offset deviation. More specifically, the generator 348 in this example has the characteristics illustrated in the diagram of Fig. 3B. As shown m Fig. 3B, if the received frequency control signal is zero (0), the frequency of the outputted node synchronization signal will be approximately 8000 Hz. However, if the received frequency control signal increases to, lets say, two (2), the frequency of the outputted node synchronization signal will increase to approximately 8001 Hz. Similarly, if the received frequency control signal decreases to, lets say, minus two (-2), the frequency of the outputted node synchronization signal will decrease to approximately 7999 Hz.

The embodiment illustrated in Fig. 3A forms a feed- back loop that continuously strives to keep the differnce detected by the detector 313 locked to the fixed, "desired" difference output from the first sample-and- hold circuit 323 by the continuous adjustment of the output frame frequency of the generator 348. Any change in the signal from the detector 313 will result in a change in the input to the low-pass filter. Any DC deviation that is persistent over time will eventually be forwarded via the low pass filter 325 and the adding circuit 326 to the generator 348, and will then cause a small change in the frequency of the outputted node synchronization signal. This small change in frequency will act to slowly cancel the change in the signal from the detector 313.

To be noted, in a steady state situation, the frequ- ency control signal inputted to the generator 348 will reflect the actual frequency of the input synchronization signal that is currently forwarded by the selection unit 343, i.e. the actual frequency of the network. At repeated intervals, the node controller 450 will instruct the second sample-and-hold circuit 327 to incrementally/- decrementally update its output in accordance with the current output from the adding circuit 326. This updating of the output of the second sample-and-hold circuit 327 provides a means for "memorizing" the network frequency. Note however that such updatings are in this exemplified embodiment performed in small steps in order to not give rise to any sudden large changes in the frequency control signal input to the generator 348.

The fact that the steady-state DC control signal to the generator is provided as the sum of an offset signal and the low-pass filtered deviation from the low-pass filter 325 has the result of reducing any non-zero DC components in the deviation from the low-pass filter. The nominal DC input/output value of the loop filter 325 will thus be reduced from some arbitrary value forming the stability of the loop (in relation to the characteristics of the generator) into nominally zero.

In Fig. 2A, when a change of synchronization source is to take place, the node controller will instruct the selection unit 343 to forward another input synchronization signal to the detector 313. As soon as the difference between the new input synchronization signal and the node synchronization signal has been determined and outputted by the detector 313, the node controller 450 will instruct the first sample-and-hold circuit 323 to update its output with to this new difference. The new difference is thereby set as the new desired difference that the design will strive to maintain in relation to the new input synchronization signal. As is understood, the normalization of the difference, as performed by the subtracting unit 324, in conjunction with the use of the low-pass filter 325, provides for a smooth behavior of the node synchronization signal generated by the generator 348 when switching synchronization source.

Another exemplifying embodiment 300-B of the node synchronization block 300 shown in Fig. 1 will now be described with reference to Fig. 2B. The embodiment 300-B comprises essentially the same components as the one described with reference to Fig. 2A, the only difference being that the subtracting circuit 324 in Fig. 2B has been replaced by a delay circuit 328 in Fig. 2B. The purpose of the fifth embodiment 300-B of Fig. 2B is simply to exemplify that the components of the embodiment in Fig. 2A in Fig. 4, while forming a linear feedback system, may be positioned in relation to each other in several different ways while still implementing basic aspects of the design.

In Fig. 2B, instead of, as in Fig. 2A, normalizing the current difference value provided by the detector 313 in said subtracting circuit using the desired difference value provided by the sample-and-hold circuit 323 as norm, the feedback version of the node synchronization signal is delayed by the delay circuit 328 before it is detected by the detector 313. The delay inflicted by the delay circuit 328 is determined by, and is to correspond to, the difference value provided by the sample-and-hold circuit 323, thereby normalizing the detected difference in relation to the desired difference. As is understood, when updating the difference value hold by the first sample-and-hold circuit 323 according to a new desired difference as provided by the detector, that is when a switch of input to be used for synchronization is preformed, the delay inflicted by the delay circuit 328 upon the feedback version of the node synchronization signal has to be taken into consideration. Consequently, the former stored value of the sample-and-hold circuit 328 will only be adjusted in accordence with the current difference detected by tbe detector 313. The operation of the embodiment in Fig. 2A during a change of synchronization source will now be described in Fig. 3A. During normal operation, illustrated as period A in Fig. 3A, the input frame synchronization signal selected as synchronization source by the node controller 450, which in Fig. 3A is assumed to be the signal from input port block 250a, is use to phase lock the output of the generator 348. As illustrated in Fig. 3A, it is assumed that the phases has been locked at a phase difference represented by an difference count of 250. When a change of synchronization source is to take place, the node controller 450 will instruct the generator 348 to enter into a hold-over mode. The period of time during which the generator 348 is set to operate in hold-over mode is illustrated as period B in Fig. 3A. In hold-over mode, generator 348 will ignore any changes in its input control signal and will instead continue to generate the node synchronization signal according to the control signal input prior to the entering into the holdover mode. This control signal input is also, at the point of entering into the hold-over mode, locked into the second sample-and-hold circuit 327 as a new offset to be outputted to offset the signal from the low-pass filter 325.

At the same time as the generator 348 is set by the node controller 450 to operate in hold-over mode, the node controller also instructs the selection unit 343 to forward another input synchronization signal to the detector 313. In Fig. 3A it is assumed that the signal from input port block 250b is selected as the new synchronization source. The detector 313 will then start determining the phase difference between the node synch- ronization signal and the new input synchronization signal from block 250b and will transmit this difference, illustrated as difference counts 328 and 329 within period B in Fig. 3A, to the sample-and-hold circuit 323. After a short period of time, during which the sample- and-hold circuit 323 is arranged to sample the difference counts received by the detector 311, the node controller 450 will instruct the sample-and-hold circuit 323 to update its output using the averaged sampled difference, and hence lock said averaged difference as a new fixed differece output to the subtracting unit 324. In Fig. 3A, it is assumed that the so updated new fixed phase difference is represented by a phase difference count of 329.

Simultaneously, or more specifically very shortly thereafter, the node controller will instruct the generator 348 to return to normal mode, illustrated as period C in Fig. 3A. The generator will then resume controlling the frequency of the node synchronization signal in accordance with its control signal input. It is to be noted in Fig. 3A that the transitions from period A to period C takes place without causing any phase-shifts in the node synchronization signal to blocks 500a-500c. An embodiment 500 exemplifying the design of the output port blocks of the kind denoted 500a-500c in Fig. 1 will now be described with reference to Fig. 4. The embodiment 500 comprises a frame buffer 510, an output port 520, a phase offset detector 530, a phase offset control unit 540, and a phase offset generator 550.

As described above with reference to Fig. 1, and as illustrated in Fig. 4, the block 500 is connected to receive time slot data from the switch core 400, an input frame synchronization signal from a respective one of the input port blocks 250a-250c, a phase control signal (not shown in Fig. 1) from the node controller 450, and the node synchronization signal from block 300. Based upon the inputs, the block 500 is arranged to output frames. More specifically, the frame buffer 510 is connected to receive time slot data from the switch core and to store such time slot data prior to the transmission thereof from the output port 520. The output port 520 is in turn arranged to receive an output frame synchroniza- tion signal from the phase offset generator 550 and to transmit 125 μs frames of time slot data, as provided by the frame buffer, using said output frame synchronization signal to synchronize the transmission of the start of each frame. The phase offset detector 530 is connected to receive the input frame synchronization signal from the respective one of the input port blocks 250a-250c, as well as a feedback copy of the output frame synchronization signal from the phase offset generator 550. The detector 530 is arranged to determine the phase difference, i.e. phase offset, between the input frame synchronization signal and the output frame synchronization signal. Each determined offset is then outputted to the phase offset control unit 540. As illustrated in Fig. 4, the phase offset control unit 540 is connected to receive the phase offset from the detector 530, as well as the phase offset control signal from the node controller 450. As the phase offset represents the difference in time between the input frame synchronization signal and the output frame synchronization signal, it also will reflect the overall delay through the node in Fig. 1, i.e. the time that it takes for data to pass through the switch from the input port providing the input frame synchronization signal to the output port 520. The purpose of the control unit 540 is to compare the offset received from the detector 530 with a desired offset, representing a desired delay through the node, received as said phase offset control signal from the node controller 450. Based upon such a comparison, the control unit 540, typically implemented in software, will generate an output offset to the phase offset generator 550. Typically, if the offset received from the detector 530 is smaller than the selected offset indicated by the control signal from the node controller 450, i.e. if the delay through the node is smaller than desired, the control unit 540 will increment the offset outputted to the generator 550. On the other hand, if the offset received from the detector 530 is higher than the selected offset indicated by the control signal from the node controller 450, i.e. if the delay through the node is larger than desired, the control unit 540 will decrement the offset outputted to the generator 550.

The generator 550 is arranged to receive the node synchronization signal from block 300 and to add the offset received from the control unit 540 thereto, thereby adjusting the phase of the frame synchronization signal outputted from the generator 550 to provide for a desired delay through the node. The generator 550 may be a counter that starts at receptions of the node synchronization signal and that transmits the phase adjusted output frame synchronization signals at the point in time that the counter reaches the a count defined by the offset signal input from the control unit 540. The so phase-adjusted output frame synchronization signal from the generator 550 is then provided to the detector 530 and to the output port 520, which will transmit frames of data based thereupon as described above .

Consequently, the function of the detector 530, the control unit 540, and the offset generator 550 is to adjust the transmission of the output frame synchronization signal to provide for a desired delay through the node. Furthermore, as the output frame synchronization signal is generated using the node synchronization signal as reference, the latter having been generated as described above to be essentially phase shift free irrespective of any change of input frame synchronization signal to be used as synchronization source, an essentially continuous behavior of the output frame synchronization signal is ensured.

Even though exemplifying embodiments of the invention have been described in detail above with reference to the accompanying drawings, different modifications, combinations and alterations thereof may be made within the scope of the invention, which is defined by the accompanying claims.

Claims

1. A method for synchronizing operation at a node of a communication network, said method comprising: receiving two or more input frame synchronization signals ; selecting one of said two or more frame synchronization signal to be used as a current reference for frame synchronization; generating a node synchronization signal having a frame freqency that is controlled by a frame frequency control signal; providing a difference signal representing a current difference between a desired frame phase difference and the frame phase difference between a feedback version of said node synchronization signal and the selected input frame synchronization signal that is used as the current reference for frame synchronization; low pass filtering said difference signal to provide a low pass filtered difference signal; and offseting said low pass filtered difference signal according to an offset signal, thereby to form said frame frequency control signal.

2. A method as claimed in claim 1, further comprising controlling said offset signal so as to correspond to a steady state component of said frame frequency control signal, thereby to bring a steady state component of said low pass control signal to zero and thus to accomo- date for performing said low pass filtering at a zero DC level .

3. A method as claimed in claim 1 or 2, further comprising monitoring the frame frequency control signal and, continuously or at selected timings, updating said offset signal to correspond to a DC component of the monitored frame frequeny control signal.

4. A method as claimed in claim 1, 2, or 3, said offset signal being updated when switching from using one of said input frame synchronization signals into using another one of said input frame synchronization signals as reference for synchronization.

5. A method as claimed in any one of the preceding claims, further comprising switching, when so required, into using another one of said input frame synchronization signals as reference for synchronization

6. A method as claimed in claim 5, said switching step including: determining a frame phase difference between a feedback version of said node synchronization signal and said another one of said input frame synchronization signals . updating said desired frame phase difference so as to correspond to the so determined frame phase difference .

7. A method as claimed in claim 5 or 6, comprising setting said desired frame phase difference so as to form an essentially fixed value inbetween changes of input frame synchronization signal to be used as reference for synchronization.

8. A method as claimed in any one of claims 1-6, comprising adjusting said desired frame phase difference inbetween changes of input frame synchronization signal to be used as reference for synchronization, thereby to adjust the frame phase difference between said node synchronization signal and the input frame synchroniza- tion signal currently being used as reference for synchronization .

9. A method as claimed in any one of the preceding steps, said step of generating a node synchronization signal being performed so as to maintain an essentially phase-shift free node synchronization signal.

10. A method as claimed in any one of the preceding claims, comprising the step of entering into a hold-over mode, prior to the effectuation of said switching into using another input frame synchronization signal refer- ence for synchronization, during which said node synchronization signal is generated based at least upon said offset signal.

11. A method as claimed in any one of the preceding claims, comprising transmitting two or more output frame synchronization signals and synchronizing the transmission of said output frame synchronization signals using said node synchronization signal as reference in such a way that each one of said output frame synchronization signals shows a respective phase difference, in relation to said node synchronization signal, that is permissible to be controlled individually for each respective output frame synchronization signal.

12. A method as claimed in claim 11, said each one of said output frame synchronization signals being controlled to show a respective phase difference in relation to said node synchronization signal so as to control the frame phase difference between said two or more input frame synchronization signals and the two or more respective output frame synchronization signals.

13. An apparatus for synchronizing operation at a node of a communication network, said apparatus comprising: selector means (343) for selecting one of two or more input frame synchronization signals to be used as a current reference for frame synchronization; generator means (348) for providing a node synchronization signal having a frame freqency that is controlled by a frame frequency control signal; first control means (323) for providing a signal that represents a desired frame phase difference; comparator means (313, 324; 313, 328) for providing a difference signal that represents a current difference between said desired frame phase difference and the frame phase difference between said feedback version of said node synchronization signal and the input frame synchronization signal currently selected by said selecting means; filtering means (325) for low-pass filtering said difference signal to provide a low pass filtered difference signal; second control means (327) for providing an offset signal; and means (326) for offseting said low pass filtered difference signal according to said offset signal so as to define said frame frequency control signal that is provided to said generator means.

14. An apparatus as claimed in claim 13, said comparator means comprising: means (313) determining a frame phase difference between said feedback version of said node synchronization signal and said input frame synchronization signal currently selected by said selecting means; and means (324) determining a difference betweeen said frame phase difference and said desired frame phase difference .

15. An apparatus as claimed in claim 13 or 14, said second control means (327) defining said offset signal so as to correspond to a steady state component of said frame frequency control signal, thereby to bring a steady state component of said low pass filtered difference signal to zero and thus to accomodate having said filtering means (325) operate at a zero DC level.

16. An apparatus as claimed in claim 15, said second control means (327) monitoring the frame frequency control signal and, continuously or at selected timings, updating said offset signal to correspond to a DC component of the monitored frame frequeny control signal.

17. An apparatus as claimed in claim 15 or 16, said control means (327) updating said offset signal in the context of said selector means (343) selecting another one of said two or more input frame synchronization signals to be used as a current reference for frame synchronization.

18. An apparatus as claimed in any one of claims 13-

17, said first control means (323) being arranged, in the context of said selector means (343) selecting another one of said two or more input frame synchronization signals to be used as a current reference for frame synchr- nization, to determe a frame phase difference between said feedback version of said node synchronization signal and said another one of said input frame synchronization signals and to updating said signal representing a desired frame phase difference so as to correspond to the so determined frame phase difference.

19. An apparatus as claimed in any one of claims 13-

18, said generator means (348) being arranged to generate an essentially phase-shift free node synchronization signal .

20. An apparatus as claimed in any one of claims 13- 19, comprising: output means (500) for transmitting two or more output frame synchronization signals, said output means including phase adjustment means (450, 550) for synchronizing the transmission of said output frame synchronization signals using said node synchronization signal as reference in such a way that each one of said output frame synchronization signals shows a respective phase difference, in relation to said node synchronization signal, that is permissible to be controlled individually for each respective output frame synchronization signal.

21. An apparatus as claimed in claim 20, said output means (500) including means (250) for determining the respective frame phase difference between said two or more input frame synchronization signals and the two or more respective output frame synchronization signals and, based thereupon, controlling said phase adjustment means to adjust the phase of the respective output frame synchronization signals accordingly.