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WO2000069108A1 - Procede et dispositif de synchronisation - Google Patents

Procede et dispositif de synchronisation Download PDF

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Publication number
WO2000069108A1
WO2000069108A1 PCT/SE2000/000874 SE0000874W WO0069108A1 WO 2000069108 A1 WO2000069108 A1 WO 2000069108A1 SE 0000874 W SE0000874 W SE 0000874W WO 0069108 A1 WO0069108 A1 WO 0069108A1
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WO
WIPO (PCT)
Prior art keywords
signal
frame
node
synchronization
phase difference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SE2000/000874
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English (en)
Inventor
Christer Bohm
Bengt J. Olsson
Magnus Danielson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Net Insight AB
Original Assignee
Net Insight AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Net Insight AB filed Critical Net Insight AB
Priority to AU47921/00A priority Critical patent/AU4792100A/en
Publication of WO2000069108A1 publication Critical patent/WO2000069108A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Definitions

  • the present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network.
  • each node has its own direct connection to this common synchronization source, which is thereby connected to directly synchronize the operation at each node of the network.
  • synchronization is forwarded from the common synchronization source through the network to reach all network nodes in a top-down manner, forming a so-called synchronization spanning-tree within the network.
  • each output port of a node is typically strictly synchronized according to synchronization signals received at an input port of the node.
  • a node may furthermore be required to operate in relation to links that may not be exactly in phase, to handle occasional phase variations, and to keeping phase variations within acceptable limits.
  • phase distortions such as jitter and wander caused by different components showing different delays, different temperature dependencies, alignment jitters, quantization noise, and the like.
  • An object of the invention is therefore to provide a simple and effective way of forwarding synchronization throught a node while limiting the effect caused by different components showing different characteristics.
  • Another object of the invention is to proide a solution that decreases the amount of phase deviations caused by the above mentioned and similar effects, thereby increasing the quality of synchronization within the network.
  • two or more input frame synchronization signals are received and one of them is selected to be used as a current reference for frame synchronization.
  • a node synchronization signal is generated to have a frame freqency that is controlled by a frame frequency control signal.
  • a difference signal is provided to represent a current difference between a desired frame phase difference and the frame phase difference between a feedback version of said node synchronization signal and the selected input frame synchronization signal that is used as the current reference for frame synchronization.
  • Said difference signal is low pass filtered, and the low pass filtered signal is then offset according to an offset signal, thereby to form said frame frequency control signal.
  • the precense of a non-zero steady state DC offset of the input/output signals of a low-pass loop filter limits the freedom of implementation of the loop filter and the possibilities of adjusting loop filter characteristics, which for example is desirable in order to accomodate for characteristics of other parts of the node design, thereby requiring complex loop filter designs.
  • the steady-state control signal to the generator is provided according to the invention as the sum of an offset signal and the low-pass filtered signal from the low-pass filter has the effect of reducing any steady-state non-zero DC components in the signal treated by the low-pass filter performing the low-pass filtering.
  • the nominal steady-state input/output signal handled by the low-pass loop filter may thus be reduced from some arbitrary value forming the stability of the loop (in relation to the characteristics of the generator) into nominally zero.
  • the loop filter characteristics using the invention, can be ajdusted at a zero stady-state DC signal level, the implementation of the loop filter may be simplified and so may the components and methods used for adjusting the loop filter characteristics .
  • the frequ- ency control signal i.e. the used offset signal
  • the offset signal thus also provides a means for "memorizing" the network frequency.
  • Another advantage of the invention is that it ensures phase continuity in the distributed frame frequency during switches of synchronization input signal.
  • the amount of frame phase distortions caused by, for example, alignment jitters and the like originating from changes in the selection of synchronization source will be redu- ced.
  • a node will have the ability to make sure that the synchronization signal that it distributed to downstream nodes will remain continuous and essentially phase-shift free when the node is required to switch from using one input signal into using to another as reference for synchronization.
  • the node synchronization signal may as such be distributed to downstream nodes as an output frame synch- ronization signal of the node.
  • the phase-shift free node synchronization signal is used to synchronize transmission of two or more output frame synchronization signals. Preferably, this is performed in such a way that each one of said output frame synchronization signals is controlled to show a respective phase, in relation to the node synchronization signal, that is permissible to be controlled individually for each respective output frame synchronization signal, thereby accomodating for having different phases on different output links, and to adjucting the delays with respect to different input/output ports individually.
  • This embodiment has the advantage of allowing different phase situations to exist simultaneously at different ports of a node.
  • phase-shift herein refers to the situation wherein an essential discontinuity, or "jump”, occurs or is generated in the phase of a signal if not desired, however not excluding the possibility of allowing the phase to be gradually and in a continuous manner be adjusted over time as desired.
  • each frame synchronization signal may show a limited jitter and may be arbitrarily located in phase in relation to other frame synchronization signals, but may not show any persistent frame drift in relation to other frame synchronization signals.
  • the invention is primarily conserned with the propagation of synchronization on a frame level, however not being limited thereto.
  • means for providing synchronization on a bit or slot level, while synchronizing a bit frequency and/or a slot frequency, could be added as well.
  • a nominal bit frequency will be generated individually by each node for and will thus essentially not be propagated through the network.
  • a frame synchronization signal is prefer- rably, but not necessarily, a so-called start of frame signal that designates the start of a frame on a link and that is transmitted tomultiple the frame on said link.
  • the node synchronization signal could for example also, but not necessarily, be regarded as a frame start signal, although in many situations it need not itself designate the actual start of frames.
  • the invention is contemplated for use in a DTM- network. Further information on the basics of DTM technology is found in "The DTM Gigabit Network", Christer Bohm, Per Lindgren, Lars Ramfelt, and Peter Sj ⁇ din, Journal of High Speed Networks, 3 (2 ): 109-126, 1994, and "Multi-gigabit networking based on DTM", Lars Gauffin, Lars Hakansson, and Bjorn Pehrson, Computer networks and ISDN Systems, 24 (2 ): 119-139, April 1992.
  • Fig. 1 schematically shows a network node according to an embodiment of the invention
  • FIGs. 2A and 2B schematically show respective exem- plifying embodiments of the node synchronization block shown in Fig. 1;
  • Fig. 3A shows a time diagram illustrating the operation of the node synchronization block shown in Fig. 1;
  • Fig. 3B shows exemplifying characteristics of the generator of the node synchronization block illustrated in Figs. 3A and 3B;
  • Fig. 4 schematically shows an exemplifying embodiment of the output port blocks shown in Fig. 1.
  • Fig. 1 schematically shows a network node 200 that comprises three input port blocks 250a-250c, a node synchronization block 300, a switch core 400, a node controller 450, and three output port blocks 500a-500c.
  • Each one of the input port blocks 250a-250c is arranged to receive regularly occurring frames of data, divided into time slots, from respective input links.
  • the location of each frame on the respective link is identified by an input frame synchronization signal, also being referred to as a frame start signal while being located in the stream of data to mark the beginning of each frame, which is carried along with the frames on the respective link.
  • an input frame synchronization signal also being referred to as a frame start signal while being located in the stream of data to mark the beginning of each frame, which is carried along with the frames on the respective link.
  • the frame frequency is nominally 8 kHz, corresponding to a frame length of 125 ⁇ s . Consequently, the frame synchro- nization signal of each respective link will be nominally received each 125 ⁇ s at the respective input port block.
  • Each input port block 250a-250c is arranged to derive data from time slots of received frames and to transmit such slot data to the switch core 400. Also, each input port block 250a-250c is arranged to derive the respective input frame synchronization signal from the respective input stream of data and to transmit said signal to the node synchronization block 300 and to a respective output port block 500a-500c.
  • the switch core 400 is arranged to switch slots of data from the input port blocks 250a-250c to the output port blocks 500a-500c in accordance with switching instructions defined by the node controller 450.
  • the switch core 400 is arranged to switch slots of data received in one or more control channels at the input port blocks 250a-250c from the input port blocks 250a-250c to the node controller 450, and to switch time slots of data to be transmitted in one or more control channels at the output port blocks 500a-500c from the node controller 450 to the output port blocks 500a-500c.
  • Data received/transmitted in said control channels from/to other nodes of the network will typically include channel management information. Based upon such channel management information, the node controller 450 will provide the switch core 400 with said switching instructions . Data received/transmitted in said control channels may for example include synchronization messages which are evaluated by the node controller 450 and based on which it will select which input link, i.e. which input frame synchronization signal, that is to be used as synchronization source for synchronizing of the operation of the node 200.
  • the node controller 450 is connected to provide the node synchronization block 300 with a synchronization selection signal that identifies which input frame synchronization signal to use as synchronization source, the timing at which a switch to using another frame synchronization signal as synchronization source is to take place, and similar related information.
  • the node synchronization block 300 is connected to receive the input frame synchronization signals from the respective input port blocks 250a-250c and the synchronization selection signal from the node controller 450. Based upon these signals, the node synchronization block 300 is arranged to generate a node internal frame synch- ronization signal, also referred to below as node synchronization signal.
  • the node synchronization signal is generated to have a continuous phase, i.e. to be essenti- ally phase-shift free, which means that a change of synchronization source for generating said node synchronization signal will not as such cause any essential discontinuities or phase-shifts in the node synchronization signal.
  • the node syncnronization signal generated by the node synchronization block is transmitted to each one of the output port blocks 500a-500c. Examples on how the phase-shift free node synchronization signal is generated by the node synchronization block 300 will be described in detail below with reference to Figs. 2A and 2B.
  • Each one of the output port blocks 500a-500c typically receives data in slots from the switch core 400, input frame synchronization signals from a respective input port block 250a-250c, and the node synchronization signal from the node synchronization block 300.
  • each output port will generate a respective output frame synchronization signal and will transmit said output frame synchronization signal as a frame start signal along with frames of time slot data received from the switch core 400 on a respective output link.
  • input port block 250a and output port block 500a could typically be configured as together forming a first input/output interface
  • input port block 250b and output port block 500b would be configured as together forming a second input/output interface
  • input port block 250c and output port block 500c would be configured as together forming a third input/output interface.
  • Each interface would then optionally be connected to provide read and write access to a respective point-to-point link, or to a respective unidirectional bus, wherein frames of slots received at, for example, the input port 250a would be switched essentially as a whole by the switch core 400 to be transmitted essentially unaffected, with the exemption of specific slots being switch to/from other ports, at output port 500a.
  • the embodiment 300-A comprises a selection unit 343, a phase offset detector 313, a first sample-and-hold circuit 323, a subtracting circuit 324, a low-pass filter 325, an adding circuit 326, a second sample-and-hold circuit 327, and a node synchronization signal generator 348.
  • the block 300-A is connected to receive input frame synchronization signals from all input port blocks 250a- 250c.
  • the block 300-A is moreover arranged to generate a phase-shift free node synchronization signal based thereupon, as controlled by control signals from the node controller 450, and to output this node synchronization signal to the output port blocks 500a-500c.
  • the selection unit 343 is connected to receive the input frame synchronization signals from the three input port blocks 250a-250c, and to forward signals from one of these three input port blocks, as selected by the control signal from the node controller 450, to the phase offset detector 313.
  • the detector 313 is connected to receive the input frame synchronization signal from the selection unit 343 as well as a feedback copy of the node synchronization signal that is outputted from the generator 348.
  • the detector 313 will determine the phase difference between the node synchronization signal and the input frame synchronization signal, said difference being outputted as a difference value to the first sample-and-hold circuit 323 and to the subtracting circuit 324.
  • the first sample-and-hold circuit 323 is in turn connected to sample the difference value from the detector 313 and to output a fixed difference value to the subtracting circuit 324.
  • the sampled difference value is in the sample-and-hold circuit 323 used to update the outputted fixed difference value at timings determined by the control signal from the node controller 450.
  • the subtracting circuit 324 is arranged to subtract the fixed difference value, outputted by the first sample-and-hold circuit 323, from the difference value outputted by the detector 313, and to output a resulting deviation to the low-pass filter 325, which m turn outputs a low-pass filtered deviation to the adding circuit 326.
  • the adding circuit 326 is arranged to add the low- pass filtered deviation, as outputted by the low-pass filter 325, to the output from the second sample-and-hold circuit 327, thereby to offset the low-pass filtered deviation to the extent defined by the output from the second sample-and-hold circuit 327, and to output the thus resulting offset deviation as a frequency control signal to the generator 348 and to the second sample-and- hold circuit 327.
  • the second sample-and-hold circuit 327 is furthermore arranged to sample said offset deviation and to update its fixed output to correspond the offset deviation at timings determined by control signals from the node controller 450.
  • the generator 348 is arranged to generate said node synchronization signal, having a frequency of approximately 8 kHz, as a function of the received control signal, i.e. the offset deviation. More specifically, the generator 348 in this example has the characteristics illustrated in the diagram of Fig. 3B. As shown m Fig. 3B, if the received frequency control signal is zero (0), the frequency of the outputted node synchronization signal will be approximately 8000 Hz. However, if the received frequency control signal increases to, lets say, two (2), the frequency of the outputted node synchronization signal will increase to approximately 8001 Hz. Similarly, if the received frequency control signal decreases to, lets say, minus two (-2), the frequency of the outputted node synchronization signal will decrease to approximately 7999 Hz.
  • the embodiment illustrated in Fig. 3A forms a feed- back loop that continuously strives to keep the differnce detected by the detector 313 locked to the fixed, "desired" difference output from the first sample-and- hold circuit 323 by the continuous adjustment of the output frame frequency of the generator 348.
  • Any change in the signal from the detector 313 will result in a change in the input to the low-pass filter.
  • Any DC deviation that is persistent over time will eventually be forwarded via the low pass filter 325 and the adding circuit 326 to the generator 348, and will then cause a small change in the frequency of the outputted node synchronization signal. This small change in frequency will act to slowly cancel the change in the signal from the detector 313.
  • the frequ- ency control signal inputted to the generator 348 will reflect the actual frequency of the input synchronization signal that is currently forwarded by the selection unit 343, i.e. the actual frequency of the network.
  • the node controller 450 will instruct the second sample-and-hold circuit 327 to incrementally/- decrementally update its output in accordance with the current output from the adding circuit 326.
  • This updating of the output of the second sample-and-hold circuit 327 provides a means for "memorizing" the network frequency. Note however that such updatings are in this exemplified embodiment performed in small steps in order to not give rise to any sudden large changes in the frequency control signal input to the generator 348.
  • the fact that the steady-state DC control signal to the generator is provided as the sum of an offset signal and the low-pass filtered deviation from the low-pass filter 325 has the result of reducing any non-zero DC components in the deviation from the low-pass filter.
  • the nominal DC input/output value of the loop filter 325 will thus be reduced from some arbitrary value forming the stability of the loop (in relation to the characteristics of the generator) into nominally zero.
  • the node controller when a change of synchronization source is to take place, the node controller will instruct the selection unit 343 to forward another input synchronization signal to the detector 313. As soon as the difference between the new input synchronization signal and the node synchronization signal has been determined and outputted by the detector 313, the node controller 450 will instruct the first sample-and-hold circuit 323 to update its output with to this new difference. The new difference is thereby set as the new desired difference that the design will strive to maintain in relation to the new input synchronization signal. As is understood, the normalization of the difference, as performed by the subtracting unit 324, in conjunction with the use of the low-pass filter 325, provides for a smooth behavior of the node synchronization signal generated by the generator 348 when switching synchronization source.
  • FIG. 2B Another exemplifying embodiment 300-B of the node synchronization block 300 shown in Fig. 1 will now be described with reference to Fig. 2B.
  • the embodiment 300-B comprises essentially the same components as the one described with reference to Fig. 2A, the only difference being that the subtracting circuit 324 in Fig. 2B has been replaced by a delay circuit 328 in Fig. 2B.
  • the purpose of the fifth embodiment 300-B of Fig. 2B is simply to exemplify that the components of the embodiment in Fig. 2A in Fig. 4, while forming a linear feedback system, may be positioned in relation to each other in several different ways while still implementing basic aspects of the design.
  • Fig. 2B instead of, as in Fig. 2A, normalizing the current difference value provided by the detector 313 in said subtracting circuit using the desired difference value provided by the sample-and-hold circuit 323 as norm, the feedback version of the node synchronization signal is delayed by the delay circuit 328 before it is detected by the detector 313.
  • the delay inflicted by the delay circuit 328 is determined by, and is to correspond to, the difference value provided by the sample-and-hold circuit 323, thereby normalizing the detected difference in relation to the desired difference.
  • the input frame synchronization signal selected as synchronization source by the node controller 450 which in Fig. 3A is assumed to be the signal from input port block 250a, is use to phase lock the output of the generator 348. As illustrated in Fig. 3A, it is assumed that the phases has been locked at a phase difference represented by an difference count of 250.
  • the node controller 450 will instruct the generator 348 to enter into a hold-over mode. The period of time during which the generator 348 is set to operate in hold-over mode is illustrated as period B in Fig. 3A.
  • generator 348 will ignore any changes in its input control signal and will instead continue to generate the node synchronization signal according to the control signal input prior to the entering into the holdover mode.
  • This control signal input is also, at the point of entering into the hold-over mode, locked into the second sample-and-hold circuit 327 as a new offset to be outputted to offset the signal from the low-pass filter 325.
  • the node controller 450 also instructs the selection unit 343 to forward another input synchronization signal to the detector 313.
  • the signal from input port block 250b is selected as the new synchronization source.
  • the detector 313 will then start determining the phase difference between the node synch- ronization signal and the new input synchronization signal from block 250b and will transmit this difference, illustrated as difference counts 328 and 329 within period B in Fig. 3A, to the sample-and-hold circuit 323.
  • the node controller 450 will instruct the sample-and-hold circuit 323 to update its output using the averaged sampled difference, and hence lock said averaged difference as a new fixed differece output to the subtracting unit 324.
  • Fig. 3A it is assumed that the so updated new fixed phase difference is represented by a phase difference count of 329.
  • the node controller will instruct the generator 348 to return to normal mode, illustrated as period C in Fig. 3A.
  • the generator will then resume controlling the frequency of the node synchronization signal in accordance with its control signal input. It is to be noted in Fig. 3A that the transitions from period A to period C takes place without causing any phase-shifts in the node synchronization signal to blocks 500a-500c.
  • An embodiment 500 exemplifying the design of the output port blocks of the kind denoted 500a-500c in Fig. 1 will now be described with reference to Fig. 4.
  • the embodiment 500 comprises a frame buffer 510, an output port 520, a phase offset detector 530, a phase offset control unit 540, and a phase offset generator 550.
  • the block 500 is connected to receive time slot data from the switch core 400, an input frame synchronization signal from a respective one of the input port blocks 250a-250c, a phase control signal (not shown in Fig. 1) from the node controller 450, and the node synchronization signal from block 300. Based upon the inputs, the block 500 is arranged to output frames. More specifically, the frame buffer 510 is connected to receive time slot data from the switch core and to store such time slot data prior to the transmission thereof from the output port 520.
  • the output port 520 is in turn arranged to receive an output frame synchroniza- tion signal from the phase offset generator 550 and to transmit 125 ⁇ s frames of time slot data, as provided by the frame buffer, using said output frame synchronization signal to synchronize the transmission of the start of each frame.
  • the phase offset detector 530 is connected to receive the input frame synchronization signal from the respective one of the input port blocks 250a-250c, as well as a feedback copy of the output frame synchronization signal from the phase offset generator 550.
  • the detector 530 is arranged to determine the phase difference, i.e. phase offset, between the input frame synchronization signal and the output frame synchronization signal. Each determined offset is then outputted to the phase offset control unit 540. As illustrated in Fig.
  • the phase offset control unit 540 is connected to receive the phase offset from the detector 530, as well as the phase offset control signal from the node controller 450.
  • the phase offset represents the difference in time between the input frame synchronization signal and the output frame synchronization signal, it also will reflect the overall delay through the node in Fig. 1, i.e. the time that it takes for data to pass through the switch from the input port providing the input frame synchronization signal to the output port 520.
  • the purpose of the control unit 540 is to compare the offset received from the detector 530 with a desired offset, representing a desired delay through the node, received as said phase offset control signal from the node controller 450.
  • the control unit 540 will generate an output offset to the phase offset generator 550.
  • the control unit 540 will increment the offset outputted to the generator 550.
  • the control unit 540 will decrement the offset outputted to the generator 550.
  • the generator 550 is arranged to receive the node synchronization signal from block 300 and to add the offset received from the control unit 540 thereto, thereby adjusting the phase of the frame synchronization signal outputted from the generator 550 to provide for a desired delay through the node.
  • the generator 550 may be a counter that starts at receptions of the node synchronization signal and that transmits the phase adjusted output frame synchronization signals at the point in time that the counter reaches the a count defined by the offset signal input from the control unit 540.
  • the so phase-adjusted output frame synchronization signal from the generator 550 is then provided to the detector 530 and to the output port 520, which will transmit frames of data based thereupon as described above .
  • the function of the detector 530, the control unit 540, and the offset generator 550 is to adjust the transmission of the output frame synchronization signal to provide for a desired delay through the node. Furthermore, as the output frame synchronization signal is generated using the node synchronization signal as reference, the latter having been generated as described above to be essentially phase shift free irrespective of any change of input frame synchronization signal to be used as synchronization source, an essentially continuous behavior of the output frame synchronization signal is ensured.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

La présente invention concerne un procédé et un dispositif synchronisation s'adressant à la mise en oeuvre d'un noeud de réseau de communication. Selon l'invention, à la réception d'au moins deux signaux de synchronisation, on choisit l'un de ces signaux qui va servir de référence courante pour la synchronisation de trame. On génère un signal de synchronisation de noeud de façon que la fréquence de trame soit régie par un signal de commande de fréquence de trame. On utilise un signal différentiel qui vient représenter une différence courante entre un déphasage de trame attendu et le déphasage de trame entre la version en retour dudit signal de synchronisation de noeud et le signal de synchronisation de trame d'entrée choisi pour servir de référence courante de la synchronisation de trame. Après un traitement par un filtre passe-bas et un filtre passe-haut, le signal différentiel subit un décalage conformément à un signal de décalage, ce qui permet de former le signal de commande de fréquence de trame.
PCT/SE2000/000874 1999-05-06 2000-05-04 Procede et dispositif de synchronisation Ceased WO2000069108A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU47921/00A AU4792100A (en) 1999-05-06 2000-05-04 Synchronization method and apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9901655A SE9901655L (sv) 1999-05-06 1999-05-06 Synkroniseringsförfarande och -anordning
SE9901655-2 1999-05-06

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WO2000069108A1 true WO2000069108A1 (fr) 2000-11-16

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511859A (en) * 1982-08-30 1985-04-16 At&T Bell Laboratories Apparatus for generating a common output signal as a function of any of a plurality of diverse input signals
US4672299A (en) * 1986-05-23 1987-06-09 American Telephone And Telegraph Co. Clock control circuit for phase control
US4736393A (en) * 1986-04-16 1988-04-05 American Telephone And Telegraph Co., At&T Information Systems, Inc. Distributed timing control for a distributed digital communication system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511859A (en) * 1982-08-30 1985-04-16 At&T Bell Laboratories Apparatus for generating a common output signal as a function of any of a plurality of diverse input signals
US4736393A (en) * 1986-04-16 1988-04-05 American Telephone And Telegraph Co., At&T Information Systems, Inc. Distributed timing control for a distributed digital communication system
US4672299A (en) * 1986-05-23 1987-06-09 American Telephone And Telegraph Co. Clock control circuit for phase control

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SE9901655L (sv) 2001-01-03
AU4792100A (en) 2000-11-21
SE9901655D0 (sv) 1999-05-06

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