WO2000069106A1

WO2000069106A1 - Synchronization method and apparatus

Info

Publication number: WO2000069106A1
Application number: PCT/SE2000/000872
Authority: WO
Inventors: Christer Bohm; Bengt J. Olsson; Magnus Danielson
Original assignee: Net Insight AB
Current assignee: Net Insight AB
Priority date: 1999-05-06
Filing date: 2000-05-04
Publication date: 2000-11-16
Anticipated expiration: 2001-11-06
Also published as: AU4791900A

Abstract

The present invention refers to a method and an apparatus for synchronizing operation in a communication network of the kind wherein the physical node-to-neighbor-node links of the network are combined into forming logical multi-access unidirectional links, on each of which data is transferred in a recurrent frame that is defined by a frame synchronization signal on the link and that is forwarded downstream on the link by the nodes attached to the link. According to the invention, a frame synchronization distribution spanning tree is defined for said network so as to span said network by regarding the network in terms of node-to-neighbor-node physical links branches, not by default limiting the structure of said spanning tree to follow the structure of said network in terms of it's logical multi-access unidirectional links.

Description

SYNCHRONIZATION METHOD AND APPARATUS

Technical Field of Invention

The present invention refers to a method and an apparatus for synchronizing operation at a node of a communication network, more specifically to a network in which the physical node-to-neighbor-node links of the network are combined into forming logical multi-access unidirectional links, on each of which data is transferred, preferably in a time division multiplexed manner, in a recurrent frame that is defined by a frame synchroniza- tion signal on the link and that is forwarded downstream on the link by the nodes attached to the link.

Background of the Invention

In all communication networks, an essential task to be addressed is how to synchronize the operation of the network and of the different equipment and components that form part of the network. Prior art provides many different approaches to address this task.

In most synchronous systems, the operation of the entire network is strictly synchronized to a common, master synchronization source. Generally, a number of redundant synchronization sources are also provided to take over the role as master synchronization source if a failure at a link or a node or at the master synchroniza- tion source itself temporarily prevents the use of the master synchronization source as reference for synchronization.

A more preferred approach for providing all nodes with the same frame frequency is to forward synchroniza- tion from the common synchronization source through the network to reach all network nodes in a top-down manner, forming a so-called synchronization spanning-tree within the network.

For example, European Patent Application EP 0522607 (Gauffin et al . ) discloses such a method for propagating cyclic frame synchronization on busses in a top-down manner in an environment similar to the one address by the invention.

A general problem statement with respect to using a spanning-tree approach of the kind disclosed for example in the above mentioned patent application, is how to define the synchronization hierarchy in an efficient manner, how maintaining a high quality of synchronization while accommodating for the fact that a node can be connected to different links being out of phase with each other, and how this situation is handle during normal operation and during switch when using a new source input as reference for synchronization.

An object of the invention is therefore to address the above mentioned problem in order to provide a solution that allows for the synchronization spanning- tree to be defined in an efficient manner, providing for stable phase operation, low delays and good jitter performance in multi-link scenarios.

Summary of the Invention

The above mentioned objects are achieved by the invention as defined in the accompanying claims.

According to the invention, a frame synchronization distribution spanning tree for a network of the kind mentioned in the introduction is defined so as to span said network by regarding the network in terms of node- to-neighbor-node physical links branches, and not by default limiting the structure of said spanning tree to follow the structure of said network in terms of it's logical multi-access unidirectional links as such.

An advantage of the invention is that it makes it possible to define a synchronization spanning tree without having to consider how the physical links of the net- work are configured into forming logical unidirectional multi-access links. This allows for simpler implementation of the spanning-tree defining algorithm. Further- more, as frame synchronization need not as such follow the path of the logical multi-access links (or busses) , the spanning tree can be defined so as to provide a best possible quality of synchronization at each node, for example by minimizing the number of hops between each node and the current best clock reference source, thereby for example reducing the jitter effects produced by each node forwarding the frame frequency.

To be noted, as comparison to the above, prior art solution such as the one disclosed in the above mentioned patent application is based upon having a frame start signal propagated along multi-access links from head end node to terminating end node on each link, the structure of the synchronization spanning-tree thus being limited to follow the structure of the unidirectional logical multi-access links (busses or rings) of the network in a top-down manner.

According to an embodiment of the invention, the defining of the frame synchronization spanning tree is performed using a message-based, distributed scheme for determining synchronization hierarchy.

An advantage with this embodiment is that the nodes are enabled to define the synchronization spanning-tree on their own, i.e. without the need for network operator interaction.

Each individual node will transmit and receive synchronization information in synchronization messages to/from other nodes and will then select which one of its input links to synchronize its operation to based upon such synchronization information that it receives from other nodes. Examples on systems that employ message- based synchronization schemes are for example found in U.S. Pat. No. 2,986,723 and in "Clock Source Selection Method in Distributed Communication System Networks", Rogers, IBM Technical Disclosure Bulletin, Vol. 25, No 118, Apr. 1983, pp. 6293-6298. Another advantage of the invention according to this embodiment is that the message-based, distributed scheme for determining synchronization hierarchy need not by default deal with how the physical links are configured to form shared multi-access links, but may instead operate based on more simple node-to-neighbor-node connectivity aspects, thereby simplifying implementations and providing for quicker operation.

According to another embodiment of the invention, it is determined, at a node of the network, which input port the node shall use as reference for frame frequency synchronizing transmissions of frame synchronization signals from said output port using the determined synchronization distribution spanning tree. However, the frame phase to apply when transmitting said frame synchronization signals from said output port is determined by regarding whether or not the physical link connected to said output port forms part of a logical multi-access link and if so selecting said frame phase considering the frame phase on said logical multi-access link. Thus, in other words, while the frame frequency of the output signal is generated using the best reference signal as reference, the frame phase of the output signal is adjusted so as to preferably keep a low delay with respect to input/output port interface connected to a multi-access link. Thus, whereas frame frequency is propagated according to the frame synchronization spanning tree, frame phase can still be propagated following the logical unidirectional multi-access links of the networks as found in prior art solutions, thereby to keep a low delay when forwarding data along a link, with possible a higher delay switching data from one link to another.

For example, when an input/output port combination is connected to a unidirectional communication bus in the above-mentioned manner, it generally preferred that the delay, i.e. the time period between the point in time when a time slot is received at the input port and when it is transmitted from the output port, is as low as possible. However, a low delay typically implies the use of very low fill levels in buffers that are typically used at said ports for temporarily storing said data. Consequently, if a small fluctuation in synchronization rates or in data forwarding mechanisms occurs, there is a risk that said buffers will run empty, which may have the effect that there is no valid data available for transmission when transmission is due. Therefore, a certain level of buffering is preferred. Consequently, the difference in time between the reception of the input frame synchronization signal and the transmission of the output frame synchronization signal should not be too low. Whether needed as a result of these or other considerations, the invention provides a very simple solution for controlling the delay as desired.

According to an embodiment of the invention, this is accomplished by generating a preferably phase-shift free node common frame synchronization signal based upon the frequency input currently defined by the spanning-tree, and by generating output signals using said node common frame synchronization signal as reference, and providing means for phase adjusting the generation of said output signals with respect to said node common signal individually for each output signal, so as to allow for thereby adjusting the delay between the start of frame at an input port of the node and the start of frame at the output port of the node forming part of the same interface as the input port and connecting to the same unidirectional multi-access link.

This means that if the node for example is connected to a unidirectional communication bus, an input port of the node being connected to receive frames of data from said bus and an output port being connected to transmit frames of data to said bus, the transmission of frames from the output port need not be directly frequency synchronized to the reception of frames at the input port. The output port may instead be primarily synchronized according to a frame signal that, for example, is received at another port of the node (typically nominally having the same frame frequency as the one on said in put port, or a multiple thereof) , but then in such a way that the phase relationship between the reception of frames from the input port and the transmission of frames from the output port is taken into consideration. This consequently has the advantage of allowing a greater freedom and flexibility when defining and building a synchronization tree of the above-mentioned kind for propagating synchronization signals through a communication network.

This feature is also very advantageous when a plurality of nodes are connected to a unidirectional bus that forms a single ring or loop with one node acting as head as well as terminating end of the loop. When closing the loop, the point in time at which the head end node transmits the start of a frame as head-end will typically not coincide with the point in time that it receives the start of a frame as terminating-end. If this difference in time should, for example, correspond to half a frame, then half a frame of data would have to be buffered at the head end node. However, by controlling the delay at the different nodes connected to the loop, in accordance with the invention, the required buffering needed to accommodate for the half-frame difference created by the closing of the loop may be distributed among all nodes of the ring in any desired way.

Also to be noted, another advantage with the freedom provided by using the spanning tree in the approach suggested by the invention is that the node actually controlling the frame frequency on a ring or bus need not be the head end node originating the frame start signal on the ring or bus. An advantage with generating an essentially phase- shift free node common frame synchronization signal according to an embodiment of the invention is that it limits or even eliminates negative effects sometimes caused by message-based approaches having a tendency to sometimes be overly dynamic and quick. As the network nodes are provided, using the message based approach, with the ability to make their own decisions as to the local structure of the synchronization spanning-tree, they may sometimes base such decisions upon local information that is invalid in a global perspective due to the fact information on changes in the network structure can only propagate through the network at a finite speed. During such situations, the node may make a plurality of decisions to change the local structure of the synchronization spanning-tree until the new, globally valid steady-state is finally obtained at the end of said interval. As the synchronization signals that are available at a node of the network may be arbitrarily located in phase with respect to each other, the phase stabilizing aspect of the invention has the advantage of making sure that the inevitable phase-shift associated with a change of signal to be used as reference for synchronization is not propagated downstream. This aspect of the invention thereby increases the quality of synchronization within the network by decreasing the amount of phase errors caused by local synchronization spanning- tree restructuring. The invention thus counteracts the "lack of rigidity" of the message-based synchronization scheme. For definition, in this context, a phase-shift refers to the situation wherein an essential discontinuity, or "jump", occurs or is generated in the phase of a signal.

Synchronization messages inter-changed in a message- based synchronization scheme of the kind discussed above will typically contain information related to the quality of a synchronization source from which the synchroniza- tion associated with said message originates, typically designating the priority of a synchronization source, said priority being considered in comparison to the prio- rity of other timing devices of the network. Each node will then select which node to synchronize operation to based upon which node has the highest priority.

Preferably, the synchronization messages will also contain information related to the quality of the network path between the node transmitting the respective message and the synchronization source from which said synchronization originates. Typically, such information may be the number of links or hops along the path between the node transmitting the respective message and the timing device from which said synchronization originates and/or information related to the length of time that at least a part of said path has been established. This information may then also be used to further assist in the decision as to which path to a reference source is the most preferred path. Typically, this will be the path having the lowest number of hops.

Synchronization messages of this kind are typically transmitted from a node to its next hop nodes. Of course, embodiments wherein nodes also send messages to other nodes than next hop nodes are also used. Such exchange of information on a larger scale will provided each node with more information on the overall network, but this will also require more processing capacity. The message- based scheme will also typically comprise means for reducing or eliminating the risk of synchronization loop formation.

Of course, there are many ways in which to design a message-based scheme for determining synchronization hierarchy and the scope of the invention is therefore not to be considered limited to the ones described and discussed explicitly herein.

As understood, the invention is especially applicable in networks wherein all nodes of is to operate at a common frequency at each point in time defined by a selected single synchronization source. The invention is especially advantageous in networks wherein the synchro- nization requirements are such that each frame synchronization signal may show a limited jitter and may be arbitrarily located in phase in relation to other frame synchronization signals, but may not show any persistent frame drift in relation to other frame synchronization signals .

Also, the invention is primarily concerned with the propagation of synchronization on a frame level. To be understood means for providing synchronization on a bit or slot level, while synchronizing a bit frequency and/or a slot frequency, could be added as well.

A frame synchronization signal according to the invention will preferably be a so-called start of frame signal that designates the start of a frame on a link and that is transmitted together with the frame on said link. Similarly, said node synchronization signal could for example also be regarded as a frame start signal.

As an example, the invention is specifically contemplated for use in a so-called DTM-network (Dynamic synchronous Transfer Mode) . Further information on the basics of DTM technology is found in "The DTM Gigabit Network", Christer Bohm, Per Lindgren, Lars Ramfelt, and Peter Sjδdin, Journal of High Speed Networks, 3(2): 109- 126, 1994, and "Multi-gigabit networking based on DTM", Lars Gauffin, Lars Hakansson, and Bjorn Pehrson, Computer networks and ISDN Systems, 24 (2 ): 119-139, April 1992.

This application is one in a series of three applications that were filed at the Swedish Patent Office on the same day, having the same title, the same applicant, and all referring to related inventive ideas, the description of the other two hereby being incorporated herein by reference.

The above mentioned and other aspects, features and details of the invention will be more fully understood from the following description of a preferred embodiment thereof. Brief Description of the Drawings

Exemplifying embodiments of the invention will now be described with reference to the accompanying drawings, wherein: Figs. 1A-1C schematically shows a DTM network;

Fig. 2 schematically shows an exemplifying design of a network node according to an embodiment of the invention;

Fig. 3 schematically shows an exemplifying embodi- ment of the node synchronization block shown in Fig. 2; and

Fig. 4 schematically shows an exemplifying embodiment of the output port blocks shown in Fig. 2.

Detailed Description of Preferred Embodiments

Figs. 1A-1C schematically show a DTM network 110 comprising nine nodes 111-119 that are interconnected via unidirectional physical links, for example in the form of optical fibers, illustrated as solid line arrows. For example, node 111 is physically connected to node 112 via two unidirectional links (one output link connected to transport signals to node 112 and one input link connected to transport signals in the opposite direction, i.e. from node 112). Similarly, node 113 is physically connected to node 112 via two unidirectional links, to node 114 via two unidirectional links, to node 116 via two unidirectional links, and to node 119 via two unidirectional links.

In Figs. 1A-1C, it is assumed that the nodes 111-115 are configured to regard the physical links interconnecting the nodes as together forming a two logical unidirectional multi-access links in the form of busses 131 and 132. Similarly, it is assumed that nodes 113, 116, 117, 118, and 119 will be configured to regard the physical links that interconnect these nodes as together forming two logical unidirectional, multi-access links in the form of single rings. On each of the logical multi- access links, a frame of time slot data, defined by a frame start signal, is to be transported and forwarded from a head end node on the link via all intermediate nodes to a terminating end node on the link. The network 110 also comprises two external clock reference sources 121 and 122, such as atomic or GPS clocks, connected to node 111 and node 118, respectively. In addition, each one of the nodes 111-119 comprises a respective internal clock reference source (not shown) . In this example, it is assumed that the each reference source is assigned a so-called reference source priority number, wherein the reference source 121 is assigned reference source priority number zero (0) and the reference source 122 is assigned reference source priority number one (1) . The lower the number, the higher the priority given to the respective reference source. While the above-mentioned internal clock reference sources are considered to be the least prioritized sources within the network, such internal clock reference sources are assig- ned a reference source priority number Pmax, Pmax being the highest available priority number and consequently representing a lowest priority.

Fig. IB illustrates how the synchronization spanning tree of the network 110 would be defined in prior art solutions. As frame frequency is as such defined by the frame start signals, and as frame start signal are propagated along multi-access links from head end node to terminating end node on each link, the synchronization spanning-tree would typically be defined to follow the structure of the unidirectional logical multi-access links of the network, starting at the head end node that is connected to the best clock reference source, e.g. node 111 in Fig. IB, and following the logical unidirectional bus 131 (see Fig. 1A) to the terminating node 115 on the link 131. As the terminating node 115 is the head end node on a logical unidirectional link 132 (see Fig 1A) propagating data in the opposite direction as compa- red to the first mentioned link, the terminating node 115 would use the received frame start signal on the link 131 to synchronize the frame start signal on the link 132. Also, node 113 forming a switch node to the logical links 133, 134 (see Fig. 1A) would act as head end node on link 133 and would be set to use the frame start signal received from the first mentioned link 131 to synchronize start of frame on link 133, to then be propagated from head end node to terminating end node on that link and optionally being "reversed" to synchronize operation in the opposite direction at said terminating node. Note that on the ring link, the head end node and the terminating node would be one and the same, i.e. node 113. Thus, using this prior art approach, the frame synchronization distribution spanning tree would receive the structure of the dashed arrow spanning tree 141 indicated in Fig. IB.

Fig. 1C illustrates how the synchronization spanning tree of the network 110 could be defined according to an embodiment of the invention. As the frame synchronization distribution spanning-tree according to the invention is defined based upon primarily regarding the network in terms of its physical connections and not, at least by default, based upon how, or whether or not, said links are configured to together form logical multi-access links, the spanning tree is in this embodiment simply based on finding the path to the currently best reference source that provides the best quality of synchronization, which in the example of Fig. 1C is based upon finding the shortest path to the best reference source. Thus, using the approach of this embodiment of the invention, in the manner as will be described more in detail below, the frame synchronization distribution spanning tree will receive the structure of the dashed arrow spanning tree 142 indicated in Fig. 1C. Note for example that whereas node 118 has five hops to the best reference source according to the prior art spanning-tree of Fig. IB, it only has four hops to the best reference source according to the spanning-tree in Fig. 1C.

In order to establish synchronization within the network 110 according to this embodiment of the invention, each node 111-119 is arranged to transmit so called synchronization messages to the neighbors that it has a physical output link to, and will receive similar synchronization messages from neighbors that it has a physical input link from. Each message will contain information related to the quality of synchronization available at the node transmitting the message. Based upon such synchronization information received in such messages, each node will select which node, or rather which physical input link, to use as its reference for synchronization, i.e. to use as synchronization source, as will be exemplified more in detail below.

The format of exemplifying synchronization messages that are transferred between neighboring nodes of the network 110 in Fig. 1A may for example be defined so as for each message to carry a reference source priority number of the kind discussed above with reference to Fig. 1A, and a node identification number that uniquely identifies the node that is directly connected to the reference source that has the subject reference source priority number (if said reference source is an internal clock reference source, the identification number will be identify the node that comprises said internal clock reference source) . The node identification number may for example be a MAC address or the like. If a node receives two synchronization messages suggesting the same reference source priority, the node will consider the message that carries the lowest node identification number as offering the better alternative for synchronization.

Each synchronization message will furthermore include a quality measure that for example may be used to identify the distance, as represented by a number of hops, to the reference source having the identification number identified in the respective message. The reason for this is that if a node receives two or more synchronization messages suggesting the same reference source priority and the same identification number, the node will consider the message suggesting the lowest number of hops to said reference as offering the better alternative for synchronization.

During operation, the nodes 111-119 in Fig. 1C will repeatedly transmit and receive messages of the type described in Fig. IB in order to establish how synchronization is to be propagated through the network. This will be illustrated by the following description of an exemplifying way in which the nodes interchange messages and synchronize operation accordingly. Initially, at network start-up, node 111 will synchronize its operation according to the external clock reference source 121 having the highest priority of zero (0) . Node 111 will therefore repeatedly transmit synchronization messages on its output link, said messages having RS set to zero (0), ID set to 111, and Q set to zero (0), i.e. informing that it operates according to a reference source having reference source priority zero (0), being connected to a node having node identification number 111, and being located at a distance of zero (0) hops from the node transmitting the message (i.e. node 111) . Node 118 will similarly synchronize its operation according to the external clock reference source 122 having priority one (1) and will transmit a synchronization message on its output links having RS set to one (1), ID set to 118, and Q set to zero (0). Nodes 112, 113, 114, 115, 116, 117, and 119, will transmit synchronization messages on their output links informing that they, in lack of better alternatives, operate according to their respective internal clock reference sources, i.e. messages having RS set to Pmax, ID set to 112, 113, ..., respectively, and Q set to zero (0). When starting to receive such synchronization messages, each node will evaluate said messages to determine whether or not select another reference source for synchronization. For example, node 112 will receive a) the message from node 111 stating that node 111 operates according to a reference source having RS zero (0) and being located at a distance of 0 hops (from node 111) , and b) a message from node 113 stating that node 113 operates according to its internal reference source. As a result, node 112 will determine that node 111 suggests a source having the highest priority available and consequently provides the most preferred synchronization reference. Node 112 will therefore synchronize its operation according to the synchronization provided via node 111. Node 112 will then start transmitting synchronization messages accordingly, i.e. stating that node 112 now operates based upon a reference source having priority zero (0) , which is connected to a node having node identification number 111, and being located at a dis- tance of 1 hop (from node 112), thus having incremented the hop count Q received in the message from node 111 by one (1) hop.

Similarly, node 119 will receive the message from node 118 stating that it operates according to a refer- ence source having RS one (1), having ID 118, and being located at a distance of 0 hops (from node 118) . As a result, instead of synchronizing operation according to its internal clock reference source, node 119 will determine that node 118 suggests a highest priority available. Node 119 will therefore synchronize its operation according to the synchronization provided via node 118, and will start transmitting synchronization messages now stating that node 119 operates based upon a reference source having priority one (1) , being connected to a node having ID 118, and being located at a distance of 1 hop (from node 119) . In a subsequent situation, node 113 may for example receive a) the message from node 112 stating that it operates according to a reference source having RS zero (0) located at a distance of 1 hop (from node 112), b) the message from node 119 stating that it operates according to a reference source having RS one (1) located at a distance of 1 hop (from node 119), and c) a message from node 114 stating that it operates according to its internal reference source (RS set to Pmax) . As a result, node 113 will determine the message from node 112 suggests a source having the highest priority available. Node 113 will therefore synchronize its operation according to the synchronization provided via node 112, and will start transmitting synchronization messages stating that it now operates based upon a reference source having priority zero (0), being connected to a node having ID 111, and being located at a distance of 2 hops (from node 113) .

In this manner, the process of synchronizing the network 100 will continue until all nodes synchronize operation according to the shortest path to the highest priority reference source 121, thus forming the spanning tree 142 of Fig. lC.

It is now assumed that a link failure occurs on both links between node 112 and node 113. In this situation, node 113 will stop receiving synchronization messages from node 112. This event will cause the node 113 to start searching for another best synchronization signal. Node 13 may for example also temporarily stop transmitting synchronization messages for a short period of time, said period being selected to be sufficiently long to ensure that no invalid messages pertaining to old, invalid synchronization states are left circulating within the network. As a result, node 113 will start resynch- ronizing its operation using synchronization message exchange in the same manner as described above. Since the best possible choice of synchronization source within the network, as long as said failure remains, is the refer- ence source 122 connected to node 118, all nodes of the network will eventually synchronize operation according to source 122. More specifically, synchronization according to reference source 121 will be selected/propagated to nodes 117 and 119 via node 118, to nodes 113 and 116 via nodes 119 and 117, respectively, to node 114 via node 113, and to node 115 via node 114. Node 112, being on the "other" side of the link failure, will still synchronize its operation according to the reference source 121 via node 111. When said link failure is eventually corrected, messages pertaining to the best synchronization source 121 will one again be forwarded through the network, and the network will automatically resynchronize accordingly. The description above exemplifies how the nodes 111- 119 of the network 110 in a distributed manner performs respective local decisions on how to synchronize operation based upon the transmission of synchronization messages between said nodes, and how the synchronization spanning-tree is automatically established and modified as a result thereof.

To be noted, in a network like DTM, synchronization distributed from one node to another in a tree-like manner will be a synchronization on a frame level, since synchronization on bit level is handled individually by each node in such a network. Therefore, the synchronization messages discussed above will in such a network mainly refer to the quality of synchronization on a frame level . Also, as is understood by those skilled in the art, that a message-based synchronization system could be designed to operate and interchange messages in many ways and that the invention in not limited to the one described in detail herein. Furthermore, while frame frequency synchronization is propagated along the spanning-tree 142 in Fig. 1C, the nodes will preferably simultaneously monitor (and adjust) the frame phase on the different interfaces of the node to keep a low delay from input port to output port connected to the same logical unidirectional multi-access link, as will be described more in detail below. Fig. 2 schematically shows a network node 200 that comprises three input port blocks 250a-250c, a node synchronization block 300, a switch core 400, a node controller 450, and three output port blocks 500a-500c.

Each one of the input port blocks 250a-250c is arranged to receive regularly occurring frames of data, divided into time slots, from respective input links. The location of each frame on the respective link is identified by an input frame synchronization signal, also being referred to as a frame start signal while being located in the stream of data to mark the beginning of each frame, which is carried along with the frames on the respective link. In this example, it is assumed that the frame frequency is nominally 8 kHz, corresponding to a frame length of 125 μs . Consequently, the frame synchro- nization signal of each respective link will be nominally received each 125 μs at the respective input port block.

Each input port block 250a-250c is arranged to derive data from time slots of received frames and to transmit such slot data to the switch core 400. Also, each input port block 250a-250c is arranged to derive the respective input frame synchronization signal from the respective input stream of data and to transmit said signal to the node synchronization block 300 and to a respective output port block 500a-500c. The switch core 400 is arranged to switch slots of data from the input port blocks 250a-250c to the output port blocks 500a-500c in accordance with switching instructions defined by the node controller 450. Furthermore, the switch core 400 is arranged to switch slots of data received in one or more control channels at the input port blocks 250a-250c from the input port blocks 250a-250c to the node controller 450, and to switch time slots of data to be transmitted in one or more control channels at the output port blocks 500a-500c from the node controller 450 to the output port blocks 500a-500c.

Data received/transmitted in said control channels from/to other nodes of the network will typically include channel management information. Based upon information, the node controller 450 will provide the switch core 400 with said switching instructions.

Data received/transmitted in said control channels will also include synchronization messages of the kind discussed above with reference to Figs. 1A-1C. Based upon an evaluation of such synchronization messages, the node controller 450 will select which input link, i.e. which input frame synchronization signal, that is to be used as synchronization source for synchronizing of the operation of the node 200. Based upon such a selection, the node controller 450 is connected to provide the node synchronization block 300 with a synchronization selection signal that identifies which input frame synchronization signal to use as synchronization source, the timing at which a switch to using another frame synchronization signal as synchronization source is to take place, and similar related information.

The node synchronization block 300 is connected to receive the input frame synchronization signals from the respective input port blocks 250a-250c and the synchronization selection signal from the node controller 450. Based upon these signals, the node synchronization block 300 is arranged to generate a node internal frame synch- ronization signal, also referred to below as node synchronization signal. The node synchronization signal is generated to have a continuous phase, i.e. to be essentially phase-shift free, which means that a change of synchronization source for generating said node synchro- nization signal will not cause any essential discontinuities or phase-shifts in the node synchronization signal. The node synchronization signal generated by the node synchronization block is transmitted to each one of the output port blocks 500a-500c. An example on how the phase-shift free node synchronization signal is generated by the node synchronization block 300 will be described in detail below with reference to Fig. 3.

Each one of the output port blocks 500a-500c typically receives data in slots from the switch core 400, input frame synchronization signals from a respective input port block 250a-250c, and the node synchronization signal from the node synchronization block 300. Using the node synchronization signal as synchronization source, optionally taking into account the phase of the respective received input frame synchronization signal, each output port will generate a respective output frame synchronization signal and will transmit said output frame synchronization signal as a frame start signal along with frames of time slot data received from the switch core 400 on a respective output link. An example on how this is realized will be described in detail below with reference to Fig. 4.

In operation, input port block 250a and output port block 500a could typically be configured as together forming a first input/output interface, input port block 250b and output port block 500b would be configured as together forming a second input/output interface, and input port block 250c and output port block 500c, would be configured as together forming a third input/output interface. Each interface would then optionally be connected to provide read and write access to a respective unidirectional bus, wherein frames of slots received at, for example, the input port 250a would be switched essentially as a whole by the switch core 400 to be transmitted essentially unaffected, with the exemption of specific slots being switch to/from other ports, at output port 500a. As an example, if node 200 would be configured as node 113 in Fig. 1A, said first interface could be connected to provide access to the unidirec- tional bus 131 from node 111 to node 115. More specifically, input port block 250a would be connected to the link from node 112 and output port block 500a would be connected to the link to node 114. Similarly, the second interface could be connected to the unidirectional bus 132 from node 115 to node 111, and the third interface could be connected to the unidirectional single ring bus 133, etc.

An exemplifying embodiment of the node synchroniza- tion block 300 shown in Fig. 2 will now be described with reference to Fig. 3. The block 300 in this embodiment comprises a selection unit 343, a phase offset detector 313, a first sample-and-hold circuit 323, a subtracting circuit 324, a low-pass filter 325, an adding circuit 326, a second sample-and-hold circuit 327, and a node synchronization signal generator 348.

As illustrated in Fig. 3, the block 300 is connected to receive input frame synchronization signals from all input port blocks 250a-250c. The block 300 is moreover arranged to generate a phase-shift free node synchronization signal based thereupon as controlled by control signals from the node controller 450, and to output said node synchronization signal to the output port blocks 500a-500c. For that purpose, the selection unit 343 is connected to receive the input frame synchronization signals from the three input port blocks 250a-250c, and to forward signals from one of these three input port blocks, as selected by the control signal from the node controller 450, to the phase offset detector 313.

The detector 313 is connected to receive the input frame synchronization signal from the selection unit 343 as well as a feedback copy of the node synchronization signal that is outputted from the generator 348. The detector 313 will determine the phase offset between the node synchronization signal and the input frame synchronization signal, said offset being outputted as an offset value to the first sample-and-hold circuit 323 and to the subtracting circuit 324.

The first sample-and-hold circuit 323 is in turn connected to sample the offset value from the detector 313 and to output a fixed offset value to the subtracting circuit 324. The sampled offset value is used to update the outputted fixed offset value at timings determined by the control signal from the node controller 450.

The subtracting circuit 324 is arranged to subtract the fixed offset value, outputted by the first sample- and-hold circuit 323, from the offset value outputted by the detector 313, and to output a resulting offset deviation to the low-pass filter 325, which in turn outputs a low-pass filtered deviation to the adding circuit 326. The adding circuit 326 is arranged to add the low- pass filtered deviation, as outputted by the low-pass filter 325, to the output from the second sample-and-hold circuit 327, and to output the thus resulting modified deviation as a frequency control signal to the generator 348 and to the second sample-and-hold circuit 327. The second sample-and-hold circuit 327 is furthermore arranged to sample said modified deviation and to update its fixed output at timings determined by control signals from the node controller 450. The generator 348 is arranged to generate said node synchronization signal, having a frequency of approximately 8 kHz, the output frequency being adjustable as a function of the received control signal.

The embodiment of Fig. 3 forms a feedback loop that continuously strives to bring the offset detected by the detector 313 to be equal to the fixed, "desired" offset output from the first sample-and-hold circuit 323 by the continuous adjustment of the output frame frequency of the generator 348. Any deviation between the offset from the detector 313 and the offset from the hold-over- circuit 323 will result in a non-zero input to the low- pass filter. If such a deviation is persistent over time, it will eventually be forwarded via the low pass filter 325 and the adding circuit 326 to the generator 348, and will then cause a small change in the frequency of the outputted node synchronization signal. This small change in frequency will act to slowly bring said difference back to zero.

To be noted, in a steady state situation, the frequency control signal inputted to the generator 348 will reflect the frequency of the input synchronization signal that is currently forwarded by the selection unit 343. Consequently, at repeated intervals, the node controller 450 will instruct the second sample-and-hold circuit 327 to incrementally/decrementally update its output in accordance with the current output from the adding circuit 326. This updating of the output of the second sample-and-hold circuit 327 provides a means for "memorizing" the network frequency. Note however that such updatings are in this exemplified embodiment performed in small steps in order to not give rise to any sudden large changes in the frequency control signal input to the generator 348.

When a change of synchronization source is to take place, the node controller will instruct the selection unit 343 to forward another input synchronization signal to the detector 313. As soon as the offset between the new input synchronization signal and the node synchronization signal has been determined and outputted by the detector 313, the node controller 450 will instruct the first sample-and-hold circuit 323 to update its output with to this new offset. The new offset is thereby set as the new desired offset that the design will strive to maintain in relation to the new input synchronization signal. As is understood, the normalization of the offset, as performed by the subtracting unit 324, in con- junction with the use of the low-pass filter 325, provides for a smooth behavior of the node synchronization signal generated by the generator 348 when switching synchronization source.

An exemplifying embodiment of the output port block 500 (denoted 500a-500c in Fig. 2) will now be described with reference to Fig. 4. In Fig. 4, the block 500 comprises a frame buffer 510, an output port 520, a phase offset detector 530, a phase offset control unit 540, and a phase offset generator 550.

As described above with reference to Fig. 2, and as illustrated in Fig. 4, the block 500 is connected to receive time slot data from the switch core 400, an input frame synchronization signal from a respective one of the input port blocks 250a-250c, a phase control signal (not shown in Fig. 2) from the node controller 450, and the node synchronization signal from block 300. Based upon the inputs, the block 500 is arranged to output frames.

More in detail, the frame buffer 510 is connected to receive said time slot data from the switch core and to store said time slot data in the frame buffer 510 prior to the transmission thereof from the output port 520. The output port 520 is in turn arranged to receive an output frame synchronization signal from the phase offset generator 550 and to transmit 125 μs frames of time slot data, as provided by the frame buffer, using said output frame synchronization signal to synchronize the transmission of the start of each frame.

The phase offset detector 530 is connected to receive the input frame synchronization signal from the respective one of the input port blocks 250a-250c, as well as a feedback copy of the output frame synchronization signal from the phase offset generator 550.

The detector 530 is arranged to determine the phase difference, corresponding to the bypass delay, between the input frame synchronization signal and the output frame synchronization signal. The detector 530 is implemented as a counter that is reset and started at the reception of each input frame synchronization signal and that is stopped at the reception of each output frame synchronization signal. Each so determined offset, provided as an offset count, is then outputted to the phase offset control unit 540. The phase offset control unit 540 is connected to receive the phase offset count from the detector 530, as well as the phase offset control signal from the node controller 450. As the phase offset count represents the difference in time between the input frame synch- ronization signal and the output frame synchronization signal, it also will reflect the overall delay through the node in Fig. 2, i.e. the time that it takes for data to pass through the switch from the input port providing the input frame synchronization signal to the output port 520. The purpose of the control unit 540 is to compare the offset count received from the detector 530 with a selected offset count, representing a desired delay through the node, received as said phase offset control signal from the node controller 450. Based upon such a comparison, the control unit 540, typically implemented in software, will generate an output offset count that is outputted to the phase offset generator 550.

The phase offset generator 550 is arranged to receive the node synchronization signal from block 300 and to add the offset received from the control unit 540 thereto, thereby adjusting the phase of the frame synchronization signal outputted from the generator 550 to provide for a desired delay through the node. The so phase-adjusted output frame synchronization signal from the generator 550 is then provided to the detector 530 and to the output port 520, which will transmit frames of data based thereupon as described above.

Consequently, the function of the detector 530, the control unit 540, and the offset generator 550 is to adjust the transmission of the output frame synchronization signal to provide for a desired delay through the node. Furthermore, as the output frame synchroniza- tion signal is generated using the node synchronization signal as reference, the latter having been generated as described above to be essentially phase shift free irrespective of any change of input frame synchronization signal to be used as synchronization source, an essentially continuous behavior of the output frame synchronization signal is ensured.

Even though exemplifying embodiments of the invention have been described in detail above with reference to the accompanying drawings, different modifications, combinations and alterations thereof may be made within the scope of the invention, which is defined by the accompanying claims.

Claims

1. A method for providing frame synchronization in a synchronous communication network, comprising: combining physical node-to-neighbor-node links into forming logical multi-access unidirectional links, on each of which data is transferred in a recurrent frame that is defined by a frame synchronization signal on the link and that is forwarded downstream on the link by the nodes attached to the link; and defining a frame synchronization distribution spanning tree for said network so as to span said network by regarding the network in terms of node-to-neighbor-node physical links branches, and not by default limiting the structure of said spanning tree to follow the structure of said network in terms of it's logical multi-access unidirectional links as such.

2. A method as claimed in claim 1, said defining of the frame synchronization spanning tree being performed using a message-based, distributed scheme for determining synchronization hierarchy.

3. A method as claimed in claim 2, said message- based, distributed scheme for determining synchronization hierarchy using a node-to-neighbor-node signaling scheme.

4. A method as claimed in claim 2 or 3, said message-based, distributed scheme for determining synch- ronization hierarchy being based on having each node controlling the local structure of the synchronization spanning-tree using information provided in messages of the message-based scheme.

5. A method as claimed in claim 2, 3, or 4, said message-based, distributed scheme for determining synchronization hierarchy being based on having each node controlling the local structure of the synchronization spanning-tree and, in doing so, regarding the local structure of the network in terms of the physical links connected to the node and disregarding the local structure of the network in terms of said physical links being defined to form part of logical multi-access unidirectional links.

6. A method as claimed in any one of the preceding claims, the structure of said spanning-tree being continuously updated to reflect any changes in the operational structure of the network.

7. A method as claimed in any one of the preceding claims, said method comprising, for an output port of a node in said network: determining which input port of the node to use as reference for frame frequency synchronizing transmissions of frame synchronization signals from said output port according to the determined synchronization distribution spanning tree; determining which frame phase to apply when transmitting said frame synchronization signals from said output port by regarding whether or not the physical link connected to said output port forms part of a logical multi-access link and if so selecting said frame phase considering the frame phase on said logical multi-access link.

8. A method as claimed in any one of the preceding claims, comprising generating, at a node of said network, a node synchronization signal in such a way that a change in which input frame synchronization signal to be used as reference for frame synchronization when generating said node synchronization signal, as determined by said spanning tree, does not cause any phase-shift in said node synchronization signal.

9. A method as claimed in claim 8, comprising the step of determining the frame phase relationship between said node synchronization signal and the one of said input frame synchronization signals that is to be used as the new reference for synchronization and performing said change in such a way that the determined frame phase relationship between said node synchronization signal and said new reference is maintained.

10. A method as claimed in claim 8 or 9, comprising transmitting two or more output frame synchronization signals using said node synchronization signal as reference .

11. A method as claimed in claim 10, comprising controlling the phase difference between the transmissions of said two or more output frame synchronization signals and the occurrences of said node synchronization signal in such a way that each one of said two or more output frame synchronization signals shows a respective phase difference, in relation to said node synchronization signal, that is controlled individually for each respective output frame synchronization signal.

12. A method as claimed in claim 10, comprising monitoring the phase difference between transmissions of said two or more output frame synchronization signals and respective ones of two or more input frame synchroniza- tion signals and to control the phase of the transmissions of the respective one of said two or more output frame synchronization signals with respect to the occurrences of said node synchronization signal individually so as to adjust the monitored phase differences.

13. A method as claimed in any one of the preceding claims, comprising controlling the transmissions of any output frame synchronization signal from a node of the network so that it is related to an input frame synchronization signal of said node in such a way that: a) said output frame synchronization signal is transmitted to show an arbitrary phase difference in relation to said input frame synchronization signal; b) said output frame synchronization signal is transmitted to show a limited phase jitter in relation to said input frame synchronization signal; and c) said output frame synchronization signal is transmitted to not show any persistent phase drift in relation to said input frame synchronization signal.

14. An apparatus in a communication network, said apparatus comprising: receiving means (250) for receiving two or more input frame synchronization signals from respective input ports to be connected to two or more respective physical links of a communication network; and processing means (450) for defining at least the local formation of said physical links into logical multi-access unidirectional links, on each of which data is transferred in recurrent frames that is defined by a frame synchronization signal on the link and that is forwarded downstream on the link by the nodes attached to the link, and for defining which input frame synchronization signal to use as reference for frame synchronization be determining the local structure of a frame synchronization spanning-tree and, in doing the latter, regarding the local structure of the network in terms of the physical links connected to the node and disregarding the local structure of the network in terms of said physical links being defined to form part of logical multi-access unidirectional links as such.

15. An apparatus as claimed in claim 14, said processing means being arranged to define the local structure of said frame synchronization spanning tree by processing synchronization information as received in messages from one or more other nodes of said network in accordance with a message-based, distributed scheme for determining synchronization hierarchy.

16. An apparatus as claimed in claim 14 or 15, further comprising output means (500) being connectable to a physical link of said communication network, said processing means defining which input port of the node to use as reference for frame frequency synchronizing transmissions of output frame synchronization signals from said output port according to the structure of the defined synchronization distribution spanning tree, said output means comprising phase adjustment means (450, 530, 540, 550) for adjusting the frame phase applied when transmitting said output frame synchronization signals by regarding whether or not the physical link connected to said output means forms part of a logical multi-access link and if so adjusting said frame phase considering the frame phase on said logical multi-access link.

17. An apparatus as claimed in claim 14, 15, or 16, further comprising generating means (300) for generating a node synchronization signal using said selected signal to be reference for synchronization in such a way that a change of signal to be used as said reference, as determined by said processing means, does not cause any phase-shifts in said node synchronization signal.

18. An apparatus as claimed in claim 17, said generating means comprising: detecting means (313) for determining the frame phase relationship between said node synchronization signal and one of said frame synchronization signals that is to be used as a new reference, and means (323, 324, 348) for generating said node synchronization signal, when a change into using said one of said frame synchronization signals as said reference, in such a way that said frame phase relationship between said node synchronization signal and said one of said frame synchronization signals is maintained.

19. An apparatus as claimed in claim 17 or 18, comprising means (500) for transmitting two or more output frame synchronization signals from respective ports of said node using said node synchronization signal as reference for synchronization.

20. An apparatus as claimed in claim 19, comprising means (530, 540, 550) for controlling the phase difference between the transmissions of said two or more output frame synchronization signals and the occurrences of said node synchronization signal individually for each respective output port.

21. An apparatus as claimed in claim 20, said means (530, 540, 550) being arranged to monitor the phase difference between transmissions of said two or more output frame synchronization signals and respective ones of said two or more input frame synchronization signals and to control the phase of the transmissions of the respective one of said two or more output frame synch- ronization signals with respect to the occurrences of said node synchronization signal individually to adjust the monitored phase differences.