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WO1998012750A1 - Composant de circuit integre a semi-conducteur - Google Patents

Composant de circuit integre a semi-conducteur Download PDF

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Publication number
WO1998012750A1
WO1998012750A1 PCT/JP1996/002722 JP9602722W WO9812750A1 WO 1998012750 A1 WO1998012750 A1 WO 1998012750A1 JP 9602722 W JP9602722 W JP 9602722W WO 9812750 A1 WO9812750 A1 WO 9812750A1
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WO
WIPO (PCT)
Prior art keywords
circuit
substrate
semiconductor substrate
integrated circuit
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1996/002722
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English (en)
Japanese (ja)
Inventor
Toshiro Tsukada
Keiko Fukuda
Satoshi Maeda
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Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to PCT/JP1996/002722 priority Critical patent/WO1998012750A1/fr
Publication of WO1998012750A1 publication Critical patent/WO1998012750A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/211—Design considerations for internal polarisation
    • H10D89/213—Design considerations for internal polarisation in field-effect devices

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly to an analog-to-analog gnodigital mixed semiconductor in which an analog circuit (analog module) and a digital circuit (digital module), which are functional circuit units, are integrated on the same semiconductor chip.
  • the present invention relates to an effective technique for reducing the influence of noise generated by a digital circuit on an analog circuit via a common semiconductor substrate.
  • analog to digital converters have analog modules such as pumps and digital modules such as microcomputers and memories mounted on the same semiconductor chip.
  • ADCs analog to digital converters
  • the demand for digital mixed-type semiconductor integrated circuits is expanding.
  • analog-Z mixed digital type semiconductor integrated circuit device the noise is generated by a digital module (for example, a noise caused by a transient current generated when a digital clock rises or falls). Degradation of the performance of analog modules has become a major problem and needs to be solved.
  • JP-A-58-70565 and JP-A-59-193046 disclose that noise generated in a digital circuit portion is mixed with an analog circuit portion. It states that the power supply wiring for the digital circuit and the analog circuit should be provided independently to prevent malfunction of the analog circuit.
  • FIG. 1 shows the configuration of such a conventional integrated circuit.
  • a low impurity concentration substrate 12 composed of an epitaxy layer is formed on a high impurity concentration bulk substrate 11 and has a low impurity concentration.
  • An analog section 1 and a digital section 2 are formed inside the pure substance concentration board 12 to constitute an analog / digital mixed integrated circuit.
  • the substrate bias power is supplied to the substrate 11 or the substrate 12, and the potential of the substrate 12 is maintained.
  • the analog section 1 and the digital section 2 are coupled via the resistors of the common boards 12 and 11, the digital noise generated in the digital section 2 due to the board resistance coupling is transmitted to the analog section 1. Transmitted, often causing malfunctions in analog circuits.
  • n-type wells are provided for an analog circuit and a digital circuit on a substrate of an integrated circuit.
  • the n-type well contains a p-type well and forms an analog [one-way or digital circuit].
  • This double cell structure separates the circuit parts from each other, and prevents digital noise from entering the analog part through the common substrate.
  • Japanese Patent Application Laid-Open No. 2-27171567 describes a technique for insulating and separating a digital part and an analog part by using a substrate having an SOI structure and a separation groove reaching an insulating layer of the substrate having the SOI structure. Is described.
  • guard band or guard ring As a circuit solution, a high impurity concentration diffusion layer called guard band or guard ring is provided on the surface of the substrate between the analog circuit and the digital circuit, and this is connected to an external power ground. It has been used to absorb digital noise and to suppress the transmission of noise to analog circuits. These methods are described in "Monthly Semiconductor World", 1993, 1 Jj (p.174-177). Disclosure of the invention
  • the power supply wiring (V cc) and the ground wiring (GND) formed on the surface of the semiconductor chip are independent of the analog circuit and the digital circuit, respectively. It is formed so that direct noise from the power supply wiring (V cc) and the ground wiring (GND) rarely affect each other.
  • the encapsulant (LSI package) is mounted on a mounting substrate such as a printed wiring board, the ground wiring (GND) of the analog circuit and digital circuit is sealed (LSI package).
  • the grounding wire (GND) on the mounting board has a much lower impedance than the grounding wire (GND) formed on the semiconductor chip, the effect of noise is small.
  • noise transmitted through the inside of a semiconductor chip, further transmitted through a metal lead frame on which a semiconductor chip is mounted, and further transmitted through a metallic lead frame mounted with a semiconductor chip. Is not taken into account and is not enough to reduce and prevent noise.
  • the semiconductor chip 21 is usually mounted on a metal lead frame, and a conductive material 23 such as silver paste is used to attach the chip support portion (die pad) 22 of the lead frame. Fixed.
  • a sealing material such as a lead portion of a lead frame and a resin is omitted for convenience of explanation.
  • the resistance of the silicon integrated circuit board 3 in the vertical direction is the lower part of the digital module 25.
  • the resistance of the silicon integrated circuit board 3 in the horizontal direction is about 100 ⁇ in the digital module section 25 and about 10 ⁇ in the lower part of the analog module 24. It is about 50 ⁇ between digital modules 25.
  • the path 2 The resistance of 6 is about 16.5 ⁇ .
  • the noise generated by the digital module 25 is transmitted in the vertical direction, reaches the chip support 22 once, propagates through the chip support 22, and is transmitted from the lower part of the analog module 24.
  • the total resistance of the path 27, which reenters the silicon integrated circuit board 3 and is transmitted to the analog module in the vertical direction, is sufficient for the resistance of the metal chip support portion 12 to be greater than the resistance of the silicon integrated circuit board 3. , It is about 15 ⁇ . This is less than 1 ⁇ 10 of the resistance of the path 26.
  • Encapsulant LSI package
  • the digital module or al noise transmitted to the chip supporting portion 2 2 there is a problem that the probability of returning to the surface of the silicon substrate is high, and the electrical reliability of the mixed analog / digital type semiconductor integrated circuit is further reduced.
  • the thickness of the epitaxial layer 12 corresponding to the silicon integrated circuit substrate 3 shown in FIG. 2 is thin, the resistance in the vertical direction with respect to the horizontal direction is further reduced. Become smaller.
  • the bottom surface of the epitaxial layer 12 is in contact with the high impurity concentration substrate, that is, the low-resistance impurity semiconductor 11, which serves as a metal chip support portion 22 of the silicon integrated circuit substrate 3 in FIG. .
  • the noise generated by the digital module is more likely to be propagated to the analog module, and the reliability of the mixed analog / digital semiconductor integrated circuit device is reduced.
  • the SOI structure substrate for insulation membrane separation is effective in decoupling of the low-frequency signal c, however, the SOI structure substrate is of relatively high frequency thin insulating film with ⁇ noise generated by the digital module There is a problem that noise cannot be cut off sufficiently due to capacitive coupling.
  • the SOI structure substrate is economically disadvantageous, such as requiring a special process for forming an insulating film.
  • the SOI structure substrate cannot supply ground potential (GND) from the back side of the substrate due to its structure, it is disadvantageous in terms of noise absorption efficiency, and it is also difficult to use analog modules that are strictly accurate. It is also disadvantageous in stabilizing the substrate potential. For this reason, when an SOI structure substrate is used, there is a problem that the electrical reliability of a mixed analog / digital type semiconductor integrated circuit device is reduced.
  • GND ground potential
  • the substrate between the digital circuit and the analog circuit is separated, so that the influence of noise due to the substrate coupling is reduced.
  • the process steps are complicated, and a voltage gradient due to noise is apt to occur on the substrate of each separated circuit region structurally, and it is difficult to keep the substrate potential of each circuit region uniform.
  • the non-uniformity of the substrate potential degrades the balance of, for example, a differential type analog circuit, and causes a problem of limiting the effect of reducing common mode noise.
  • the digital module support is connected independently to the digital module support, and these analog module support and digital module support are connected via independent analog module ground leads and digital module ground leads.
  • the method of connecting to the ground wiring (GND) of the mounting board was also studied by the present inventors.
  • the analog module ground lead terminal and the digital module ground lead terminal each have a non-negligible lead 'inductance.
  • the noise current due to the operation of the digital module is reduced from the digital module of the semiconductor chip to the ground wiring (GND) of the mounting board via the digital module support section and the lead of the digital module ground lead terminal.
  • the digital module and the digital module support are not maintained at the virtual ground potential, and a noise voltage is generated due to the noise current flowing through the lead inductance.
  • the analog module generates a large-amplitude output signal
  • the noise current due to the operation of the digital module is transferred from the digital module of the semiconductor chip to the analog module supporting portion and the analog module ground lead terminal. Since the ground wiring (GND) of the mounting board flows through the lead's inductance, the analog module and the analog module support are not maintained at the virtual ground potential, and the noise due to the noise current flowing through the lead's inductance A voltage is generated.
  • the present invention has been made based on the results of the study by the inventors of the present invention as described above, and an object of the present invention is to provide a semiconductor integrated circuit device capable of solving the problem of circuit performance degradation or malfunction. To do.
  • a first functional circuit portion (2) is formed in a first surface region of the main surface, and a first voltage detection region (6a) and a first voltage control region (6b) are formed near the first surface region of the main surface.
  • a first substrate support member (4b) made of a conductive material connected to a first back surface region of the back surface of the semiconductor substrate (3) located below the first functional circuit portion;
  • a reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
  • An inverting input terminal (1) of the amplifier circuit (7a) is connected to the first voltage detection region (6a) on the main surface of the semiconductor substrate (3);
  • An output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6b) on the main surface of the semiconductor substrate (3) (see FIG. 3).
  • the first substrate support member (4b) is not connected to the ground wiring (GND) of the mounting board via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplification board.
  • the feedback operation of the circuit (7a), the first voltage detection area (6a), the first voltage control area (6b), and the first substrate support member (6) on the main surface of the semiconductor substrate (3) 4b) is virtually set to the above-mentioned reference voltage (GND).
  • the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member (4b) to substantially the reference voltage (GND), and the feedback of the amplifier circuit (7a) does not contribute. The action contributes.
  • the application of the reference voltage (GND) to the non-inverting input terminal (+) of the amplifier circuit (7a) is performed by the ground lead terminal of the semiconductor integrated circuit device. a) If the stray capacitance between the inverting input terminal (1) and the non-inverting input terminal (+) can be neglected, the lead of the ground lead terminal of the non-inverting input terminal (+). The noise power due to the noise current flowing through the device also becomes a negligible level.
  • the first voltage detection area (6a) and the first voltage control area (6b) correspond to the first functional circuit section (2) of the first surface area of the main surface of the semiconductor substrate (3). ), Formed by a conductive double ring guard band formed around
  • the first voltage detection area (6a) and the first substrate supporting member (4b) are set to substantially the reference voltage (GND), and the first function
  • the feature is that it can reduce the complexity of the circuit section (2) (see Fig. 3 BB).
  • the first voltage detection area (6a) and the first voltage control area (6b) are formed around the first functional circuit section (2). Since the guard band is a heavy ring guard band, the noise propagated between the first functional circuit section (2) and other portions of the semiconductor substrate (3) can be reduced more completely.
  • a semiconductor integrated circuit device according to a more specific embodiment of the present invention
  • a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
  • the first voltage detection area (6a) and the first substrate support member (4b) are set to substantially the reference voltage (GND). (See Fig. 3).
  • noise propagated between the first functional circuit unit (2) and the second functional circuit unit (1) can be reduced.
  • a second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the second substrate support member (4a) is set to approximately the reference voltage (GND) (see FIG. 3).
  • Another conductive guard band (6c) is formed around (1),
  • the other guard band (6c) is set to approximately the reference voltage.
  • Another conductive guard band (6c, 6d) is formed around (1) around the second functional circuit portion in the second surface region of the main surface of the semiconductor substrate (3),
  • a second substrate support member (4a) made of a conductive material connected to a second back surface area located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the semiconductor substrate includes another amplifier circuit (7b),
  • the other guard bands are a second voltage detection region (6c) and a second voltage control region (6d) composed of the guard band of another double ring.
  • the above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
  • the inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second voltage detection area (6c) on the main surface of the semiconductor substrate (3),
  • the output terminal of the other amplifier circuit (7b) is connected to the second voltage control region (6d) on the main surface of the semiconductor substrate (3),
  • the second voltage detection area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 6). According to such a more specific embodiment, it is possible to reduce noise propagated between the first functional circuit section (2) and the second functional circuit section (1).
  • One and the other of the first functional circuit section (2) and the second functional circuit section (1) are a circuit for processing a digital signal and a circuit for processing an analog signal. 3 to 6).
  • a first functional circuit portion (2, 1) is formed in a first surface region of the main surface, and a first voltage control region (6a, 6c) is formed in the vicinity of the first surface region of the main surface,
  • a first substrate support member (4b, 4b) made of a conductive material connected to a first back surface region located below the first functional circuit portion (2, 1) on the back surface of the semiconductor substrate (3).
  • the reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a, 7b).
  • the inverting input terminal (1) of the amplifier circuit (7a, 7b) is connected to the first substrate support member (4b, 4a),
  • the output terminal of the amplifier circuit (7a, 7b) is connected to the first voltage control region (6a, 6c) on the main surface of the semiconductor substrate (3). See Figures 7 and 8.)
  • the first substrate support member (4b, 4a) is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the amplifier circuit (7a 7b) is virtually set to the above-mentioned reference power (GND) virtually.
  • the first substrate supporting members (4b, 4a) are substantially the same in phase opposite to the generated noise as virtually set to the reference voltage (GND).
  • An amplitude cancellation signal is applied from the output terminal of the amplifier circuit (7a, 7b) to the first voltage control area (6a, 6c).
  • the potential fluctuation of the first substrate support member (4b, 4a) is also reduced, and even if the stray capacitance cannot be ignored, the ground lead terminal of the non-inverting input terminal (+) can be used.
  • the noise voltage due to the noise current flowing through the lead ⁇ inductance is also at a negligible level.
  • the first voltage control region (6c) is formed by a guard band of a conductive ring formed around the first functional circuit portion (1) on the first surface region on the main surface of the semiconductor substrate (3). Composed,
  • the first voltage control area (6c) and the first substrate support member (4a) are set to substantially the reference voltage (GND), and noise can be reduced. (See Fig. 8).
  • the first voltage control area (6c) is a guard band of a ring formed around the first functional circuit section (1). Noise transmitted between the functional circuit section (1) and other parts of the semiconductor substrate (3) can be reduced more completely.
  • a second functional circuit portion (2) is formed in a second surface region of the main surface of the semiconductor substrate (3);
  • the feedback operation of the amplifier circuit (7b) sets the first voltage control area (6c) and the first substrate support member (4a) to approximately the reference voltage (GND). (See Figure 8).
  • the second substrate support member (4b) made of a conductive material connected to the second back surface region located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the second substrate support member (4b) is set to approximately the reference voltage (GND) (see FIG. 9).
  • the other guard band (6a) is set to approximately the above-mentioned reference voltage (GND) (see Fig. 9).
  • Another conductive guard band (6a) is formed around the second functional circuit portion (2) in the second surface region on the main surface of the semiconductor substrate (3), A second substrate support member (4b) made of a conductive material connected to a second back surface area located below the second functional circuit portion (2) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the semiconductor substrate (3) includes another amplifier circuit (7a),
  • the other guard band is a second voltage control region (6a) composed of a ring guard band,
  • the reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7a),
  • the inverting input terminal (1) of the other amplifier circuit (7a) is connected to the second substrate support member (4b) of the semiconductor substrate (3),
  • the output terminal of another amplifier circuit (7a) is connected to the second voltage control region (6a) on the main surface of the semiconductor substrate (3).
  • the second voltage control region (6a) and the second substrate support member (4b) are set to substantially the reference voltage (GND) by a feedback operation of the other amplifier circuit (7a). (See Figure 9).
  • One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
  • a first functional circuit portion (2) is formed in a first surface region of the main surface, a first voltage control region (6a) is formed in the vicinity of the first surface region of the main surface, and an amplifier circuit (7a) is formed. ) Containing a semiconductor substrate (3);
  • a first substrate support member (4b) made of a conductive substance connected to a first back surface region located below the first functional circuit portion (2) on the back surface of the semiconductor substrate (3);
  • the first voltage control region (6a) is constituted by a guard band of a conductive ring formed around the first functional circuit portion (2) in the first surface region of the main surface of the semiconductor substrate.
  • a reference voltage (GND) is applied to the non-inverting input terminal (+) of the amplifier circuit (7a),
  • the inverting input terminal (-) of the amplifier circuit (7a) is connected between the semiconductor substrate (3) and the first substrate support member (4b) so that the amplifier circuit (7a) detects noise due to circuit operation. Connected to at least one of them, The output terminal of the amplifier circuit (7a) is connected to the first voltage control region (6a) on the main surface of the semiconductor substrate (3) by connecting the output terminal of the amplifier circuit (7a). The output signal of the terminal is characterized by reducing the noise (see FIGS. 3 and 7).
  • the first voltage control area (6a) is provided with the first function. Since it is constituted by a guard band of a conductive ring formed around the circuit section (2), the gap between the first functional circuit section (2) and the other portion of the semiconductor substrate (3) is provided. Propagated noise can be reduced more completely.
  • a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
  • the second substrate support member (4a) made of a conductive material connected to the second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the second substrate support member (4a) is set to approximately the first voltage (see FIGS. 3 and 7).
  • a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
  • Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region on the main surface of the semiconductor substrate (3);
  • the other guard band (6c) is set to approximately the reference voltage (G ND) (see Figs. 4 and 7).
  • a second functional circuit portion (1) is formed in a second surface region of the main surface of the semiconductor substrate (3);
  • Another conductive guard band (6c) is formed around the second functional circuit portion (1) in the second surface region of the main surface of the semiconductor substrate,
  • a second substrate support member (4a) made of a conductive material connected to a second back surface region located below the second functional circuit portion (1) on the back surface of the semiconductor substrate (3) is further added. Equipped,
  • the semiconductor substrate (3) includes another amplifier circuit (7b),
  • the other guard band (6c) is the second voltage composed of the ring guard band. Control area,
  • the above reference voltage (GND) is applied to the non-inverting input terminal (+) of the other amplifier circuit (7b),
  • the inverting input terminal (1) of the other amplifier circuit (7b) is connected to the second substrate support member of the semiconductor substrate (3),
  • An output terminal of the other amplifier circuit (7b) is connected to the second voltage control region on the main surface of the semiconductor substrate.
  • the second voltage control area (6c) and the second substrate support member (4a) are set to substantially the reference voltage (GND) by the feedback operation of the other amplifier circuit (7b). (See Figure 9).
  • One and the other of the first functional circuit section and the second functional circuit section are a circuit for processing a digital signal and a circuit for processing an analog signal (see FIGS. 7 to 9). .
  • the substrate support member is constituted by a packaged metal lead frame.
  • the above semiconductor substrate is a low impurity concentration semiconductor layer formed on a silicon substrate (13).
  • the configuration of the present invention can be achieved by a simple process, it is possible to improve the electrical reliability of a semiconductor device including a mixed analog / digital semiconductor integrated circuit device and to reduce the cost.
  • FIG. 1 is a diagram for explaining a conventional integrated circuit structure in a mixed analog / digital type semiconductor integrated circuit device.
  • FIG. 1 is a model diagram of a conventional semiconductor integrated circuit device including a semiconductor integrated circuit.
  • FIG. 3 is a diagram illustrating an analog / digital Z-mixed semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 4 is a diagram for explaining a diagram for explaining another analog / digital Z-mixed semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 5 is a diagram for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 6 is a view for explaining an analog / digital Z-mixed semiconductor integrated circuit device according to a third embodiment of the present invention.
  • FIG. 7 is a diagram illustrating a mixed analog / digital semiconductor integrated circuit device according to a fourth embodiment of the present invention.
  • FIG. 8 is a diagram illustrating an analog-Z digital mixed type semiconductor integrated circuit device according to a fifth embodiment of the present invention.
  • FIG. 9 is a diagram illustrating a mixed analog / digital type semiconductor integrated circuit device according to a sixth embodiment of the present invention.
  • FIG. 10 is a diagram illustrating an analog / digital mixed semiconductor integrated circuit device according to a seventh embodiment of the present invention.
  • FIG. 1 is a view for explaining a substrate structure of an analog / digital Z-type mixed semiconductor integrated circuit device according to an eighth embodiment of the present invention.
  • FIG. 12 is a view for explaining another substrate structure of an analog / digital mixed semiconductor integrated circuit device according to a ninth embodiment of the present invention. -Best mode for carrying out the invention
  • FIGS. 3 and 4 show a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of the present embodiment.
  • the analog section 1 is configured with a circuit that handles weak analog signals such as an amplifier and an A / D converter
  • the digital section 2 is configured with digital circuits such as logic and memory.
  • a low-concentration p-type or n-type silicon substrate force f is used for the integrated circuit substrate 3.
  • independent conductor parts 4a and 4b which are electrically separated from each other, are connected to positions corresponding to the lower part of the analog part 1 and the digital part 2 area, respectively. Is done.
  • the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
  • the conductor portions 4a and 4b can be connected to the substrate 3 using a conductive adhesive such as silver paste, for example.
  • a conductive adhesive such as silver paste, for example.
  • ring-shaped guard bands 6a and 6b of a high concentration p-type or n-type diffusion layer are arranged and formed.
  • guard bands 6a and 6b are integrated circuit boards 3 W
  • they serve as electrodes of the integrated circuit substrate 3 composed of the resistors 5a and 5b.
  • the board noise generated in the digital section 2 is canceled, and the noise canceling signal generating circuit 73 is connected to the guard bands 6a and 6b.
  • the noise canceling signal generation circuit 7a is composed of a circuit such as an operational amplifier.
  • the inverting input terminal (1) is connected to the guard band 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the ground. Connect to band 6b.
  • the noise canceling signal generating circuit 7a is formed inside the integrated circuit board 3, and is preferably formed inside the analog section 1 in order to make it insensitive to noise.
  • the noise canceling signal generating circuit 7a can generate a canceling signal for canceling the original noise generated in the digital section.
  • a signal is generated at the output terminal so that the potential of the guard band 6a connected to the inverting human input terminal (1) becomes a virtual ground.
  • the guard band 6a force 5 ' is ideally virtual grounded because the conductor 4b is grounded via the force resistance 5a. It means that it becomes a potential. Therefore, since the noise canceling signal that comprehensively cancels the noise voltage source generated in the digital section 2 is generated by the noise canceling signal generation circuit 7a, the conductor section 4 is maintained at the ground potential free of flicker noise. Will be.
  • the first substrate support member 4b is not connected to the ground wiring GND of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is connected to the ground of the amplification circuit 7a.
  • the first voltage detection region 6a, the first voltage control region 6b, and the first substrate support member 4b on the main surface of the semiconductor substrate 3 are virtually set to the reference voltage GND by the feedback operation.
  • the ground lead terminal of the semiconductor integrated circuit device does not directly contribute to the setting of the first substrate support member 4b to the substantially reference voltage GND, but the feedback operation of the amplifier circuit 7a contributes.
  • the reference voltage GND is applied to the non-inverting input terminal + of the amplifier circuit 7a by the ground lead terminal of the semiconductor integrated circuit device. If the stray capacitance between them can be neglected, the noise voltage due to the noise current flowing through the lead and inductance of the ground lead terminal of the non-inverting input terminal will also be at a negligible level.
  • the substrate potential of the analog section 1 may be obtained by directly grounding the conductor section 4a connected to the bottom surface of the integrated circuit board 3 of the analog section 1 as shown in FIG. As described above, by directly grounding the guard band 6c of the analog section 1, the substrate potential of the analog section 1 can be supplied, and a stable constant potential can be maintained.
  • noise generated by the digital circuit is canceled in the area of the digital section 2 of the integrated circuit board 3 by the noise canceling signal generation circuit 7a and the conductor section 4b. Since the data is erased, digital noise applied to the analog circuit of the analog unit 1 can be suppressed. Further, the ground potential is supplied to the bottom surface of the integrated circuit board 3 of the analog section 1 by the conductor section 4a independent of the digital section, so that the board potential can be kept stable and uniform. For this reason, analog circuits are often used to prevent degradation of characteristics due to noise, such as deterioration of the balance of the high-precision differential circuits used, and to provide a stable and highly reliable analog / digital mixed integrated circuit device. it can.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3.
  • ring-shaped guard bands 6c and 6d made of a diffusion layer having a high impurity concentration and serving as electrodes of the integrated circuit board 3 are arranged.
  • Independent conductor sections 4a and 4b are connected to the positions corresponding to section 1 and digital section 2, respectively.
  • the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
  • the guard bands 6c and 6d are connected to a noise canceling signal generation circuit 7 '.
  • the noise canceling signal generation circuit 7b is composed of a circuit such as an operational amplifier.
  • the inverting input terminal (1) is connected to the guard band 6c, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard band 6d.
  • the noise canceling signal generation circuit 7b generates an output signal on the guard band 6d by the feed knock operation so that the guard band 6c is always at the virtual ground.
  • the conductor 4a is also fixed to the ground potential, and the noise canceling signal generating circuit 7b generates a canceling signal to cancel the noise arriving from the digital section. And apply to guard band 6d.
  • the substrate of the analog section 1 can be maintained at a stable potential without noise.
  • the substrate potential of the digital section 2 is connected to the conductor section 4 b connected to the bottom of the board or the guard band 6 a formed on the board surface to a stable ground potential, and biased independently of the analog section 1. Power can be supplied to suppress noise generated on the board.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG.
  • End Ring guard bands 6c and 6d and ring guard bands 6a and 6b are arranged around the ring section 1 and the digital section 2, respectively.
  • the independent conductor portions 4a and 4b are connected to the positions corresponding to the analog portion 1 and the digital portion 2, respectively.
  • the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
  • the noise canceling signal generation circuit 7b is connected to the guard bands 6c and 6d of the analog section 1, and the noise canceling signal generation circuit 7a is connected to the guard bands 6a and 6b of the digital section 2. .
  • the noise cancellation signal generation circuit is composed of circuits such as an operational amplifier.
  • the inverting input terminal (1) is connected to guard bands 6c and 6a, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected. Connect to guard bands 6 d and 6 b respectively.
  • the noise canceling signal generating circuit 7b generates an optimal noise canceling signal by feedback operation so that the guard band 6c of the analog opening section 1, that is, the conductor section 4a is always at virtual ground. And apply it to guard band 6d.
  • the noise canceling signal generating circuit 7a of the digital section 2 generates an optimal digital noise canceling signal by a feedback operation and applies the signal to the guard band 6b.
  • the guard band 6a that is, the conductor portion 4b is held at the virtual ground, and the original substrate noise generated in the digital portion 2 can be eliminated.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
  • independent conductor portions 4a and conductor portions 4b are respectively connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively.
  • the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
  • a ring-shaped guard band 6a is arranged around the digital section 2, and a ring-shaped guard band 6c is arranged around the analog section 1.
  • the noise canceling signal generating circuit 7a is composed of a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor 4b of the digital section 2.
  • the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6a of the digital section.
  • the noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6a, and the conductor 4b, that is, the bottom surface of the substrate of the digital section 2 is virtually grounded. It works to keep the potential. This is because the conductor portion 4b is virtually grounded, so that the conductor portion 4b is not easily affected by parasitic elements of the external lead wiring. This is because a steady ground current does not flow compared to the case where the ground is directly grounded.
  • the substrate potential of the analog section 1 is set by grounding the guard band 6c disposed around the analog section 1 or by grounding the conductor section 4a on the bottom surface of the integrated circuit board 3 of the analog section 1. Supply a constant voltage. Even if noise remains in the conductor section 4b of the digital section 1, the influence of the board noise on the analog section 1 can be reduced by independently controlling the conductor section 4a.
  • the first substrate support member 4b is not connected to the ground wiring (GND) of the mounting substrate via the ground lead terminal of the semiconductor integrated circuit device, but is substantially referenced by the feedback operation of the amplifier circuit 7a. Virtually set to voltage (GND). At this time, even if noise is generated, the first substrate supporting member 4b generates a canceling signal having substantially the same phase and the same amplitude as that of the generated noise so that it is virtually set to the substantially reference voltage (GND).
  • the output terminal of a is applied to the first voltage control area 6a.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
  • the conductor portion 4a is connected only to the position corresponding to the analog portion 1, and the conductor portion is not formed at the position corresponding to the digital portion 2.
  • the semiconductor integrated circuit is fixed and mounted on a package via the conductor portion 4a.
  • a guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2.
  • the noise canceling signal generating circuit 7 b is configured by a circuit such as an operational amplifier, and the inverting input terminal (1) is directly connected to the conductor section 4 a of the analog section 1.
  • the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to guard band 6c of analog section 1.
  • the noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation and applies the signal to the guard band 6c, so that the conductor portion 4a, that is, the bottom surface of the analog portion 1 is virtually grounded. It works to keep the potential.
  • the substrate potential of the digital section 2 supplies a constant voltage by grounding the guard band 6a disposed around the digital section 2.
  • the conductor section 4a provided on the lower surface of the analog section 1 is virtually grounded, so that the substrate potential of the analog section 1 is directly constant. Therefore, the effect of substrate noise from the digital section can be suppressed.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 in FIG.
  • Ring-shaped guard bands 6c and 6d and ring-shaped guard bands 6a and 6b are arranged around the antenna opening section 1 and the digital signal section 2, respectively.
  • independent conductor portions 4a and 4b are connected to positions corresponding to the analog portion 1 and the digital portion 2, respectively.
  • the semiconductor integrated circuit is fixed and mounted on an insulating package via these conductor portions 4a and 4b.
  • a guard band 6c is arranged around the analog section 1, and a guard band 6a is arranged around the digital section 2.
  • the noise canceling signal generation circuits 7b and 7a are composed of circuits such as operational amplifiers.
  • the inverting input terminal (1) is directly connected to the conductor 4a of the analog unit 1 and the conductor 4b of the digital unit 2, respectively. It is connected.
  • the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is connected to the guard band 6c of the analog unit 1 and the guard band 6a of the digital unit 2.
  • the noise canceling signal generation circuit 7b always generates an optimum noise canceling signal by a feedback operation, applies these signals to the guard band 6c, and applies the conductor portion 4a, that is, the bottom surface force of the analog portion 1 to the virtual ground. It works to keep the potential.
  • the noise canceling signal generating circuit 7a always generates an optimum noise canceling signal by the feedback operation, applies these to the guard band 6a, and the conductor 4b, that is, the bottom of the substrate of the digital section 2 It works to keep the virtual ground potential.
  • An analog section 1 and a digital section 2 are formed on the integrated circuit board 3 of FIG.
  • a ring-shaped guard band 6a is arranged around the digital section 2
  • a conductor section 4 is provided on the bottom of the integrated circuit board 3, and the board bottoms of the analog section 1 and the digital section 2 are connected in common. Is done.
  • the semiconductor integrated circuit is fixed to an insulating package via the conductor portion 4 and mounted.
  • the inverting input terminal (1) of the noise canceling signal generation circuit 7a is directly connected to the conductor section 4, the non-inverting input terminal (+) is connected to the ground terminal, and the output terminal is the guard band 6a of the digital section 2. It is connected to the.
  • the noise canceling signal generation circuit 7a performs a feedback operation so that the bottom surface force of the integrated circuit board common to the conductor portion 4, that is, the analog portion 1 and the digital portion 2, is imaginary, and is always optimal. Generate a noise canceling signal and apply it to guard band 6a.
  • the signal is generated on the board of the digital section 2 by the noise canceling signal generation circuit 7a.
  • the digital noise generated is canceled out and reduced, and the substrate noise of the digital unit 2 is reduced even on the substrate of the analog unit 1, whereby a stable substrate bias potential is obtained.
  • the substrate noise generated by these digital circuit areas is generally a sum of positive and negative digital noises, and thus has a small value centered at 0. Since the noise is reduced by canceling the noise, the noise canceling signal may be a relatively small value. Therefore, the noise canceling signal generation circuit 7a can be configured with low power consumption.
  • FIG. 11 eighth and ninth embodiments of the present invention relating to the configuration of the conductor portion will be described with reference to FIGS. 11 and 12.
  • FIG. 11 eighth and ninth embodiments of the present invention relating to the configuration of the conductor portion will be described with reference to FIGS. 11 and 12.
  • a high impurity concentration layer 8a of ap + type semiconductor is provided inside or on the bottom of a low impurity concentration substrate 10 of a p-type semiconductor, which is a silicon substrate, corresponding to the analog section 1 and the digital section 2. , 8b respectively.
  • These high-concentration layers 8a and 8b serve as the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and reduce the substrate noise together with the noise canceling signal generation circuits 7a and 7b. Can be achieved.
  • the low impurity concentration substrate 14 consisting of an epitaxy layer on the high impurity concentration silicon substrate 13 of p + type semiconductor, which is a silicon bulk substrate, corresponds to the analog unit 1 and the digital unit 2.
  • the high impurity concentration buried layers 9a and 9b are formed.
  • These high impurity concentration buried layers 9a and 9b play the role of the conductor portions 4a and 4b (FIGS. 3 to 9) of the present invention, and the substrate noise together with the noise canceling signal generating circuits 7a and 7b. Can be reduced.
  • the high-concentration layers 8a and 8b or the buried layers 9a and 9b act as a conductor, Join.
  • the boards of the digital section 2 and the analog section 1 are not separated, but in combination with a noise canceling signal generation circuit, the board noise of the digital section is reduced, noise transmission is suppressed, and the board potential of the analog section is reduced. Can be kept constant.
  • the high impurity concentration layers 8a and 8b and the high impurity concentration buried layers 9a and 9b of this embodiment can be applied to the lower surface of the well of the integrated circuit to stabilize the well substrate. It can also be applied to a substrate. According to this embodiment, it is possible to always obtain the same noise suppression effect regardless of the mounting conditions.
  • the noise cancellation signal generation circuits 7a and 7b according to the embodiment of the present invention are configured on the same integrated circuit to reduce the substrate noise of the digital circuit, prevent the propagation to the analog circuit, and reduce the substrate potential of the analog circuit. It is possible to maintain the stability and improve the electrical reliability of the analog-Z digital mixed integrated circuit.
  • the present invention relates to a semiconductor integrated circuit device, in particular, an analog / digital mixed semiconductor integrated circuit in which an analog circuit (analog module) and a digital circuit (digital module) which are functional circuit units are integrated on the same semiconductor chip. It can be used to reduce the effects of noise generated by digital circuits on analog circuits via a common semiconductor substrate.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

Composant de circuit intégré à semi-conducteur permettant de solutionner les problèmes posés par la détérioration des capacités et par le mauvais fonctionnement du circuit. Comme l'illustre la figure, des bandes de garde (6a et 6b) entourant soit une section analogique (1), soit une section numérique, sont situées à l'avant d'un substrat de circuit intégré, et les sections conductrices (4a et 4b) des sections analogique et numérique (1 et 2) sont situées à l'arrière du substrat du circuit. La section conductrice (4b) de la section numérique (2) est réglée à un potentiel virtuel de mise à la terre par l'alimentation de soutien d'un circuit amplificateur (7a). Ceci permet d'éliminer le bruit du substrat produit par la section numérique (2) et de limiter l'influence du bruit numérique transmis à la section analogique (1).
PCT/JP1996/002722 1996-09-20 1996-09-20 Composant de circuit integre a semi-conducteur Ceased WO1998012750A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/002722 WO1998012750A1 (fr) 1996-09-20 1996-09-20 Composant de circuit integre a semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/002722 WO1998012750A1 (fr) 1996-09-20 1996-09-20 Composant de circuit integre a semi-conducteur

Publications (1)

Publication Number Publication Date
WO1998012750A1 true WO1998012750A1 (fr) 1998-03-26

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WO (1) WO1998012750A1 (fr)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003461A1 (fr) * 2001-06-27 2003-01-09 Renesas Technology Corp. Dispositif de circuit integre a semiconducteur et procede de reduction du bruit
US6744112B2 (en) 2002-10-01 2004-06-01 International Business Machines Corporation Multiple chip guard rings for integrated circuit and chip guard ring interconnect
JP2007514321A (ja) * 2003-12-10 2007-05-31 ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア ミックスド・シグナル集積回路のための低クロストーク回路基板
JP2007531281A (ja) * 2004-03-26 2007-11-01 ハネウェル・インターナショナル・インコーポレーテッド 混合信号についての基板クロストークを低減する技術及びｒｆ回路設計
JP2009536788A (ja) * 2006-05-08 2009-10-15 インターナショナル レクティファイアー コーポレイション 単一ダイにおいてゲートドライバー段と結合されているｐｗｍ変調器のノイズフリー技術
WO2011086612A1 (fr) * 2010-01-15 2011-07-21 パナソニック株式会社 Dispositif à semi-conducteurs
JP2014090187A (ja) * 2013-12-09 2014-05-15 Renesas Electronics Corp 半導体集積回路およびそのパターンレイアウト方法
JP2015092570A (ja) * 2001-08-10 2015-05-14 株式会社半導体エネルギー研究所 発光装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03222467A (ja) * 1990-01-29 1991-10-01 Mitsubishi Electric Corp 半導体集積回路装置
JPH05235266A (ja) * 1992-02-24 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
WO1996006460A1 (fr) * 1994-08-19 1996-02-29 Hitachi, Ltd. Dispositif semi-conducteur
JPH0884061A (ja) * 1994-09-14 1996-03-26 Hitachi Ltd 集積回路の雑音低減回路および雑音低減法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03222467A (ja) * 1990-01-29 1991-10-01 Mitsubishi Electric Corp 半導体集積回路装置
JPH05235266A (ja) * 1992-02-24 1993-09-10 Nec Ic Microcomput Syst Ltd 半導体集積回路装置
WO1996006460A1 (fr) * 1994-08-19 1996-02-29 Hitachi, Ltd. Dispositif semi-conducteur
JPH0884061A (ja) * 1994-09-14 1996-03-26 Hitachi Ltd 集積回路の雑音低減回路および雑音低減法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003461A1 (fr) * 2001-06-27 2003-01-09 Renesas Technology Corp. Dispositif de circuit integre a semiconducteur et procede de reduction du bruit
JP2015092570A (ja) * 2001-08-10 2015-05-14 株式会社半導体エネルギー研究所 発光装置
US6744112B2 (en) 2002-10-01 2004-06-01 International Business Machines Corporation Multiple chip guard rings for integrated circuit and chip guard ring interconnect
JP2007514321A (ja) * 2003-12-10 2007-05-31 ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア ミックスド・シグナル集積回路のための低クロストーク回路基板
JP2007531281A (ja) * 2004-03-26 2007-11-01 ハネウェル・インターナショナル・インコーポレーテッド 混合信号についての基板クロストークを低減する技術及びｒｆ回路設計
JP2009536788A (ja) * 2006-05-08 2009-10-15 インターナショナル レクティファイアー コーポレイション 単一ダイにおいてゲートドライバー段と結合されているｐｗｍ変調器のノイズフリー技術
WO2011086612A1 (fr) * 2010-01-15 2011-07-21 パナソニック株式会社 Dispositif à semi-conducteurs
US8450836B2 (en) 2010-01-15 2013-05-28 Panasonic Corporation Semiconductor device
JP2014090187A (ja) * 2013-12-09 2014-05-15 Renesas Electronics Corp 半導体集積回路およびそのパターンレイアウト方法

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