[go: up one dir, main page]

US6111291A - MOS transistor with high voltage sustaining capability - Google Patents

MOS transistor with high voltage sustaining capability Download PDF

Info

Publication number
US6111291A
US6111291A US09/344,338 US34433899A US6111291A US 6111291 A US6111291 A US 6111291A US 34433899 A US34433899 A US 34433899A US 6111291 A US6111291 A US 6111291A
Authority
US
United States
Prior art keywords
drain
area
region
doping
drain extension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/344,338
Other languages
English (en)
Inventor
Thomas Giebel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmos Semiconductor SE
Original Assignee
Elmos Semiconductor SE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=7872112&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US6111291(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Elmos Semiconductor SE filed Critical Elmos Semiconductor SE
Application granted granted Critical
Publication of US6111291A publication Critical patent/US6111291A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the present invention relates to a MOS transistor with high voltage sustaining capability and low closing resistance.
  • the invention relates to a PMOS transitor having a high voltage sustaining capability with low closing resistance.
  • a high-voltage PMOS-transistor with a breakthrough voltage of about 44 V is disclosed in EP-A-91 911 911. Particularly in the automative region, however, increased demands are posed to the voltage sustaining capability. Thus, for instance, it is desirable that the PMOS transistor has a voltage sustaining capability of >60, preferably about 80 V, with the additional demand that the closing resistance of this transistor is relatively low.
  • the electric field between the drain-side gate edge and the drain is decreased and the strength of the electric field on the drain-side gate edge is reduced.
  • this can be achieved in that the drain is arranged at a distance from the drain-side gate edge, and in that a so-called drain extension region is arranged between the drain region and the gate, with the drain extension region having a lower concentration of charge carriers.
  • the drain extension region is located around the drain region so that the latter is arranged within the former.
  • Such a drain extension region makes it possible, due to the relatively low concentration of charge carriers, to sufficiently decrease the electric field between the drain and the drain-side gate edge and to reduce the strength of the electric field on the gate edge to a sufficient extent.
  • the closing resistance will increase. This closing resistance can be lowered if one succeeds in gradually increasing the charge carrier concentration in the drain extension region, i. e. starting from the drain-side gate edge up to the drain region.
  • An example of such a MOS transistor with laterally modulated drain extension region is known from WO-A 97/13277.
  • Said document discloses the lateral modulation of the doping material concentration in the drain extension region by insertion of an n-ion implantation while masking at least one distance region, wherein the implantation areas separated after ion implantation will "flow into each other" by subsequent thermally induced diffusion. In these regions, the doping material concentration will thus be reduced.
  • the generation of the drain extension region has to be performed while only one ion implantation without subsequent thermally induced diffusion is available, the measures indicated in the above mentioned PCT document are not suited to realize a lateral modulation in the ion-implanted drain extension region.
  • the drain extension region could be generated by introducing a plurality of ion implantations with different energies. This, however, would require additional process steps with an inherent disadvantage.
  • an MOS transistor with high voltage sustaining capability and low closing resistance comprising:
  • a substrate comprising a doping of a first conductive type
  • a gate comprising a gate oxide layer and arranged between the source area and the drain region, the gate having drain-side end region arranged at a distance from the drain region and with a field oxide web being arranged below the drain-side end region of the gate, and
  • drain extension region comprising a doping of the first conductive type and having the drain region arranged therein, with the drain extension region reaching below the drain-side end region of the gate.
  • the above MOS transistor is characterized in
  • the drain extension region is formed by ion implantation and comprises a first partial area arranged below the field oxide web, and a second partial area joining the first partial area in the direction of the drain region and having at least a partial area of the drain region arranged therein or having the drain region bordering thereon, with the concentration of the electrically active doping of the first conductive type being smaller in the first partial area than in the second partial area of the drain extension region but larger than in the rest of the area of the drain extension region, and
  • the well area is formed by ion implantation of two partial areas spaced from each other by a distance region aligned with the the first and the second partial area of the drain extension region, and by subsequent thermally induced diffusion, wherein these two partial areas after diffusion are connected to each other within a connection region corresponding to the first and the second partial area of the drain extension region, and the concentration of the doping of the second conductive type is lower in this connection region than in the rest of the well area.
  • a classical approach is made to increase the voltage sustaining capability, i. e. a field oxide web is arranged below the drain-side gate edge. Since the ion implantation for the drain extension region is introduced after configuration of this field oxid web, the drain extension region has a smaller depth below the field oxide web than in the rest of the region; for only the higher-energy portion of the ion implantation for the drain extension region is capable of penetrating the field oxide web. Thus a relatively narrow channel connection region froms below the field oxide web via which the entire current flowing from the gate to the drain is discharged.
  • the special feature of the MOS transistor of the invention is that it has been succeeded in increasing the doping material concentration below the field oxide web and in the region between the field oxide web and the drain region within the drain extenion region without changing the ion implantation for generation of the drain extension region.
  • this is realised by a lateral modulation of the doping material concentration within the well area.
  • this well area is generated by implantation of two partial areas which are spaced from each other by a distance region. The location of this distance region corresponds to that region in which the field oxide web and the distance region between field oxide web and drain area is arranged.
  • the MOS transistor of the invention comprises two partial areas with different doping material concentrations in the region of its drain extension region, which is arranged between the drain-side end region of the gate and the drain area.
  • the first partial area is arranged below the field oxide web whereas the second partial area is arranged between said first partial area and the drain area or the drain area extends at least into said second partial area.
  • the concentration of electrially active doping smaller than in the second partial area. The reason for this is that the first partial area is covered by the field oxide web during ion implantation for the drain extension region and thus in the first partial area only a smaller portion of ion implantation can be introduced than in the second partial area.
  • the concentration of electrically active doping in the first partial area is larger than in the remaining drain extension region, except for the second partial area.
  • the reason for this is that the doping material concentration of the well area in the region corresponding to the two partial areas of the drain extension region is reduced by masking (distance area). On the whole this results in a doping material concentration modulation both in vertial and lateral direction within the two partial areas of the drain extension region.
  • a region of the drain extension region is generated which possesses a higher concentration of electrically active doping which has a positive effect on the closing resistance of the MOS transistor.
  • it is of advantage to the closing resistance that the second partial area of the drain extension region adjacent to the field oxide web displays a concentration of electrically active doping further increased as compared with that of the first partial area.
  • drain extension region Due to masking the well area a vertical and lateral modulation of the concentration of electrically active doping of the drain extension region is achieved for a MOS transistor with field oxide web below the drain-side end region of the gate, without the drain extension region having to be generated by means of an ion implanation comprising locally different energies.
  • the drain extension area can rather be configured with the aid of an ion implantation remaining constant over its overall surface. Thus the production process need not be modified as far as the drain extension ion implantation is concerned. Merely masking of the well area is required during introduction of the ion implantation, which, however, has no effect on the production process.
  • the classical approach to increase the voltage sustaining capability is applied to the MOS transistor of the invention, according to which besides a drift interval (drain extension) also a field plate in the drain-side end region of the gate is provided for equalization of the electrical field.
  • a one-piece or two-piece p-doping implantation of a LOCOS process is used as drain extension, which, however, should not be employed unconsidered due to the excessively steep profile.
  • the distictive maximum in this profile causes a field strength peak at the drain-side gate edge, which leads to premature breakthrough of the conventional HV-PMOS.
  • the classical approach of using a field plate is selected: In the area of the drain-side gate edge a field oxide web is produced so that the drain-side gate edge is located in the middle of this web. Thus the field strength peak lies in the field oxide and has no influence on the silicon.
  • the duct connection is ensured by the p-doping implantation extending into the channel area. This overlapping should amount to at least 0.5 ⁇ m to about 1 ⁇ m in order to guarantee that the pn-transition between implantation region and well displays an adequate distance to the active region edge of the field oxide web. Otherwise a critical field strength peak will occur again at this edge.
  • the field oxide web should be as narrow as technically possible to keep this high-resistive part of the drift interval as short as possible. In this connection it must be taken into consideration that in this way the field oxide thickness is also reduced which, in turn, leads to an increas in the field strength.
  • the electrically active doping is determined by two doping materials, boron and phosphorus
  • the well implantation in the area of the field oxide web is masked out.
  • the two well parts are reconnected by diffusion and a lower phosphorus concentration is thus achieved in this area.
  • the excess in the phosphorus concentration below the field oxide is no longer as high as previously due to segregation. For this reason the electrically active doping and thus the conductivity of the drift interval below the field oxide rises in the subsequent boron implantation by that amount by which the phosphorus concentration has been decreased, i. e. about 30-50%.
  • the sequence of a process for production of a transistor according to the invention configured as PMOS transistor comprises, for example:
  • FIGS. 1 to 3 show cross-sections of the near-to-surface region of a p-substrate in different phases of the production process for a voltage-proof PMOS transistor with low closing resistance
  • FIGS. 4 to 6 show doping material concentration patterns at locations of the p-substate marked in FIGS. 2 and 3.
  • FIG. 1 shows a p-substrate 10 with two n-ion implantation areas 16, 18, spaced from each other by a distance region 14, introduced into the surface 12 of said areas.
  • the two areas 16, 18 will flow together to form the n-well area 20 as shown in FIG. 2.
  • the connection region 22 corresponding to distance region 14 a reduced depth of n-well area 20 as well as a reduced phosphorus doping material concentration will be generated in the process. This is evident from the two curves in FIG. 4 and from curve 3 in FIG. 5.
  • the doping material concentration profile resulting in the depth direction of n-well 20 outside connection region 22 is indicated by curve 1 as the amount of the doping material concentration.
  • the concentration decreases towards the bottom of n-well area 20 (p-n-transition a of FIG. 2) and then, with increasing progress into the depth of the p-substrate 10, takes on the doping material concentration of the latter.
  • FIG. 3 shows the situation after introduction of the drain extension region 24 and configuration of the source area 26 as well as the drain area 28 arranged within the drain extension region 24.
  • the field oxide 30 and the gate oxide 36 with field plate 37 of the gate 32 have already been configured.
  • the configuration of this oxide layers takes place at the same time as the thermally induced diffusion of the well area 20.
  • the gate electrode 34 shown in FIG. 3 is not yet configured at this time, but it is shown in FIG. 3 for the sake of completeness.
  • the two partial areas 38 and 44 correspond to the region c of the well area 20 within the drain extension region 24.
  • the partial area 38 is spaced from the drain-side gate edge 42 by distance 40 with the field plate 37 being arranged below the gate edge 42 and the field plate 37 extending on both sides of this drain-side gate edge 42 both further below the gate 32 and towards the drain area 28.
  • the reason for this is that owing to the field oxide web 37 a smaller amount of doping materials are fed to the region 44 during the ion implantation of the drain extension region 24 than to the region 38 and that the region (c) of the well area 20 corresponding to the two partial areas 38 and 44 has a lower concentration of doping materials (in this case phosphorus concentration) due to the masking. Since, however, the phosphorus concentration in the region c of the well area 20 is on the whole lower than in the rest of the region of the well area 20 an increased concentration of electrically active doping materials occurs in the two partial areas 38 and 44 of the drain extension region as compared with the rest of the part of the drain extension region 24.
  • a threshold voltage ion implantation may be introduced below the gate 32 in the substrate 10 in the case of the transistor according to FIG. 3. This implantation is appropriately masked in the transition region between the gate oxide layer 36 and the field oxide web 37. Said threshold voltage implantation serves for adjustment of the threshold voltage of the transistor and is appropriately also introduced in the rest of the exposed upper side of the drain extension area 24, i. e. in particular in the area 38, to ensure here increase of the conductivity.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Logic Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
US09/344,338 1998-06-26 1999-06-25 MOS transistor with high voltage sustaining capability Expired - Lifetime US6111291A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19828520 1998-06-26
DE19828520 1998-06-26

Publications (1)

Publication Number Publication Date
US6111291A true US6111291A (en) 2000-08-29

Family

ID=7872112

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/344,338 Expired - Lifetime US6111291A (en) 1998-06-26 1999-06-25 MOS transistor with high voltage sustaining capability

Country Status (4)

Country Link
US (1) US6111291A (fr)
EP (1) EP0973205B1 (fr)
AT (1) ATE267461T1 (fr)
DE (1) DE59909507D1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6309053B1 (en) * 2000-07-24 2001-10-30 Hewlett-Packard Company Ink jet printhead having a ground bus that overlaps transistor active regions
US6476457B2 (en) * 1999-05-10 2002-11-05 Hyundai Electronics Industries Co, Ltd. Semiconductor device with drift layer
WO2002102597A3 (fr) * 2001-06-19 2003-03-27 Hewlett Packard Co Tete d'impression a jet d'encre compacte
US6543883B1 (en) 2001-09-29 2003-04-08 Hewlett-Packard Company Fluid ejection device with drive circuitry proximate to heating element
US20050253217A1 (en) * 2004-04-26 2005-11-17 Texas Instruments, Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
JP2007535139A (ja) * 2004-02-27 2007-11-29 オーストリアマイクロシステムズ アクチエンゲゼルシャフト 高電圧ｐｍｏｓトランジスタ

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5307973B2 (ja) 2006-02-24 2013-10-02 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP4989085B2 (ja) * 2006-02-24 2012-08-01 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
EP2987682B1 (fr) 2014-08-20 2020-12-16 Nexans Agencement pour des conduites électriques montées dans un véhicule automobile

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE536227C (de) * 1930-03-02 1931-10-21 Magdeburger Werkzeugmaschinenf Spanabweiser fuer schnellaufende Drehbaenke
US5541435A (en) * 1992-05-12 1996-07-30 Harris Corporation Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
US5548147A (en) * 1994-04-08 1996-08-20 Texas Instruments Incorporated Extended drain resurf lateral DMOS devices
US5977590A (en) * 1998-01-14 1999-11-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having insulation gate type field effect transistor of high breakdown voltage
US5981997A (en) * 1996-03-22 1999-11-09 Fuji Electric Co., Ltd. Horizontal field effect transistor and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368581A (en) * 1976-12-01 1978-06-19 Hitachi Ltd Semiconductor device
JPS62274767A (ja) * 1986-05-23 1987-11-28 Fujitsu Ltd 高耐圧半導体装置及びその製造方法
JPH0730107A (ja) * 1993-07-13 1995-01-31 Sony Corp 高耐圧トランジスタ及びその製造方法
DE19536753C1 (de) * 1995-10-02 1997-02-20 El Mos Elektronik In Mos Techn MOS-Transistor mit hoher Ausgangsspannungsfestigkeit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE536227C (de) * 1930-03-02 1931-10-21 Magdeburger Werkzeugmaschinenf Spanabweiser fuer schnellaufende Drehbaenke
US5541435A (en) * 1992-05-12 1996-07-30 Harris Corporation Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps
US5548147A (en) * 1994-04-08 1996-08-20 Texas Instruments Incorporated Extended drain resurf lateral DMOS devices
US5981997A (en) * 1996-03-22 1999-11-09 Fuji Electric Co., Ltd. Horizontal field effect transistor and method of manufacturing the same
US5977590A (en) * 1998-01-14 1999-11-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having insulation gate type field effect transistor of high breakdown voltage

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476457B2 (en) * 1999-05-10 2002-11-05 Hyundai Electronics Industries Co, Ltd. Semiconductor device with drift layer
US6309053B1 (en) * 2000-07-24 2001-10-30 Hewlett-Packard Company Ink jet printhead having a ground bus that overlaps transistor active regions
WO2002102597A3 (fr) * 2001-06-19 2003-03-27 Hewlett Packard Co Tete d'impression a jet d'encre compacte
AU2001292592B2 (en) * 2001-06-19 2006-04-06 Hewlett-Packard Development Company, L.P. Compact ink jet printhead
US6543883B1 (en) 2001-09-29 2003-04-08 Hewlett-Packard Company Fluid ejection device with drive circuitry proximate to heating element
JP2007535139A (ja) * 2004-02-27 2007-11-29 オーストリアマイクロシステムズ アクチエンゲゼルシャフト 高電圧ｐｍｏｓトランジスタ
US20050253217A1 (en) * 2004-04-26 2005-11-17 Texas Instruments, Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
EP1592069A3 (fr) * 2004-04-26 2008-04-23 Texas Instruments Inc. Transistor haute tension à effet de champ et sa méthode de fabrication
US7498652B2 (en) 2004-04-26 2009-03-03 Texas Instruments Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof
US20090124068A1 (en) * 2004-04-26 2009-05-14 Texas Instruments Incorporated Non-Uniformly Doped High Voltage Drain-Extended Transistor and Method of Manufacture Thereof
US7618870B2 (en) 2004-04-26 2009-11-17 Texas Instruments Incorporated Non-uniformly doped high voltage drain-extended transistor and method of manufacture thereof

Also Published As

Publication number Publication date
DE59909507D1 (de) 2004-06-24
EP0973205A3 (fr) 2001-07-25
EP0973205A2 (fr) 2000-01-19
EP0973205B1 (fr) 2004-05-19
ATE267461T1 (de) 2004-06-15

Similar Documents

Publication Publication Date Title
EP2259327B1 (fr) Dispositif semi-conducteur de puissance à grille isolée et diode Schottky et procédé de fabrication correspondant
US8828810B2 (en) Method of producing a semiconductor including two differently doped semiconductor zones
US6111291A (en) MOS transistor with high voltage sustaining capability
KR101571615B1 (ko) 반도체 장치 및 반도체 장치의 제조 방법
EP3509102A1 (fr) Composant intégré à un transistor à effet de champ à jonction à mode appauvrissement et procédé de fabrication de composant
US9711621B2 (en) Trench transistor having a doped semiconductor region
US20160126350A1 (en) Ldmos transistors for cmos technologies and an associated production method
US5981342A (en) Method of making a semiconductor component with compensation implantation
US9786779B2 (en) High voltage double-diffused MOS (DMOS) device and method of manufacture
GB2374456A (en) High-voltage metal oxide semiconductor device and method of forming the device
KR20050034548A (ko) 반도체 장치 및 그 제조 방법
US20020197860A1 (en) Smart power device and method for fabricating the same
US6608336B2 (en) Lateral double diffused MOS transistor
US5482888A (en) Method of manufacturing a low resistance, high breakdown voltage, power MOSFET
US7781809B2 (en) High voltage depletion layer field effect transistor
KR100826714B1 (ko) 고전압 ｐｍｏｓ 트랜지스터
US7898030B2 (en) High-voltage NMOS-transistor and associated production method
US7750428B2 (en) Semiconductor device and method for producing it
US6093949A (en) MOS transistor
EP1890336B1 (fr) Dispositif à transistor MOS à haute tension et sa méthode de fabrication
US20240222527A1 (en) Breakdown diodes and methods of making the same
KR100343790B1 (ko) 표류층 내부로 웰이 확장된 고압소자
WO2022091218A1 (fr) Dispositif à semi-conducteur, dispositif de conversion de puissance, et procédé destiné à la fabrication d'un dispositif semi-conducteur
JPH09260661A (ja) トランジスタおよびその製造方法
JP2002289874A (ja) 半導体装置および半導体装置を用いた回路

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12