US3373362A - Static counter incorporating stages having main and auxiliary stores - Google Patents

Description

March 12, 1968 D. PETZOLD 3,373,362

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\efe Peizold United States Patent Ofilice 3,373,362 STATIC COUNTER INCORPORATING STAGES HAVING MAIN AND AUXILIARY STORES Dieter Petzold, Berlin-Neulrolln, Germany, assignor to Licentia Fatent-Verwaltungs-Gm.l).H., Frankfurt am Main, Germany Filed Apr. 5, 1965, Ser. No. 445,565 Claims priority, application Germany, Apr. 3, 1964,

4 Claims. ci. 328-41) ABSTRACT OF THE DISCLQSURE The present invention relates to a static counter and, more particularly, to a static counter of the type disclosed in my copending application Ser. No. 327,585, filed Nov. 29, 1963.

The counter shown in application Ser. No. 327,585, is a binary counter capable of counting forward or backward, which may be provided with means for converting the counter into a decimal counter, and which has a plurality of counter stages each incorporating two memory units, namely, a main storage device and an auxiliary storage device, termed main and auxiliary stores, respectively. The counter is controlled by means of counting signals and auxiliary counting signals which may have any suitable wave shape, these counting signals and auxiliary counting signals being time displaced, i.e., staggered with respect to each other in the sense that they do not change their states (L or O, with L being used to represent the binary one) simultaneously. The counter described in application Ser. No. 327,585, has the counting signals applied in parallel to the main stores of all of the counter stages while the auxiliary counting signals are applied in parallel to the auxiliary stores of all of the counter stages. All that is required of the counting signals and auxiliary counting signals is that they be of suflicient amplitude and duration. Furthermore, the timely staggered counting signals and auxiliary counting signals will generally appear with time intervals between them, i.e., there will be a time interval between a given counting signal t and the corresponding auxiliary counting signal t Any faults or disturbances which cause any counting signal or auxiliary counting signal repeatedly to appear or to disappear, as, for example, shocks resulting from mechanical contacting or by oscillations of the signal generator, will not cause the counter to produce an incorrect count.

One drawback of the counter described in application Ser. No. 327,585 is that, under certain circumstances, one of the counting signals or auxiliary counting signals applied to the counter may have such a small amplitude, and/or be of such short duration, that the counter will will not properly process such signal. Since, as explained above, the signal trains are applied in parallel to the main and auxiliary stores of the counter stages, it may happen that one or more of the main or auxiliary stores will not properly respond to such signal, while the remaining main or auxiliary stores do respond properly. That is to say, it may be that a given signal may be just small enough, or just short enough, so that some of the stores to which it is applied will not respond but that others will. Consequent- 3,373,362 Patented Mar. 12, 1968 ly, the appearance of such an inadequate signal will cause the counter to put out an incorrect count.

It is, therefore, the primary object of the present invention to provide a way in which to overcome the above drawback and with this object in view, the present invention resides in a counter which is basically of the abovedescribed type in that it incorporates stages having main and auxiliary stores, of which the main store puts out the count of the particular digit, but wherein, in contradistinction to the counter described in application Ser. No. 327,585, the counting signals and auxiliary counting signals are applied to the main and auxiliary stores, respectively, of the lowest-order counter stage only. New counting signals and auxiliary counting signals 7' T2, are then derived from the output signals of the main and auxiliary stores of the lowest-order counter stage, and these new signals are then applied in parallel to the main and auxiliary stores, respectively, of all higher-order counter stages. The counter will, of course, be so designed that the new counting and auxiliary counting signals 7 T2 will unquestionably be fully adequate, i.e., of suflicient amplitude and duration, to control all of the higher-order stages.

Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompanying drawings in which:

FIGURE 1 is a schematic circuit diagram showing the first four stages of one embodiment of a counter according to the present invention, the same being a forward counting binary counter having non-identical counter stages.

FIGURE 2 is a schematic circuit diagram showing the first four stages of another embodiment of a counter according to the present invention, the same being a forward counting counter having identical counter stages.

FIGURE 3 is a schematic circuit diagram showing the 0th decade of a forward counting counter, the same including four binary stages which are not all identical to each other.

FIGURE 4 is a schematic circuit diagram showing the 0th decade of a forward counting counter, the same including four identical binary stages.

FIGURE 5 is a schematic circuit diagram showing the first four stages of still another embodiment of a counter according to the present invention, the same being a backward counting counter having non-identical counter stages.

FIGURE 6 is a schematic circuit diagram showing the first four stages of yet another embodiment of a counter according to the present invention, the same being a backward counting counter having identical counter stages.

FIGURE 7 is a schematic circuit diagram showing the 0th decade of a backward counting counter, the same including four binary stages which are different from each other.

FIGURE 8 is a schematic circuit diagram showing the 0th decade of a backward counting counter, the same including four identical binary stages.

FIGURES 9a and 9b are schematic circuit diagrams of arrangements for producing the new counting signals 7'1 and auxiliary counting signals T2.

FIGURES 10a, 10b, 100, 11a, 11b and 110 are schematic circuit diagrams of arrangements for producing compensating signals which make it possible to provide the counter with identical counter stages, the signals produced by the circuits of FIGURES 10a and 1% being used in conjunction with the counter of FIGURE 2, the signals produced by the circuits of FIGURES 10a, 10b and being used in conjunction with the counter of FIGURE 4, the signal produced by the circuits of FIG- URES 11a and 11b being used in conjunction with the 3 counter of FIGURE 6, and the signals produced by the circuits of FIGURES 11a, 11b and llc being used in conjunction with the counter of FIGURE 8.

FIGURE 12 is a time plot showing various signals applied to and produced by the counters of FIGURES 1 and 2.

FIGURE 12a is a schematic circuit diagram of a natural binary code counter of the type shown in application Serial No. 327,585, namely, a counter in which the counting signals and auxiliary counting signals t t are applied in parallel to all of the stages of the counter. This counter, and its operation, are set forth to facilitate the explanation of the present invention.

FIGURES 13a, 13b, 13c and 13d are time plots showing the timed relationship between various signals in the counter of FIGURE 12a.

FIGURES 14a, 14b, 14c and 14d are, respectively, schematic circuit diagrams of means for producing signals used in the counter of FIGURE 12a.

In each of the various circuit diagrams, the AND- circuits are identified by & (in some cases with subscripts) and the OR-circuits by v, and in each case the black bar represents the presence of an inverse or complement, i.e., a negated, output. Various ones of the circuits also include pure inverter or so-called NOT- circuits, these being circuits at which the output is the inverse, that is to say, the negate, or complement, of the input, namely, when the input is L and L when the input is O.

In the time plots, only the afiirmative signals are shown, in the interests of simplicity and clarity. That is to say that, for example, only the signals I but not the negates 7 thereof, are shown. Also, the signals are shown as having a rectangular wave form although in practice the wave form need not necessarily be square. As a matter of expediency, the abscissa of each signal represents the value 0 while the lines overlying the abscissa represent the binary one or L.

For purposes of explanation, reference will be made to the static counter shown in application Ser. No. 327,585, one embodiment of which is depicted in FIGURE 12a of the accompanying drawings. FIGURE 12a shows the first four counter stages of a binary counter made up of identical counter stages, each incorporating a main store S and an auxiliary store S Each store is identified by an appropriate subscript, e.g., S 8 The stores are constituted by input AND-circuits whose outputs are connected to OR/NOT/NOT-circuits. All of the stores are galvanically coupled to each other. The configuration or wave shape of the applied input signals is of no consequence; all that is necessary is that the input signals have certain predetermined amplitudes.

There will now be described the operation of the counters as well as the signficance of the various signals.

The counter has applied to it the actual counting signals 1 as well as auxiliary counting signals t the signals t and t being staggered or time-shifted with respect to each other, i.e., the signals t and t occur at different times and, as shown graphically in FIGURE 13a, there are time intervals between the signals t and t The signals themselves, as well as the time intervals therebetween, may be of different durations. If the timed relationship between the signals 2 and t; is as depicted in FIGURE 13b, t can be used as the counting signal and T as the auxiliary counting signal. If the timed relationship between the signals t and I is as shown in FIGURE 13c, two AND-circuits can be used for producing two signals (t & t and & t which are staggered with respect to each other and between which there is a time interval. The repeated disappearance and reappearance of the t-signalsas depicted in FIGURE 13d and as might be produced by shocks or vibrations to which the pulse generator is subjected-will not adversely influence the operation. The signal trains identified in FIGURE 13d at a, will each be considered, by the counter, as one counting signal, comparable to the signals a, of FIGURE 13a. The same applies to the signal trains 11 each of which will be considered by the counter as an auxiliary counting signal.

The A-signals represent the number of counting signals t registered by the counter. The H-signals are auxiliary signals which are formed by the counter itself and which assist the function of the counter. As explained above, the A-signals and H-signals of the binary counter are identified by subscripts. The signal A, (i=0, 1, 2, 3, of the binary counter thus has the value 2 Before the start of a counting operation, the counter is put into a definite starting position by means of an erase or reset signal l=L. During the counting operation, the reset signal 1:0. For purposes of simplification, those signals which in each counter stage together act on one AND-stage, are separately combined. The counters therefore have applied to them t'-signals which are derived from the t-signals and the negated reset signal I by means of the circuits shown in FIGURES 14a, 14b and 140. The e-signal produced by the circuit of FIGURE 14d is provided solely so that the auxiliary store of the counter stage of the lowest order is constituted by circuitry similar to that of the auxiliary stores of the higher-order counter stages. The circuit shown in FIGURE 14d comprises two input AND-circuits whose outputs are connected to an OR/NOT-circuit. One of the AND-circuits has applied to it the negate of a counting command signal z by means of which the counter is made to count (when z=L) or not to count (when z=0). (The single-input AND-circuit just referred to, as well as other single-input logic circuits which are part of circuitry referred to throughout the following description, are provided for purposes of electrical symmetry.) The other AND-circuit has applied to it the signals A and 1 The signal Z is derived from the z-signal, which may appear at any time, and a signal 22 is derived from the signal Z such that Z2 can change its state only at the start of an auxiliary counting signal t;,, as explained in the mentioned application Ser. No. 327,585. The signal Z serves as a clear-for-counting signal, i.e., the t -signals are counted only so long as z =L. So long as 2 :0, the counter remains at whatever count it has reached. The counter can be preset to any desired starting number by means of preset signals k, the same being identified by subscripts and superscripts in a manner analogous to that in which the A and H signals are identified, as explained above. The k-signals are accepted by the counter when a clear-for-presetting signal f=L. Since the f-signal disappears at the start of the counting operation, a new number to which the counter may later be preset can be made ready during the counting opera tion. If no presetting is required, the means by which the presetting is accomplished can be dispensed with.

Referring next to FIGURE 1, the same shows a forward counting binary counter according to the present invention, whose lowest-order counter stage Z incorporating the main store S and the auxiliary store S is, in principle, similar to the corresponding stage of the corresponding counter disclosed in application Ser. No. 327,585, in that the main store S has the counting signal t and its negate I; applied to it while the auxiliary store S has the auxiliary counting signal 1 and its negate T applied to it.

According to the present invention, new counting signals 7'1 and new auxiliary counting signals T2, as well as their respective negates are derived from the counter stage Z which new signals are applied in parallel to the stores of the higher-order counter stages Z Z Z More particularly, the new -r-signals are derived from the outputs of the main and auxiliary stores of the lowest-order counter stage. Various inputs of the counter stages are provided with two references; in FIG- URE 1, for example, a line 1 is referenced a, l. The corresponding signals can be combined in separate AND- circuits. The same applies to the other counters to be described.

FIGURE 9a shows an AND/NOT/NOT-circuit for producing the new counting signals T1 and the correspon ing negatesT The circuit of FIGURE 9a has two inputs to which are applied, respectively, the negated output signal K of the main store of the lowest-order counter stage and the output signal H of the corresponding auxiliary store. The new auxiliary counting signals 1- and their corresponding negates 1- are produced by the AND/NOT/NOT-circuit shown in FIGURE 9b, which has two inputs to which are applied, respectively, the output signal A of the main store of the lowest-order counter stage and the negated output signal I l of the corresponding auxiliary store. The new counting signals and auxiliary counting signals T1, 7- are of longer duration than the original input counting signals and auxiliary counting signals t t and appear but half as frequently as do the signals t.

If, now, an inadequate counting signal t or auxiliary counting signal t is produced by the signal generator (not shown), the same is applied only to the main or auxiliary store of the counter stage Z Such a signal can have but one of two possible effects; either the counter stage Z will respond properly and change its state, or it will not. It, then, such inadequate signal is picked up by the stage Z in the same way as an adequate or nonfaulted signal would be, the same will be processed by the stage and the new counting signals 7- and auxiliary counting signals T2 derived from the outputs of the stage Z will be routinely processed by all of the higher-order counter stages. If, on the other hand, the lowest-order counter stage Z does not respond to the inadequate signal, the output signals at A and H remain unchanged and consequently no new counting signals and auxiliary counting signals will be produced. This means that the higherorder stages will not be affected in any way.

While in the counter of FIGURE 1, the auxiliary stores S and 8 of the counter stages Z and Z are not identical to the auxiliary stores 8 and S of the counter stages Z Z the counter of FIGURE 2 is so constructed as to have identical counter stages, the counter of FIG- URE 2 being a forward counting binary counter whose first four counter stages are illustrated. In order to enable all of the counter stages to be made up of identical components, the auxiliary stores S and 8 have compensating signals e and e applied to them. These signals are derived in the circuits shown in FIGURES 10a and 10b, respectively, the former comprising two input AND- circuits & & and one OR/NOT-circuit v the AND- circuits having the signals t and K applied to them, as shown, and the circuit of FIGURE b comprising an AND/NOT-circuit & which has the signals T2 and K applied to it. With the counter being used in conjunction with the circuits of FIGURES 10a and 10b as well as those of FIGURES 9a and 9b all of the counter stages can be identical to each other, thereby allowing the use of modular components.

FIGURE 3 is a schematic circuit diagram showing the first four binary stages of the 0th stage of a forward counting decimal counter, which puts out, as its count, a decimal number in binary coded form. As in the case of the counter of FIGURE 1, from which the counter of FIGURE 3 is derived, only the lowest-order counter stage Z has the counting signals and auxiliary counting signals t t applied to it. The new counting signals and auxiliary counting signals 1 T2, are then derived from the outputs of the main and auxiliary stores of the lowest-order counter stage and these signals are applied to the higherorder counter stages, in the manner described above.

FIGURE 4 is a schematic circuit diagram showing the first four binary stages of the 0th stage of another forward counting decimal counter which differs from those depicted in FIGURE 3 in that all of the counter stages are identical to each other. In order to make this possible, the auxiliary stores S and S have the compensating signals e e 2 applied to them, the first and second of which are derived in the circuits shown in FIGURES 10a and 1012, as described above, the third being derived in the circuit shown in FIGURE 10c which comprises an AND/NOT-circuit 8: to which the signals 7'2 and K are applied.

FIGURE 5 is a schematic circuit diagram of a backward counting binary counter having non-identical counter stages. As in the case of the counters described above, only the main and auxiliary stores S and S have the counting signals and auxiliary signals t t applied to them, the outputs of these stores being used to derive the new counting signals and auxiliary counting signals T1, T2, which are then applied in parallel to the main and auxiliary stores of the higher-order counter stages.

The counter shown in FIGURE 6 differs from that of FIGURE 5 in that the counter stages are identical to each other. Accordingly, the auxiliary stores S and have the compensating signals 2 and 2 applied to them; the signal e is formed in the circuit shown in FIGURE 1111 which comprises two input AND-circuits & and 8: whose outputs are connected to an OR/NOT-circuit v the input AND-circuits having the signals 5 t and A applied to them, as illustrated. The signal c is formed in the circuit shown in FIGURE 11b which comprises an AND/NOT-circuit 8: to which the signals T and A are applied.

The counter shown in FIGURE 7 is the 0th decade of a backward counting decimal counter, the same being based on the counter of FIGURE 6, so that here, too, only the 0th counter stage will have the counting signals and auxiliary counting signals t t applied to it, the new counting signals and auxiliary counting signals 7- 1 which are applied in parallel to the higher-order counter stages, being derived from the outputs of the main and auxiliary stores of the lowest-order counter stage Z As is apparent from FIGURE 7, the counter stages are not identical.

The counter of FIGURE 8 differs from that of FIG- URE 7 in that the counter stages are identical, the auxiliary stores S S S having the compensating signals 2 c e applied to them. The signals e and c are derived in the circuits show in FIGURES 11a and 1112, respectively, the signal e being derived in the circuit shown in FIGURE 11c which comprises two input AND- circuits 8: and 8: whose outputs are connected to an OR/NOT-circuit v The two input AND-circuits have the signals A v and H applied to them, as illustrated.

FIGURE 12 is a time plot showing the operation of the counters of FIGURES l and 2. The signals A and H are set and erased in the same manner as in the counters described in application Ser. No. 327,585, i.e., when, between any two auxiliary counting signals, there appears at least one counting signal of adequate amplitude and duration, or when, between any two counting signals, there appears at least one auxiliary counting signal of adequate amplitude and duration. The time plot lines bracketed by (a) represent the case where it is assumed that all of the applied counting signals and auxiliary counting signals t t are adequate and therefore properly registered and processed, while the time plot lines bracketed by (b) represent the case where it is assumed that the third counting signal t (3') is inadequate, i.e., of insutficient amplitude and/or duration, to be considered as a counting signal by the lowest-order counter stage Z The first signal A will appear upon the occurrence of the first counting signals 1', and the first signal H will appear upon the occurrence of the first auxiliary counting signal I". The new signals T1,7'2 are then formed and are used for controlling the higher-order counter stages. As explained above and as is apparent from FIGURES 9a and 9b, the new counting signal 1- is derived from the signal K and the signal H while the new auxiliary counting signal 7 is derived from the signal A and the signal E There will be a time gap between the signals T1, 1- The time plot further shows that the signal A of the next higher-order counter stage is not put out until there is a signal T1. The main store which produces this signal A is thus set with the appearance of a signal 7 Only thereafter can the auxiliary store of this counter stage, which produces the signal H be set, and this occurs upon appearance of a signal '1 In the time plot as shown in FIGURE 12, the first signal 7 has no effect on the counting operation, because only after the signal A has been formed can a signal 1- produce a signal H The time plots shown in the lines bracketed by (b) are identical up to the point represented by the vertical dashed line, which passes through the third counting signal 3 and which, as set forth above, is a signal which is inadequate for purposes of being treated as a counting signal by the lowest-order counter stage. As a result, the third counting signal t identified at 3, produces no signal A in consequence of which no signal H will appear upon the occurrence of the following t -signal 3". The signal A will, in fact, not appear until the application of the fourth t -counting signal 4', so that the next H -signal will not appear until the application of the next auxiliary counting signal t this being the auxiliary counting signal identified at 4".

A comparison between the lines bracketed by (a) and (b) will show that, in case (a), the count of the counter will, upon the application of the fourth t -signal, be four, while in case (b), where the third counting signal 3' had no eflect, the count of the counter will be only three.

It will thus be seen that, in accordance with the present invention, there is provided a counter responsive to timely displaced counting signals and auxiliary counting signals t t which counter comprises a plurality of identical or non-identical counter stages each having a main store and an auxiliary store, each of which stores is provided with input means for receiving counting signals and auxiliary counting signals. Means are provided for applying the counting signals and auxiliary counting signals t t only to the main store and auxiliary store, respectively, of the lowest-order counter stage, and for deriving new counting signals and auxiliary counting signals 1- 7' from the outputs of the main and auxiliary stores of the lowestorder counter stage. These new counting signals and auxiliary counting signals are then applied in parallel to the main and auxiliary stores, respectively, of all higher-order counter stages. As is apparent from FIGURES 9a and 9b, the new counting signals 7' are derived in logic circuits having the following logic functions:

It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

, What is claimed is:

1. A static counter responsive to timely displaced counting signals and auxiliary counting signals t t said counter comprising, in combination:

(a) a plurality of counter stages each having a main store and an auxiliary store, each of said stores being provided with input means for receiving counting signals and auxiliary counting signals;

(b) means for applying the counting signals and auxiliary counting signals r r only to the main store and auxiliary store, respectively, of the lowest-order counter stage;

(0) means for deriving new counting signals and auxiliary counting signals 1- T2, from the outputs of said main and auxiliary stores of said lowest-order counter stage; and

(d) means for applying said new counting signals and auxiliary counting T1, T2 in parallel to the main and auxiliary stores, respectively, of all higher-order counter stages.

2. A counter as defined in claim 1 in which T1:(ZO&HO) and =(A &H wherein A and K are the output and negated output signals of said main store of said lowest-order counter stage and H and i are the output and negated output signals of said auxiliary store of said lowest-order counter stage.

3'. A counter as defined in claim 1 wherein said counter stages are non-identical.

4. A counter as defined in claim 1 wherein said counter stages are identical.

References Cited UNITED STATES PATENTS 3,218,532 11/1965 Toscano 31828 ARTHUR GAUSS, Primary Examiner.

STANLEY MILLER, 1a., Assistant Examiner.

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